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Thu, 14 Nov 2019 19:13:23 +0000 From: Srinath Parvathaneni To: "gcc-patches@gcc.gnu.org" CC: Richard Earnshaw , Kyrylo Tkachov Subject: [PATCH][ARM][GCC][5/5x]: MVE ACLE load intrinsics which load a byte, halfword, or word from memory. Date: Thu, 14 Nov 2019 19:16:00 -0000 Message-ID: References: <157375666998.31400.16652205595246718910.scripted-patch-series@arm.com> In-Reply-To: <157375666998.31400.16652205595246718910.scripted-patch-series@arm.com> Authentication-Results-Original: spf=none (sender IP is ) smtp.mailfrom=Srinath.Parvathaneni@arm.com; X-MS-Exchange-PUrlCount: 1 x-ms-exchange-transport-forked: True x-checkrecipientrouted: true x-ms-oob-tlc-oobclassifiers: OLM:7219;OLM:7219; X-Forefront-Antispam-Report-Untrusted: SFV:NSPM;SFS:(10009020)(1496009)(4636009)(39860400002)(396003)(366004)(376002)(346002)(136003)(54534003)(199004)(189003)(81156014)(316002)(81166006)(30864003)(2501003)(44832011)(4326008)(74316002)(7696005)(99286004)(478600001)(186003)(11346002)(26005)(54906003)(76176011)(52536014)(5660300002)(446003)(25786009)(71190400001)(71200400001)(33656002)(66946007)(52116002)(305945005)(66556008)(7736002)(66446008)(66476007)(66616009)(64756008)(14444005)(256004)(5024004)(9686003)(966005)(5640700003)(3846002)(66066001)(6916009)(86362001)(486006)(6506007)(6436002)(14454004)(8936002)(2906002)(6116002)(2351001)(55016002)(8676002)(102836004)(386003)(476003)(6306002)(579004)(559001)(569006);DIR:OUT;SFP:1101;SCL:1;SRVR:DBBPR08MB4807;H:DBBPR08MB4775.eurprd08.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: buP4txvSz9yJFN/b7wesaRHUp/3chRp4215uEA8ToyAEhamRkBPbC/pr5pg/vxh9eVJu475R7Szf/2CoulfN6/u4tV0cOKQWje6mt1P1/5d2Xpo1SQ4thVGqMmru9wonLXKjWJprhDM3dqvrmFIh1SMoHRH/bX3VpXO80pxiTD01weyNNhlmjBnprH7ShqpvlOhW/lqQJQSSwdfkxeXHmQ6kWCGIUVdE5ipt4YoABIVe4ZhiDV9hJ344wMmp7LwaYNr27iJ4W7Bx3FqtvabzD5afguPDhP7dmtIaKdiOxTNZvMH/L6SOBCUuSXcf/tViXlJtNJLqrxK0qm5grZ66nv8N00pgTdL/LcCUcSXV5eU72j13jhZ27x7+zO9GMSg0D5M/3jDboMU51kvFLr+eerRXW1HnPgtp78sNdj0VG2vp8ZodjwBySqgMiXA//0lUByvIFXaOhTRnoaiT/Ha4MLT1izvWMw2DzM2z4zZP2rA= Content-Type: multipart/mixed; boundary="_002_DBBPR08MB477565EB3A26B42AADED3D759B710DBBPR08MB4775eurp_" MIME-Version: 1.0 Original-Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Srinath.Parvathaneni@arm.com; Return-Path: Srinath.Parvathaneni@arm.com X-MS-Exchange-Transport-CrossTenantHeadersStripped: VE1EUR03FT038.eop-EUR03.prod.protection.outlook.com X-MS-Office365-Filtering-Correlation-Id-Prvs: db76d5a6-3ed7-4c05-1770-08d76936b7a9 X-IsSubscribed: yes X-SW-Source: 2019-11/txt/msg01268.txt.bz2 --_002_DBBPR08MB477565EB3A26B42AADED3D759B710DBBPR08MB4775eurp_ Content-Type: text/plain; charset="us-ascii" Content-ID: Content-Transfer-Encoding: quoted-printable Content-length: 76944 Hello, This patch supports the following MVE ACLE load intrinsics which load a byt= e, halfword, or word from memory. vld1q_s8, vld1q_s32, vld1q_s16, vld1q_u8, vld1q_u32, vld1q_u16, vldrhq_gath= er_offset_s32, vldrhq_gather_offset_s16, vldrhq_gather_offset_u32, vldrhq_gather_offset_u1= 6, vldrhq_gather_offset_z_s32, vldrhq_gather_offset_z_s16, vldrhq_gather_offse= t_z_u32, vldrhq_gather_offset_z_u16, vldrhq_gather_shifted_offset_s32,vldrwq_f32, vl= drwq_z_f32, vldrhq_gather_shifted_offset_s16, vldrhq_gather_shifted_offset_u32, vldrhq_gather_shifted_offset_u16, vldrhq_gather_shifted_offset_z_s32, vldrhq_gather_shifted_offset_z_s16, vldrhq_gather_shifted_offset_z_u32, vldrhq_gather_shifted_offset_z_u16, vldrhq_s32, vldrhq_s16, vldrhq_u32, vld= rhq_u16, vldrhq_z_s32, vldrhq_z_s16, vldrhq_z_u32, vldrhq_z_u16, vldrwq_s32, vldrwq_= u32, vldrwq_z_s32, vldrwq_z_u32, vld1q_f32, vld1q_f16, vldrhq_f16, vldrhq_z_f16. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more d= etails. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/hel= ium/mve-intrinsics Regression tested on arm-none-eabi and found no regressions. Ok for trunk? Thanks, Srinath. gcc/ChangeLog: 2019-11-01 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm_mve.h (vld1q_s8): Define macro. (vld1q_s32): Likewise. (vld1q_s16): Likewise. (vld1q_u8): Likewise. (vld1q_u32): Likewise. (vld1q_u16): Likewise. (vldrhq_gather_offset_s32): Likewise. (vldrhq_gather_offset_s16): Likewise. (vldrhq_gather_offset_u32): Likewise. (vldrhq_gather_offset_u16): Likewise. (vldrhq_gather_offset_z_s32): Likewise. (vldrhq_gather_offset_z_s16): Likewise. (vldrhq_gather_offset_z_u32): Likewise. (vldrhq_gather_offset_z_u16): Likewise. (vldrhq_gather_shifted_offset_s32): Likewise. (vldrhq_gather_shifted_offset_s16): Likewise. (vldrhq_gather_shifted_offset_u32): Likewise. (vldrhq_gather_shifted_offset_u16): Likewise. (vldrhq_gather_shifted_offset_z_s32): Likewise. (vldrhq_gather_shifted_offset_z_s16): Likewise. (vldrhq_gather_shifted_offset_z_u32): Likewise. (vldrhq_gather_shifted_offset_z_u16): Likewise. (vldrhq_s32): Likewise. (vldrhq_s16): Likewise. (vldrhq_u32): Likewise. (vldrhq_u16): Likewise. (vldrhq_z_s32): Likewise. (vldrhq_z_s16): Likewise. (vldrhq_z_u32): Likewise. (vldrhq_z_u16): Likewise. (vldrwq_s32): Likewise. (vldrwq_u32): Likewise. (vldrwq_z_s32): Likewise. (vldrwq_z_u32): Likewise. (vld1q_f32): Likewise. (vld1q_f16): Likewise. (vldrhq_f16): Likewise. (vldrhq_z_f16): Likewise. (vldrwq_f32): Likewise. (vldrwq_z_f32): Likewise. (__arm_vld1q_s8): Define intrinsic. (__arm_vld1q_s32): Likewise. (__arm_vld1q_s16): Likewise. (__arm_vld1q_u8): Likewise. (__arm_vld1q_u32): Likewise. (__arm_vld1q_u16): Likewise. (__arm_vldrhq_gather_offset_s32): Likewise. (__arm_vldrhq_gather_offset_s16): Likewise. (__arm_vldrhq_gather_offset_u32): Likewise. (__arm_vldrhq_gather_offset_u16): Likewise. (__arm_vldrhq_gather_offset_z_s32): Likewise. (__arm_vldrhq_gather_offset_z_s16): Likewise. (__arm_vldrhq_gather_offset_z_u32): Likewise. (__arm_vldrhq_gather_offset_z_u16): Likewise. (__arm_vldrhq_gather_shifted_offset_s32): Likewise. (__arm_vldrhq_gather_shifted_offset_s16): Likewise. (__arm_vldrhq_gather_shifted_offset_u32): Likewise. (__arm_vldrhq_gather_shifted_offset_u16): Likewise. (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise. (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise. (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise. (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise. (__arm_vldrhq_s32): Likewise. (__arm_vldrhq_s16): Likewise. (__arm_vldrhq_u32): Likewise. (__arm_vldrhq_u16): Likewise. (__arm_vldrhq_z_s32): Likewise. (__arm_vldrhq_z_s16): Likewise. (__arm_vldrhq_z_u32): Likewise. (__arm_vldrhq_z_u16): Likewise. (__arm_vldrwq_s32): Likewise. (__arm_vldrwq_u32): Likewise. (__arm_vldrwq_z_s32): Likewise. (__arm_vldrwq_z_u32): Likewise. (__arm_vld1q_f32): Likewise. (__arm_vld1q_f16): Likewise. (__arm_vldrwq_f32): Likewise. (__arm_vldrwq_z_f32): Likewise. (__arm_vldrhq_z_f16): Likewise. (__arm_vldrhq_f16): Likewise. (vld1q): Define polymorphic variant. (vldrhq_gather_offset): Likewise. (vldrhq_gather_offset_z): Likewise. (vldrhq_gather_shifted_offset): Likewise. (vldrhq_gather_shifted_offset_z): Likewise. * config/arm/arm_mve_builtins.def (LDRU): Use builtin qualifier. (LDRS): Likewise. (LDRU_Z): Likewise. (LDRS_Z): Likewise. (LDRGU_Z): Likewise. (LDRGU): Likewise. (LDRGS_Z): Likewise. (LDRGS): Likewise. * config/arm/mve.md (MVE_H_ELEM): Define mode iterator. (V_sz_elem1): Likewise. (VLD1Q): Define iterator. (VLDRHGOQ): Likewise. (VLDRHGSOQ): Likewise. (VLDRHQ): Likewise. (VLDRWQ): Likewise. (mve_vldrhq_fv8hf): Define RTL pattern. (mve_vldrhq_gather_offset_): Likewise (mve_vldrhq_gather_offset_z_): Likewise (mve_vldrhq_gather_shifted_offset_): Likewise (mve_vldrhq_gather_shifted_offset_z_): Likewise (mve_vldrhq_): Likewise (mve_vldrhq_z_fv8hf): Likewise (mve_vldrhq_z_): Likewise (mve_vldrwq_fv4sf): Likewise (mve_vldrwq_v4si): Likewise (mve_vldrwq_z_fv4sf): Likewise (mve_vldrwq_z_v4si): Likewise (mve_vld1q_f): Define RTL expand pattern. (mve_vld1q_): Likewise gcc/testsuite/ChangeLog: 2019-11-01 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vld1q_f16.c: New test. * gcc.target/arm/mve/intrinsics/vld1q_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vld1q_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s16.c: Likewi= se. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_s32.c: Likewi= se. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u16.c: Likewi= se. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_u32.c: Likewi= se. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s16.c: Like= wise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_s32.c: Like= wise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u16.c: Like= wise. * gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_offset_z_u32.c: Like= wise. * gcc.target/arm/mve/intrinsics/vldrhq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c: Likewise. ############### Attachment also inlined for ease of reply ##########= ##### diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index b40a9c238b7f883a0e91dd6fcc5f41182ea6efe3..e85d36051ef748709da3b9fcdf5= 22e39deb12c08 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -1758,6 +1758,46 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vldrbq_z_u32(__base, __p) __arm_vldrbq_z_u32(__base, __p) #define vldrwq_gather_base_z_u32(__addr, __offset, __p) __arm_vldrwq_gath= er_base_z_u32(__addr, __offset, __p) #define vldrwq_gather_base_z_s32(__addr, __offset, __p) __arm_vldrwq_gath= er_base_z_s32(__addr, __offset, __p) +#define vld1q_s8(__base) __arm_vld1q_s8(__base) +#define vld1q_s32(__base) __arm_vld1q_s32(__base) +#define vld1q_s16(__base) __arm_vld1q_s16(__base) +#define vld1q_u8(__base) __arm_vld1q_u8(__base) +#define vld1q_u32(__base) __arm_vld1q_u32(__base) +#define vld1q_u16(__base) __arm_vld1q_u16(__base) +#define vldrhq_gather_offset_s32(__base, __offset) __arm_vldrhq_gather_off= set_s32(__base, __offset) +#define vldrhq_gather_offset_s16(__base, __offset) __arm_vldrhq_gather_off= set_s16(__base, __offset) +#define vldrhq_gather_offset_u32(__base, __offset) __arm_vldrhq_gather_off= set_u32(__base, __offset) +#define vldrhq_gather_offset_u16(__base, __offset) __arm_vldrhq_gather_off= set_u16(__base, __offset) +#define vldrhq_gather_offset_z_s32(__base, __offset, __p) __arm_vldrhq_gat= her_offset_z_s32(__base, __offset, __p) +#define vldrhq_gather_offset_z_s16(__base, __offset, __p) __arm_vldrhq_gat= her_offset_z_s16(__base, __offset, __p) +#define vldrhq_gather_offset_z_u32(__base, __offset, __p) __arm_vldrhq_gat= her_offset_z_u32(__base, __offset, __p) +#define vldrhq_gather_offset_z_u16(__base, __offset, __p) __arm_vldrhq_gat= her_offset_z_u16(__base, __offset, __p) +#define vldrhq_gather_shifted_offset_s32(__base, __offset) __arm_vldrhq_ga= ther_shifted_offset_s32(__base, __offset) +#define vldrhq_gather_shifted_offset_s16(__base, __offset) __arm_vldrhq_ga= ther_shifted_offset_s16(__base, __offset) +#define vldrhq_gather_shifted_offset_u32(__base, __offset) __arm_vldrhq_ga= ther_shifted_offset_u32(__base, __offset) +#define vldrhq_gather_shifted_offset_u16(__base, __offset) __arm_vldrhq_ga= ther_shifted_offset_u16(__base, __offset) +#define vldrhq_gather_shifted_offset_z_s32(__base, __offset, __p) __arm_vl= drhq_gather_shifted_offset_z_s32(__base, __offset, __p) +#define vldrhq_gather_shifted_offset_z_s16(__base, __offset, __p) __arm_vl= drhq_gather_shifted_offset_z_s16(__base, __offset, __p) +#define vldrhq_gather_shifted_offset_z_u32(__base, __offset, __p) __arm_vl= drhq_gather_shifted_offset_z_u32(__base, __offset, __p) +#define vldrhq_gather_shifted_offset_z_u16(__base, __offset, __p) __arm_vl= drhq_gather_shifted_offset_z_u16(__base, __offset, __p) +#define vldrhq_s32(__base) __arm_vldrhq_s32(__base) +#define vldrhq_s16(__base) __arm_vldrhq_s16(__base) +#define vldrhq_u32(__base) __arm_vldrhq_u32(__base) +#define vldrhq_u16(__base) __arm_vldrhq_u16(__base) +#define vldrhq_z_s32(__base, __p) __arm_vldrhq_z_s32(__base, __p) +#define vldrhq_z_s16(__base, __p) __arm_vldrhq_z_s16(__base, __p) +#define vldrhq_z_u32(__base, __p) __arm_vldrhq_z_u32(__base, __p) +#define vldrhq_z_u16(__base, __p) __arm_vldrhq_z_u16(__base, __p) +#define vldrwq_s32(__base) __arm_vldrwq_s32(__base) +#define vldrwq_u32(__base) __arm_vldrwq_u32(__base) +#define vldrwq_z_s32(__base, __p) __arm_vldrwq_z_s32(__base, __p) +#define vldrwq_z_u32(__base, __p) __arm_vldrwq_z_u32(__base, __p) +#define vld1q_f32(__base) __arm_vld1q_f32(__base) +#define vld1q_f16(__base) __arm_vld1q_f16(__base) +#define vldrhq_f16(__base) __arm_vldrhq_f16(__base) +#define vldrhq_z_f16(__base, __p) __arm_vldrhq_z_f16(__base, __p) +#define vldrwq_f32(__base) __arm_vldrwq_f32(__base) +#define vldrwq_z_f32(__base, __p) __arm_vldrwq_z_f32(__base, __p) #endif =20 __extension__ extern __inline void @@ -11443,6 +11483,245 @@ __arm_vldrwq_gather_base_z_u32 (uint32x4_t __addr= , const int __offset, mve_pred1 return __builtin_mve_vldrwq_gather_base_z_uv4si (__addr, __offset, __p); } =20 +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld1q_s8 (int8_t const * __base) +{ + return __builtin_mve_vld1q_sv16qi ((__builtin_neon_qi *) __base); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld1q_s32 (int32_t const * __base) +{ + return __builtin_mve_vld1q_sv4si ((__builtin_neon_si *) __base); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld1q_s16 (int16_t const * __base) +{ + return __builtin_mve_vld1q_sv8hi ((__builtin_neon_hi *) __base); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld1q_u8 (uint8_t const * __base) +{ + return __builtin_mve_vld1q_uv16qi ((__builtin_neon_qi *) __base); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld1q_u32 (uint32_t const * __base) +{ + return __builtin_mve_vld1q_uv4si ((__builtin_neon_si *) __base); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld1q_u16 (uint16_t const * __base) +{ + return __builtin_mve_vld1q_uv8hi ((__builtin_neon_hi *) __base); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_offset_s32 (int16_t const * __base, uint32x4_t __offse= t) +{ + return __builtin_mve_vldrhq_gather_offset_sv4si ((__builtin_neon_hi *) _= _base, __offset); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_offset_s16 (int16_t const * __base, uint16x8_t __offse= t) +{ + return __builtin_mve_vldrhq_gather_offset_sv8hi ((__builtin_neon_hi *) _= _base, __offset); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_offset_u32 (uint16_t const * __base, uint32x4_t __offs= et) +{ + return __builtin_mve_vldrhq_gather_offset_uv4si ((__builtin_neon_hi *) _= _base, __offset); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_offset_u16 (uint16_t const * __base, uint16x8_t __offs= et) +{ + return __builtin_mve_vldrhq_gather_offset_uv8hi ((__builtin_neon_hi *) _= _base, __offset); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_offset_z_s32 (int16_t const * __base, uint32x4_t __off= set, mve_pred16_t __p) +{ + return __builtin_mve_vldrhq_gather_offset_z_sv4si ((__builtin_neon_hi *)= __base, __offset, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_offset_z_s16 (int16_t const * __base, uint16x8_t __off= set, mve_pred16_t __p) +{ + return __builtin_mve_vldrhq_gather_offset_z_sv8hi ((__builtin_neon_hi *)= __base, __offset, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_offset_z_u32 (uint16_t const * __base, uint32x4_t __of= fset, mve_pred16_t __p) +{ + return __builtin_mve_vldrhq_gather_offset_z_uv4si ((__builtin_neon_hi *)= __base, __offset, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_offset_z_u16 (uint16_t const * __base, uint16x8_t __of= fset, mve_pred16_t __p) +{ + return __builtin_mve_vldrhq_gather_offset_z_uv8hi ((__builtin_neon_hi *)= __base, __offset, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_shifted_offset_s32 (int16_t const * __base, uint32x4_t= __offset) +{ + return __builtin_mve_vldrhq_gather_shifted_offset_sv4si ((__builtin_neon= _hi *) __base, __offset); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_shifted_offset_s16 (int16_t const * __base, uint16x8_t= __offset) +{ + return __builtin_mve_vldrhq_gather_shifted_offset_sv8hi ((__builtin_neon= _hi *) __base, __offset); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_shifted_offset_u32 (uint16_t const * __base, uint32x4_= t __offset) +{ + return __builtin_mve_vldrhq_gather_shifted_offset_uv4si ((__builtin_neon= _hi *) __base, __offset); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_shifted_offset_u16 (uint16_t const * __base, uint16x8_= t __offset) +{ + return __builtin_mve_vldrhq_gather_shifted_offset_uv8hi ((__builtin_neon= _hi *) __base, __offset); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_shifted_offset_z_s32 (int16_t const * __base, uint32x4= _t __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrhq_gather_shifted_offset_z_sv4si ((__builtin_ne= on_hi *) __base, __offset, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_shifted_offset_z_s16 (int16_t const * __base, uint16x8= _t __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrhq_gather_shifted_offset_z_sv8hi ((__builtin_ne= on_hi *) __base, __offset, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_shifted_offset_z_u32 (uint16_t const * __base, uint32x= 4_t __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrhq_gather_shifted_offset_z_uv4si ((__builtin_ne= on_hi *) __base, __offset, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_gather_shifted_offset_z_u16 (uint16_t const * __base, uint16x= 8_t __offset, mve_pred16_t __p) +{ + return __builtin_mve_vldrhq_gather_shifted_offset_z_uv8hi ((__builtin_ne= on_hi *) __base, __offset, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_s32 (int16_t const * __base) +{ + return __builtin_mve_vldrhq_sv4si ((__builtin_neon_hi *) __base); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_s16 (int16_t const * __base) +{ + return __builtin_mve_vldrhq_sv8hi ((__builtin_neon_hi *) __base); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_u32 (uint16_t const * __base) +{ + return __builtin_mve_vldrhq_uv4si ((__builtin_neon_hi *) __base); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_u16 (uint16_t const * __base) +{ + return __builtin_mve_vldrhq_uv8hi ((__builtin_neon_hi *) __base); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_z_s32 (int16_t const * __base, mve_pred16_t __p) +{ + return __builtin_mve_vldrhq_z_sv4si ((__builtin_neon_hi *) __base, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_z_s16 (int16_t const * __base, mve_pred16_t __p) +{ + return __builtin_mve_vldrhq_z_sv8hi ((__builtin_neon_hi *) __base, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_z_u32 (uint16_t const * __base, mve_pred16_t __p) +{ + return __builtin_mve_vldrhq_z_uv4si ((__builtin_neon_hi *) __base, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_z_u16 (uint16_t const * __base, mve_pred16_t __p) +{ + return __builtin_mve_vldrhq_z_uv8hi ((__builtin_neon_hi *) __base, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_s32 (int32_t const * __base) +{ + return __builtin_mve_vldrwq_sv4si ((__builtin_neon_si *) __base); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_u32 (uint32_t const * __base) +{ + return __builtin_mve_vldrwq_uv4si ((__builtin_neon_si *) __base); +} + + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_z_s32 (int32_t const * __base, mve_pred16_t __p) +{ + return __builtin_mve_vldrwq_z_sv4si ((__builtin_neon_si *) __base, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_z_u32 (uint32_t const * __base, mve_pred16_t __p) +{ + return __builtin_mve_vldrwq_z_uv4si ((__builtin_neon_si *) __base, __p); +} + #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ =20 __extension__ extern __inline void @@ -13585,6 +13864,47 @@ __arm_vsubq_m_n_f16 (float16x8_t __inactive, float= 16x8_t __a, float16_t __b, mve return __builtin_mve_vsubq_m_n_fv8hf (__inactive, __a, __b, __p); } =20 +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld1q_f32 (float32_t const * __base) +{ + return __builtin_mve_vld1q_fv4sf((__builtin_neon_si *) __base); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vld1q_f16 (float16_t const * __base) +{ + return __builtin_mve_vld1q_fv8hf((__builtin_neon_hi *) __base); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_f32 (float32_t const * __base) +{ + return __builtin_mve_vldrwq_fv4sf((__builtin_neon_si *) __base); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_z_f32 (float32_t const * __base, mve_pred16_t __p) +{ + return __builtin_mve_vldrwq_z_fv4sf((__builtin_neon_si *) __base, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_z_f16 (float16_t const * __base, mve_pred16_t __p) +{ + return __builtin_mve_vldrhq_z_fv8hf((__builtin_neon_hi *) __base, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrhq_f16 (float16_t const * __base) +{ + return __builtin_mve_vldrhq_fv8hf((__builtin_neon_hi *) __base); +} #endif =20 enum { @@ -15132,6 +15452,18 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mv= e_type_float16x8_t]: __arm_vorrq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t)= , __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t),= p3), \ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mv= e_type_float32x4_t]: __arm_vorrq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t)= , __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t),= p3));}) =20 +#define vld1q(p0) __arm_vld1q(p0) +#define __arm_vld1q(p0) ({ __typeof(p0) __p0 =3D (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8_t_const_ptr]: __arm_vld1q_s8 (__ARM_mve_coer= ce(__p0, int8_t const *)), \ + int (*)[__ARM_mve_type_int16_t_const_ptr]: __arm_vld1q_s16 (__ARM_mve_co= erce(__p0, int16_t const *)), \ + int (*)[__ARM_mve_type_int32_t_const_ptr]: __arm_vld1q_s32 (__ARM_mve_co= erce(__p0, int32_t const *)), \ + int (*)[__ARM_mve_type_uint8_t_const_ptr]: __arm_vld1q_u8 (__ARM_mve_coe= rce(__p0, uint8_t const *)), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr]: __arm_vld1q_u16 (__ARM_mve_c= oerce(__p0, uint16_t const *)), \ + int (*)[__ARM_mve_type_uint32_t_const_ptr]: __arm_vld1q_u32 (__ARM_mve_c= oerce(__p0, uint32_t const *)), \ + int (*)[__ARM_mve_type_float16_t_const_ptr]: __arm_vld1q_f16 (__ARM_mve_= coerce(__p0, float16_t const *)), \ + int (*)[__ARM_mve_type_float32_t_const_ptr]: __arm_vld1q_f32 (__ARM_mve_= coerce(__p0, float32_t const *)));}) + #else /* MVE Interger. */ =20 #define vst4q(p0,p1) __arm_vst4q(p0,p1) @@ -18071,6 +18403,52 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint8_t_const_ptr][__ARM_mve_type_uint16x8_t]: __= arm_vldrbq_gather_offset_z_u16 (__ARM_mve_coerce(__p0, uint8_t const *), __= ARM_mve_coerce(__p1, uint16x8_t), p2), \ int (*)[__ARM_mve_type_uint8_t_const_ptr][__ARM_mve_type_uint32x4_t]: __= arm_vldrbq_gather_offset_z_u32 (__ARM_mve_coerce(__p0, uint8_t const *), __= ARM_mve_coerce(__p1, uint32x4_t), p2));}) =20 +#define vld1q(p0) __arm_vld1q(p0) +#define __arm_vld1q(p0) ({ __typeof(p0) __p0 =3D (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8_t_const_ptr]: __arm_vld1q_s8 (__ARM_mve_coer= ce(__p0, int8_t const *)), \ + int (*)[__ARM_mve_type_int16_t_const_ptr]: __arm_vld1q_s16 (__ARM_mve_co= erce(__p0, int16_t const *)), \ + int (*)[__ARM_mve_type_int32_t_const_ptr]: __arm_vld1q_s32 (__ARM_mve_co= erce(__p0, int32_t const *)), \ + int (*)[__ARM_mve_type_uint8_t_const_ptr]: __arm_vld1q_u8 (__ARM_mve_coe= rce(__p0, uint8_t const *)), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr]: __arm_vld1q_u16 (__ARM_mve_c= oerce(__p0, uint16_t const *)), \ + int (*)[__ARM_mve_type_uint32_t_const_ptr]: __arm_vld1q_u32 (__ARM_mve_c= oerce(__p0, uint32_t const *)));}) + +#define vldrhq_gather_offset(p0,p1) __arm_vldrhq_gather_offset(p0,p1) +#define __arm_vldrhq_gather_offset(p0,p1) ({ __typeof(p0) __p0 =3D (p0); \ + __typeof(p1) __p1 =3D (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __= arm_vldrhq_gather_offset_s16 (__ARM_mve_coerce(__p0, int16_t const *), __AR= M_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint32x4_t]: __= arm_vldrhq_gather_offset_s32 (__ARM_mve_coerce(__p0, int16_t const *), __AR= M_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint16x8_t]: _= _arm_vldrhq_gather_offset_u16 (__ARM_mve_coerce(__p0, uint16_t const *), __= ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint32x4_t]: _= _arm_vldrhq_gather_offset_u32 (__ARM_mve_coerce(__p0, uint16_t const *), __= ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vldrhq_gather_offset_z(p0,p1,p2) __arm_vldrhq_gather_offset_z(p0,p= 1,p2) +#define __arm_vldrhq_gather_offset_z(p0,p1,p2) ({ __typeof(p0) __p0 =3D (p= 0); \ + __typeof(p1) __p1 =3D (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __= arm_vldrhq_gather_offset_z_s16 (__ARM_mve_coerce(__p0, int16_t const *), __= ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint32x4_t]: __= arm_vldrhq_gather_offset_z_s32 (__ARM_mve_coerce(__p0, int16_t const *), __= ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint16x8_t]: _= _arm_vldrhq_gather_offset_z_u16 (__ARM_mve_coerce(__p0, uint16_t const *), = __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint32x4_t]: _= _arm_vldrhq_gather_offset_z_u32 (__ARM_mve_coerce(__p0, uint16_t const *), = __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + +#define vldrhq_gather_shifted_offset(p0,p1) __arm_vldrhq_gather_shifted_of= fset(p0,p1) +#define __arm_vldrhq_gather_shifted_offset(p0,p1) ({ __typeof(p0) __p0 =3D= (p0); \ + __typeof(p1) __p1 =3D (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __= arm_vldrhq_gather_shifted_offset_s16 (__ARM_mve_coerce(__p0, int16_t const = *), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint32x4_t]: __= arm_vldrhq_gather_shifted_offset_s32 (__ARM_mve_coerce(__p0, int16_t const = *), __ARM_mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint16x8_t]: _= _arm_vldrhq_gather_shifted_offset_u16 (__ARM_mve_coerce(__p0, uint16_t cons= t *), __ARM_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint32x4_t]: _= _arm_vldrhq_gather_shifted_offset_u32 (__ARM_mve_coerce(__p0, uint16_t cons= t *), __ARM_mve_coerce(__p1, uint32x4_t)));}) + +#define vldrhq_gather_shifted_offset_z(p0,p1,p2) __arm_vldrhq_gather_shift= ed_offset_z(p0,p1,p2) +#define __arm_vldrhq_gather_shifted_offset_z(p0,p1,p2) ({ __typeof(p0) __p= 0 =3D (p0); \ + __typeof(p1) __p1 =3D (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint16x8_t]: __= arm_vldrhq_gather_shifted_offset_z_s16 (__ARM_mve_coerce(__p0, int16_t cons= t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_int16_t_const_ptr][__ARM_mve_type_uint32x4_t]: __= arm_vldrhq_gather_shifted_offset_z_s32 (__ARM_mve_coerce(__p0, int16_t cons= t *), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint16x8_t]: _= _arm_vldrhq_gather_shifted_offset_z_u16 (__ARM_mve_coerce(__p0, uint16_t co= nst *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint16_t_const_ptr][__ARM_mve_type_uint32x4_t]: _= _arm_vldrhq_gather_shifted_offset_z_u32 (__ARM_mve_coerce(__p0, uint16_t co= nst *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) + #endif /* MVE Floating point. */ =20 #ifdef __cplusplus diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_b= uiltins.def index 45b00e889cfe716a2c70fb86d72eb9a4c411b70d..be407f4d690cadadbdbdab30aed= 5b0339178dda9 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -709,3 +709,26 @@ VAR3 (LDRGS_Z, vldrbq_gather_offset_z_s, v16qi, v8hi, = v4si) VAR3 (LDRGU_Z, vldrbq_gather_offset_z_u, v16qi, v8hi, v4si) VAR3 (LDRS_Z, vldrbq_z_s, v16qi, v8hi, v4si) VAR3 (LDRU_Z, vldrbq_z_u, v16qi, v8hi, v4si) +VAR3 (LDRU, vld1q_u, v16qi, v8hi, v4si) +VAR3 (LDRS, vld1q_s, v16qi, v8hi, v4si) +VAR2 (LDRU_Z, vldrhq_z_u, v8hi, v4si) +VAR2 (LDRU, vldrhq_u, v8hi, v4si) +VAR2 (LDRS_Z, vldrhq_z_s, v8hi, v4si) +VAR2 (LDRS, vldrhq_s, v8hi, v4si) +VAR2 (LDRS, vld1q_f, v8hf, v4sf) +VAR2 (LDRGU_Z, vldrhq_gather_shifted_offset_z_u, v8hi, v4si) +VAR2 (LDRGU_Z, vldrhq_gather_offset_z_u, v8hi, v4si) +VAR2 (LDRGU, vldrhq_gather_shifted_offset_u, v8hi, v4si) +VAR2 (LDRGU, vldrhq_gather_offset_u, v8hi, v4si) +VAR2 (LDRGS_Z, vldrhq_gather_shifted_offset_z_s, v8hi, v4si) +VAR2 (LDRGS_Z, vldrhq_gather_offset_z_s, v8hi, v4si) +VAR2 (LDRGS, vldrhq_gather_shifted_offset_s, v8hi, v4si) +VAR2 (LDRGS, vldrhq_gather_offset_s, v8hi, v4si) +VAR1 (LDRS, vldrhq_f, v8hf) +VAR1 (LDRS_Z, vldrhq_z_f, v8hf) +VAR1 (LDRS, vldrwq_f, v4sf) +VAR1 (LDRS, vldrwq_s, v4si) +VAR1 (LDRU, vldrwq_u, v4si) +VAR1 (LDRS_Z, vldrwq_z_f, v4sf) +VAR1 (LDRS_Z, vldrwq_z_s, v4si) +VAR1 (LDRU_Z, vldrwq_z_u, v4si) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 05b94e4ee283da427aee18c7223bf5ff4b0e1e4a..31ccb7b1608713e89ae9866b0b1= 24efe8dc88ae3 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -26,6 +26,7 @@ (define_mode_iterator MVE_3 [V16QI V8HI]) (define_mode_iterator MVE_2 [V16QI V8HI V4SI]) (define_mode_iterator MVE_5 [V8HI V4SI]) +(define_mode_iterator MVE_6 [V8HI V4SI]) =20 (define_c_enum "unspec" [VST4Q VRNDXQ_F VRNDQ_F VRNDPQ_F VRNDNQ_F VRNDMQ_F VRNDAQ_F VREV64Q_F VNEGQ_F VDUPQ_N_F VABSQ_F VREV32Q_F @@ -193,10 +194,13 @@ VFMAQ_M_N_F VFMASQ_M_N_F VFMSQ_M_F VMAXNMQ_M_F VMINNMQ_M_F VSUBQ_M_F VSTRWQSB_S VSTRWQSB_U VSTRBQSO_S VSTRBQSO_U VSTRBQ_S VSTRBQ_U VLDRBQGO_S - VLDRBQGO_U VLDRBQ_S VLDRBQ_U VLDRWQGB_S VLDRWQGB_U]) + VLDRBQGO_U VLDRBQ_S VLDRBQ_U VLDRWQGB_S VLDRWQGB_U + VLD1Q_F VLD1Q_S VLD1Q_U VLDRHQ_F VLDRHQGO_S + VLDRHQGO_U VLDRHQGSO_S VLDRHQGSO_U VLDRHQ_S VLDRHQ_U + VLDRWQ_F VLDRWQ_S VLDRWQ_U]) =20 -(define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") - (V8HF "V8HI") (V4SF "V4SI")]) +(define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI") + (V4SF "V4SI")]) =20 (define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u") (VREV16Q_S "s= ") (VREV16Q_U "u") (VMVNQ_N_S "s") (VMVNQ_N_U "u") @@ -348,7 +352,11 @@ (VSTRWQSB_S "s") (VSTRWQSB_U "u") (VSTRBQSO_S "s") (VSTRBQSO_U "u") (VSTRBQ_S "s") (VSTRBQ_U "u") (VLDRBQGO_S "s") (VLDRBQGO_U "u") (VLDRBQ_S "s") - (VLDRBQ_U "u") (VLDRWQGB_S "s") (VLDRWQGB_U "u")]) + (VLDRBQ_U "u") (VLDRWQGB_S "s") (VLDRWQGB_U "u") + (VLD1Q_S "s") (VLD1Q_U "u") (VLDRHQGO_S "s") + (VLDRHQGO_U "u") (VLDRHQGSO_S "s") (VLDRHQGSO_U "u") + (VLDRHQ_S "s") (VLDRHQ_U "u") (VLDRWQ_S "s") + (VLDRWQ_U "u")]) =20 (define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32") (VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16") @@ -362,10 +370,12 @@ (V4SI "mve_imm_31")]) (define_mode_attr MVE_constraint3 [ (V8HI "Rb") (V4SI "Rd")]) (define_mode_attr MVE_pred3 [ (V8HI "mve_imm_8") (V4SI "mve_imm_16")]) - (define_mode_attr MVE_constraint1 [ (V8HI "Ra") (V4SI "Rc")]) (define_mode_attr MVE_pred1 [ (V8HI "mve_imm_7") (V4SI "mve_imm_15")]) (define_mode_attr MVE_B_ELEM [ (V16QI "V16QI") (V8HI "V8QI") (V4SI "V4QI")= ]) +(define_mode_attr MVE_H_ELEM [ (V8HI "V8HI") (V4SI "V4HI")]) +(define_mode_attr V_sz_elem1 [(V16QI "b") (V8HI "h") (V4SI "w") (V8HF "h") + (V4SF "w")]) =20 (define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U]) (define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S]) @@ -575,6 +585,11 @@ (define_int_iterator VLDRBGOQ [VLDRBQGO_S VLDRBQGO_U]) (define_int_iterator VLDRBQ [VLDRBQ_S VLDRBQ_U]) (define_int_iterator VLDRWGBQ [VLDRWQGB_S VLDRWQGB_U]) +(define_int_iterator VLD1Q [VLD1Q_S VLD1Q_U]) +(define_int_iterator VLDRHGOQ [VLDRHQGO_S VLDRHQGO_U]) +(define_int_iterator VLDRHGSOQ [VLDRHQGSO_S VLDRHQGSO_U]) +(define_int_iterator VLDRHQ [VLDRHQ_S VLDRHQ_U]) +(define_int_iterator VLDRWQ [VLDRWQ_S VLDRWQ_U]) =20 (define_insn "*mve_mov" [(set (match_operand:MVE_types 0 "s_register_operand" "=3Dw,w,r,w,w,r,w") @@ -8201,3 +8216,276 @@ return ""; } [(set_attr "length" "8")]) + +;; +;; [vldrhq_f] +;; +(define_insn "mve_vldrhq_fv8hf" + [(set (match_operand:V8HF 0 "s_register_operand" "=3Dw") + (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us")] + VLDRHQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ops[2]; + int regno =3D REGNO (operands[0]); + ops[0] =3D gen_rtx_REG (TImode, regno); + ops[1] =3D operands[1]; + output_asm_insn ("vldrh.f16\t%q0, %E1",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vldrhq_gather_offset_s vldrhq_gather_offset_u] +;; +(define_insn "mve_vldrhq_gather_offset_" + [(set (match_operand:MVE_6 0 "s_register_operand" "=3D&w") + (unspec:MVE_6 [(match_operand: 1 "memory_operand" "Us") + (match_operand:MVE_6 2 "s_register_operand" "w")] + VLDRHGOQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] =3D operands[0]; + ops[1] =3D operands[1]; + ops[2] =3D operands[2]; + if (!strcmp ("","s") && =3D=3D 16) + output_asm_insn ("vldrh.u16\t%q0, [%m1, %q2]",ops); + else + output_asm_insn ("vldrh.\t%q0, [%m1, %q2]",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vldrhq_gather_offset_z_s vldrhq_gather_offset_z_u] +;; +(define_insn "mve_vldrhq_gather_offset_z_" + [(set (match_operand:MVE_6 0 "s_register_operand" "=3D&w") + (unspec:MVE_6 [(match_operand: 1 "memory_operand" "Us") + (match_operand:MVE_6 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up") + ]VLDRHGOQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[4]; + ops[0] =3D operands[0]; + ops[1] =3D operands[1]; + ops[2] =3D operands[2]; + ops[3] =3D operands[3]; + if (!strcmp ("","s") && =3D=3D 16) + output_asm_insn ("vpst\n\tvldrht.u16\t%q0, [%m1, %q2]",ops); + else + output_asm_insn ("vpst\n\tvldrht.\t%q0, [%m1, %q2]",= ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vldrhq_gather_shifted_offset_s vldrhq_gather_shifted_offset_u] +;; +(define_insn "mve_vldrhq_gather_shifted_offset_" + [(set (match_operand:MVE_6 0 "s_register_operand" "=3D&w") + (unspec:MVE_6 [(match_operand: 1 "memory_operand" "Us") + (match_operand:MVE_6 2 "s_register_operand" "w")] + VLDRHGSOQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] =3D operands[0]; + ops[1] =3D operands[1]; + ops[2] =3D operands[2]; + if (!strcmp ("","s") && =3D=3D 16) + output_asm_insn ("vldrh.u16\t%q0, [%m1, %q2, uxtw #1]",ops); + else + output_asm_insn ("vldrh.\t%q0, [%m1, %q2, uxtw #1]",= ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vldrhq_gather_shifted_offset_z_s vldrhq_gather_shited_offset_z_u] +;; +(define_insn "mve_vldrhq_gather_shifted_offset_z_" + [(set (match_operand:MVE_6 0 "s_register_operand" "=3D&w") + (unspec:MVE_6 [(match_operand: 1 "memory_operand" "Us") + (match_operand:MVE_6 2 "s_register_operand" "w") + (match_operand:HI 3 "vpr_register_operand" "Up") + ]VLDRHGSOQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[4]; + ops[0] =3D operands[0]; + ops[1] =3D operands[1]; + ops[2] =3D operands[2]; + ops[3] =3D operands[3]; + if (!strcmp ("","s") && =3D=3D 16) + output_asm_insn ("vpst\n\tvldrht.u16\t%q0, [%m1, %q2, uxtw #1]",ops); + else + output_asm_insn ("vpst\n\tvldrht.\t%q0, [%m1, %q2, u= xtw #1]",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; +;; [vldrhq_s, vldrhq_u] +;; +(define_insn "mve_vldrhq_" + [(set (match_operand:MVE_6 0 "s_register_operand" "=3Dw") + (unspec:MVE_6 [(match_operand: 1 "memory_operand" "Us")] + VLDRHQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[2]; + int regno =3D REGNO (operands[0]); + ops[0] =3D gen_rtx_REG (TImode, regno); + ops[1] =3D operands[1]; + output_asm_insn ("vldrh.\t%q0, %E1",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vldrhq_z_f] +;; +(define_insn "mve_vldrhq_z_fv8hf" + [(set (match_operand:V8HF 0 "s_register_operand" "=3Dw") + (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us") + (match_operand:HI 2 "vpr_register_operand" "Up")] + VLDRHQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ops[2]; + int regno =3D REGNO (operands[0]); + ops[0] =3D gen_rtx_REG (TImode, regno); + ops[1] =3D operands[1]; + output_asm_insn ("vpst\n\tvldrht.f16\t%q0, %E1",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vldrhq_z_s vldrhq_z_u] +;; +(define_insn "mve_vldrhq_z_" + [(set (match_operand:MVE_6 0 "s_register_operand" "=3Dw") + (unspec:MVE_6 [(match_operand: 1 "memory_operand" "Us") + (match_operand:HI 2 "vpr_register_operand" "Up")] + VLDRHQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[2]; + int regno =3D REGNO (operands[0]); + ops[0] =3D gen_rtx_REG (TImode, regno); + ops[1] =3D operands[1]; + output_asm_insn ("vpst\n\tvldrht.\t%q0, %E1",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vldrwq_f] +;; +(define_insn "mve_vldrwq_fv4sf" + [(set (match_operand:V4SF 0 "s_register_operand" "=3Dw") + (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us")] + VLDRWQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ops[2]; + int regno =3D REGNO (operands[0]); + ops[0] =3D gen_rtx_REG (TImode, regno); + ops[1] =3D operands[1]; + output_asm_insn ("vldrw.f32\t%q0, %E1",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vldrwq_s vldrwq_u] +;; +(define_insn "mve_vldrwq_v4si" + [(set (match_operand:V4SI 0 "s_register_operand" "=3Dw") + (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us")] + VLDRWQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[2]; + int regno =3D REGNO (operands[0]); + ops[0] =3D gen_rtx_REG (TImode, regno); + ops[1] =3D operands[1]; + output_asm_insn ("vldrw.32\t%q0, %E1",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vldrwq_z_f] +;; +(define_insn "mve_vldrwq_z_fv4sf" + [(set (match_operand:V4SF 0 "s_register_operand" "=3Dw") + (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us") + (match_operand:HI 2 "vpr_register_operand" "Up")] + VLDRWQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" +{ + rtx ops[2]; + int regno =3D REGNO (operands[0]); + ops[0] =3D gen_rtx_REG (TImode, regno); + ops[1] =3D operands[1]; + output_asm_insn ("vpst\n\tvldrwt.f32\t%q0, %E1",ops); + return ""; +} + [(set_attr "length" "8")]) + +;; +;; [vldrwq_z_s vldrwq_z_u] +;; +(define_insn "mve_vldrwq_z_v4si" + [(set (match_operand:V4SI 0 "s_register_operand" "=3Dw") + (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us") + (match_operand:HI 2 "vpr_register_operand" "Up")] + VLDRWQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[2]; + int regno =3D REGNO (operands[0]); + ops[0] =3D gen_rtx_REG (TImode, regno); + ops[1] =3D operands[1]; + output_asm_insn ("vpst\n\tvldrwt.32\t%q0, %E1",ops); + return ""; +} + [(set_attr "length" "8")]) + +(define_expand "mve_vld1q_f" + [(match_operand:MVE_0 0 "s_register_operand") + (unspec:MVE_0 [(match_operand: 1 "memory_operand")] VLD1Q_F) + ] + "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT" +{ + emit_insn (gen_mve_vldrq_f(operands[0],operands[1])); + DONE; +}) + +(define_expand "mve_vld1q_" + [(match_operand:MVE_2 0 "s_register_operand") + (unspec:MVE_2 [(match_operand:MVE_2 1 "memory_operand")] VLD1Q) + ] + "TARGET_HAVE_MVE" +{ + emit_insn (gen_mve_vldrq_(operands[0],operands[1= ])); + DONE; +}) diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c b/gcc/= testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c new file mode 100644 index 0000000000000000000000000000000000000000..9665c7d6721016bd7cccf3d6df5= bb09746216e53 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve.fp -mfloat-abi=3Dh= ard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16_t const * base) +{ + return vld1q_f16 (base); +} + +/* { dg-final { scan-assembler "vldrh.f16" } } */ + +float16x8_t +foo1 (float16_t const * base) +{ + return vld1q (base); +} + +/* { dg-final { scan-assembler "vldrh.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c b/gcc/= testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c new file mode 100644 index 0000000000000000000000000000000000000000..8f720bd28a293858575ae9a7ed2= 5aeb7cde827f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve.fp -mfloat-abi=3Dh= ard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32_t const * base) +{ + return vld1q_f32 (base); +} + +/* { dg-final { scan-assembler "vldrw.f32" } } */ + +float32x4_t +foo1 (float32_t const * base) +{ + return vld1q (base); +} + +/* { dg-final { scan-assembler "vldrw.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c b/gcc/= testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c new file mode 100644 index 0000000000000000000000000000000000000000..9fa37f82fd604b225ba038673ef= 937bf3778f5ba --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16_t const * base) +{ + return vld1q_s16 (base); +} + +/* { dg-final { scan-assembler "vldrh.s16" } } */ + +int16x8_t +foo1 (int16_t const * base) +{ + return vld1q (base); +} + +/* { dg-final { scan-assembler "vldrh.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c b/gcc/= testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c new file mode 100644 index 0000000000000000000000000000000000000000..38af9e66c2b19133a21f87c9482= f9370d8f9b69d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32_t const * base) +{ + return vld1q_s32 (base); +} + +/* { dg-final { scan-assembler "vldrw.s32" } } */ + +int32x4_t +foo1 (int32_t const * base) +{ + return vld1q (base); +} + +/* { dg-final { scan-assembler "vldrw.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c b/gcc/t= estsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c new file mode 100644 index 0000000000000000000000000000000000000000..a8b4c1fe3addec2ced922d66bf5= d9f554fb2392c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8_t const * base) +{ + return vld1q_s8 (base); +} + +/* { dg-final { scan-assembler "vldrb.s8" } } */ + +int8x16_t +foo1 (int8_t const * base) +{ + return vld1q (base); +} + +/* { dg-final { scan-assembler "vldrb.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c b/gcc/= testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c new file mode 100644 index 0000000000000000000000000000000000000000..b69a0642e2ebaf62a4f7c164b23= 085dab7d1237d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16_t const * base) +{ + return vld1q_u16 (base); +} + +/* { dg-final { scan-assembler "vldrh.u16" } } */ + +uint16x8_t +foo1 (uint16_t const * base) +{ + return vld1q (base); +} + +/* { dg-final { scan-assembler "vldrh.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c b/gcc/= testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c new file mode 100644 index 0000000000000000000000000000000000000000..cbe87e31750d71dd1f5deaf8166= dd3ec05c81d16 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32_t const * base) +{ + return vld1q_u32 (base); +} + +/* { dg-final { scan-assembler "vldrw.u32" } } */ + +uint32x4_t +foo1 (uint32_t const * base) +{ + return vld1q (base); +} + +/* { dg-final { scan-assembler "vldrw.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c b/gcc/t= estsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c new file mode 100644 index 0000000000000000000000000000000000000000..75637eb88d20ce3eebd3030062e= d8c23c8b1931e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8_t const * base) +{ + return vld1q_u8 (base); +} + +/* { dg-final { scan-assembler "vldrb.u8" } } */ + +uint8x16_t +foo1 (uint8_t const * base) +{ + return vld1q (base); +} + +/* { dg-final { scan-assembler "vldrb.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c b/gcc= /testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c new file mode 100644 index 0000000000000000000000000000000000000000..80fcdfc3bf66f73d6f2e91e5be9= aba8ccb5a0af7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve.fp -mfloat-abi=3Dh= ard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16_t const * base) +{ + return vldrhq_f16 (base); +} + +/* { dg-final { scan-assembler "vldrh.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offs= et_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset= _s16.c new file mode 100644 index 0000000000000000000000000000000000000000..cf429f323b6c59717e2d073355a= 7b6a6189bce71 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16_t const * base, uint16x8_t offset) +{ + return vldrhq_gather_offset_s16 (base, offset); +} + +/* { dg-final { scan-assembler "vldrh.u16" } } */ + +int16x8_t +foo1 (int16_t const * base, uint16x8_t offset) +{ + return vldrhq_gather_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrh.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offs= et_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset= _s32.c new file mode 100644 index 0000000000000000000000000000000000000000..264090080cb4435d5fa0512e166= 48f111dc79ad5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int32x4_t +foo (int16_t const * base, uint32x4_t offset) +{ + return vldrhq_gather_offset_s32 (base, offset); +} + +/* { dg-final { scan-assembler "vldrh.s32" } } */ + +int32x4_t +foo1 (int16_t const * base, uint32x4_t offset) +{ + return vldrhq_gather_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrh.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offs= et_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset= _u16.c new file mode 100644 index 0000000000000000000000000000000000000000..9c46661a2a94cfb7f34658ee5f9= 0ec8de626dee4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16_t const * base, uint16x8_t offset) +{ + return vldrhq_gather_offset_u16 (base, offset); +} + +/* { dg-final { scan-assembler "vldrh.u16" } } */ + +uint16x8_t +foo1 (uint16_t const * base, uint16x8_t offset) +{ + return vldrhq_gather_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrh.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offs= et_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset= _u32.c new file mode 100644 index 0000000000000000000000000000000000000000..93efe5d1e38a7be3bb00009fc63= 1528b76c4998e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint16_t const * base, uint32x4_t offset) +{ + return vldrhq_gather_offset_u32 (base, offset); +} + +/* { dg-final { scan-assembler "vldrh.u32" } } */ + +uint32x4_t +foo1 (uint16_t const * base, uint32x4_t offset) +{ + return vldrhq_gather_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrh.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offs= et_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offs= et_z_s16.c new file mode 100644 index 0000000000000000000000000000000000000000..a1beb003049d57f036ddd8ea142= 60985d0befc89 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s1= 6.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16_t const * base, uint16x8_t offset, mve_pred16_t p) +{ + return vldrhq_gather_offset_z_s16 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrht.u16" } } */ + +int16x8_t +foo1 (int16_t const * base, uint16x8_t offset, mve_pred16_t p) +{ + return vldrhq_gather_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrht.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offs= et_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offs= et_z_s32.c new file mode 100644 index 0000000000000000000000000000000000000000..3f5173ba44a8759106623f2cc39= 2425a32aaf184 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_s3= 2.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int32x4_t +foo (int16_t const * base, uint32x4_t offset, mve_pred16_t p) +{ + return vldrhq_gather_offset_z_s32 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrht.s32" } } */ + +int32x4_t +foo1 (int16_t const * base, uint32x4_t offset, mve_pred16_t p) +{ + return vldrhq_gather_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrht.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offs= et_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offs= et_z_u16.c new file mode 100644 index 0000000000000000000000000000000000000000..4059307f77a1070fa621dc6dab9= 9f340012a9540 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u1= 6.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16_t const * base, uint16x8_t offset, mve_pred16_t p) +{ + return vldrhq_gather_offset_z_u16 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrht.u16" } } */ + +uint16x8_t +foo1 (uint16_t const * base, uint16x8_t offset, mve_pred16_t p) +{ + return vldrhq_gather_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrht.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offs= et_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offs= et_z_u32.c new file mode 100644 index 0000000000000000000000000000000000000000..4e14c5ad4cdaaf5b12fdb9c807c= 5ddc5f9206173 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_z_u3= 2.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint16_t const * base, uint32x4_t offset, mve_pred16_t p) +{ + return vldrhq_gather_offset_z_u32 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrht.u32" } } */ + +uint32x4_t +foo1 (uint16_t const * base, uint32x4_t offset, mve_pred16_t p) +{ + return vldrhq_gather_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrht.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shif= ted_offset_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gathe= r_shifted_offset_s16.c new file mode 100644 index 0000000000000000000000000000000000000000..c4c520344eaadeb250aab0833d5= d93552d4004cf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_off= set_s16.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16_t const * base, uint16x8_t offset) +{ + return vldrhq_gather_shifted_offset_s16 (base, offset); +} + +/* { dg-final { scan-assembler "vldrh.u16" } } */ + +int16x8_t +foo1 (int16_t const * base, uint16x8_t offset) +{ + return vldrhq_gather_shifted_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrh.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shif= ted_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gathe= r_shifted_offset_s32.c new file mode 100644 index 0000000000000000000000000000000000000000..b4ef042f21d3965b370991269c7= 6e18d652ad13c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_off= set_s32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int32x4_t +foo (int16_t const * base, uint32x4_t offset) +{ + return vldrhq_gather_shifted_offset_s32 (base, offset); +} + +/* { dg-final { scan-assembler "vldrh.s32" } } */ + +int32x4_t +foo1 (int16_t const * base, uint32x4_t offset) +{ + return vldrhq_gather_shifted_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrh.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shif= ted_offset_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gathe= r_shifted_offset_u16.c new file mode 100644 index 0000000000000000000000000000000000000000..972b6d1035035e432167bdb72a0= 7d141b256dd16 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_off= set_u16.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16_t const * base, uint16x8_t offset) +{ + return vldrhq_gather_shifted_offset_u16 (base, offset); +} + +/* { dg-final { scan-assembler "vldrh.u16" } } */ + +uint16x8_t +foo1 (uint16_t const * base, uint16x8_t offset) +{ + return vldrhq_gather_shifted_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrh.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shif= ted_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gathe= r_shifted_offset_u32.c new file mode 100644 index 0000000000000000000000000000000000000000..6617efff82855734af0ffa69ef7= 0cfd0a5883a9d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_off= set_u32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint16_t const * base, uint32x4_t offset) +{ + return vldrhq_gather_shifted_offset_u32 (base, offset); +} + +/* { dg-final { scan-assembler "vldrh.u32" } } */ + +uint32x4_t +foo1 (uint16_t const * base, uint32x4_t offset) +{ + return vldrhq_gather_shifted_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrh.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shif= ted_offset_z_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gat= her_shifted_offset_z_s16.c new file mode 100644 index 0000000000000000000000000000000000000000..e067faa24e2d0b913943c553112= 30633ad4f0a9e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_off= set_z_s16.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16_t const * base, uint16x8_t offset, mve_pred16_t p) +{ + return vldrhq_gather_shifted_offset_z_s16 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrht.u16" } } */ + +int16x8_t +foo1 (int16_t const * base, uint16x8_t offset, mve_pred16_t p) +{ + return vldrhq_gather_shifted_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrht.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shif= ted_offset_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gat= her_shifted_offset_z_s32.c new file mode 100644 index 0000000000000000000000000000000000000000..01d9ad1996db17f2b64a7cb8a78= 85ec2aaad1f36 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_off= set_z_s32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int32x4_t +foo (int16_t const * base, uint32x4_t offset, mve_pred16_t p) +{ + return vldrhq_gather_shifted_offset_z_s32 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrht.s32" } } */ + +int32x4_t +foo1 (int16_t const * base, uint32x4_t offset, mve_pred16_t p) +{ + return vldrhq_gather_shifted_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrht.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shif= ted_offset_z_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gat= her_shifted_offset_z_u16.c new file mode 100644 index 0000000000000000000000000000000000000000..133ff330a92bc6874519acb573e= 8fbc32a6c409f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_off= set_z_u16.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16_t const * base, uint16x8_t offset, mve_pred16_t p) +{ + return vldrhq_gather_shifted_offset_z_u16 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrht.u16" } } */ + +uint16x8_t +foo1 (uint16_t const * base, uint16x8_t offset, mve_pred16_t p) +{ + return vldrhq_gather_shifted_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrht.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shif= ted_offset_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gat= her_shifted_offset_z_u32.c new file mode 100644 index 0000000000000000000000000000000000000000..f370ddd51dfef82eda57c881123= 0250d429bbd7f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shifted_off= set_z_u32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint16_t const * base, uint32x4_t offset, mve_pred16_t p) +{ + return vldrhq_gather_shifted_offset_z_u32 (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrht.u32" } } */ + +uint32x4_t +foo1 (uint16_t const * base, uint32x4_t offset, mve_pred16_t p) +{ + return vldrhq_gather_shifted_offset_z (base, offset, p); +} + +/* { dg-final { scan-assembler "vldrht.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c b/gcc= /testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c new file mode 100644 index 0000000000000000000000000000000000000000..07c563a2cd0e8d3bdbf34c0e2ad= 9939fd3bfa1c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16_t const * base) +{ + return vldrhq_s16 (base); +} + +/* { dg-final { scan-assembler "vldrh.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c b/gcc= /testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c new file mode 100644 index 0000000000000000000000000000000000000000..6f56a2cc88eb3a9439ac602e0ce= dea676ac93419 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int32x4_t +foo (int16_t const * base) +{ + return vldrhq_s32 (base); +} + +/* { dg-final { scan-assembler "vldrh.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c b/gcc= /testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c new file mode 100644 index 0000000000000000000000000000000000000000..e18d7585b7ff66a1e038586069e= e09a27579da22 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16_t const * base) +{ + return vldrhq_u16 (base); +} + +/* { dg-final { scan-assembler "vldrh.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c b/gcc= /testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c new file mode 100644 index 0000000000000000000000000000000000000000..4a89ed61f7aa2a580012093456d= cff6d9eedb15f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint16_t const * base) +{ + return vldrhq_u32 (base); +} + +/* { dg-final { scan-assembler "vldrh.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c b/g= cc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c new file mode 100644 index 0000000000000000000000000000000000000000..00b68f3f4b607e522321c4158ca= 8f3eef672920c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve.fp -mfloat-abi=3Dh= ard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16_t const * base, mve_pred16_t p) +{ + return vldrhq_z_f16 (base, p); +} + +/* { dg-final { scan-assembler "vldrht.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c b/g= cc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c new file mode 100644 index 0000000000000000000000000000000000000000..a62b15c18051a42758a1b153028= bf0a9b49761f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16_t const * base, mve_pred16_t p) +{ + return vldrhq_z_s16 (base, p); +} + +/* { dg-final { scan-assembler "vldrht.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c b/g= cc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c new file mode 100644 index 0000000000000000000000000000000000000000..e43b696c91b7a10c1f822f4f7e8= fdd460830fe31 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int32x4_t +foo (int16_t const * base, mve_pred16_t p) +{ + return vldrhq_z_s32 (base, p); +} + +/* { dg-final { scan-assembler "vldrht.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c b/g= cc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c new file mode 100644 index 0000000000000000000000000000000000000000..9911442882cc9cc707f9a7034cb= 62516a06bc235 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16_t const * base, mve_pred16_t p) +{ + return vldrhq_z_u16 (base, p); +} + +/* { dg-final { scan-assembler "vldrht.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c b/g= cc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c new file mode 100644 index 0000000000000000000000000000000000000000..b28d52c9fd53029b13cbbaa10a5= 1c5f6b1c38e20 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint16_t const * base, mve_pred16_t p) +{ + return vldrhq_z_u32 (base, p); +} + +/* { dg-final { scan-assembler "vldrht.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c b/gcc= /testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c new file mode 100644 index 0000000000000000000000000000000000000000..c86b1ea7b8f19c231505a84030a= 3f9babaa6829d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve.fp -mfloat-abi=3Dh= ard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32_t const * base) +{ + return vldrwq_f32 (base); +} + +/* { dg-final { scan-assembler "vldrw.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c b/gcc= /testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c new file mode 100644 index 0000000000000000000000000000000000000000..d0cab13dcea72037c5e11be76fe= 67b6906221571 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32_t const * base) +{ + return vldrwq_s32 (base); +} + +/* { dg-final { scan-assembler "vldrw.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c b/gcc= /testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c new file mode 100644 index 0000000000000000000000000000000000000000..de9b3d9df3bbc9e6b655626636d= a9a97102b141a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32_t const * base) +{ + return vldrwq_u32 (base); +} + +/* { dg-final { scan-assembler "vldrw.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c b/g= cc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c new file mode 100644 index 0000000000000000000000000000000000000000..1f62417ecaf597dca883e8b8b33= 60eafacc48209 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve.fp -mfloat-abi=3Dh= ard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32_t const * base, mve_pred16_t p) +{ + return vldrwq_z_f32 (base, p); +} + +/* { dg-final { scan-assembler "vldrwt.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c b/g= cc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c new file mode 100644 index 0000000000000000000000000000000000000000..1922df6268a46dab4bdb5ac89c6= f28610592e2a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32_t const * base, mve_pred16_t p) +{ + return vldrwq_z_s32 (base, p); +} + +/* { dg-final { scan-assembler "vldrwt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c b/g= cc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c new file mode 100644 index 0000000000000000000000000000000000000000..ac49091ce2e3330b4d5b92f8f37= 3752d9f9b8ba6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32_t const * base, mve_pred16_t p) +{ + return vldrwq_z_u32 (base, p); +} + +/* { dg-final { scan-assembler "vldrwt.u32" } } */ --_002_DBBPR08MB477565EB3A26B42AADED3D759B710DBBPR08MB4775eurp_ Content-Type: application/gzip; name="diff24.patch.gz" Content-Description: diff24.patch.gz Content-Disposition: attachment; filename="diff24.patch.gz"; size=6707; creation-date="Thu, 14 Nov 2019 19:13:22 GMT"; modification-date="Thu, 14 Nov 2019 19:13:22 GMT" Content-ID: <9DD2E8F6F49AC5478A76B4CDA2248841@eurprd08.prod.outlook.com> Content-Transfer-Encoding: base64 Content-length: 9094 H4sIAP6ezV0C/+1d6XLbOLb+3X4KXnXNlB3LDhYSBCedrkmms1VN0uM4y9RN u1Qgllh1bVkxhTijTL/7BUiJoiRSpCjIsRNnsSkSBzg4+M4GgJDoK+UdHHzs jzx2/yPn9/nFQPU/3meX5/Z/7/yzPDz14spHO/2BkF+82Acs4gjTOFSUYgZk BIUgivNA+RBSJBmRSuLDQ0kDgQkIoFShT0MQCYbjSHGhAoQkjoSMIeKAehAA 4vs7BwcHKzjb2d/fX8Xd3//uHcAwoF3i7ae/feKZe6P/DKWQyktGl5qPvK+e 7g9G9AskvZH3mZ198E8eeH/mN7/4vdGDHe9nQ9EfSO/zmbiMP/XGPY3Rbq8X s0R2vV5vuGd+2JYrn89XcfWp95GNTuVlWiIvzoS47Hqm/IVSiRwt1bwOWU2D SbsGV5Dt7BcahJ96CZ0IoFDh3O0lglxkCxSz+0skkJSTzO4vkuhytnQlW7qC LV3Nlq5gS1ewdXmayzmTaKHP3VzMxYFpRlDXSM5O00bKCGoa0ev2RLfoiV63 J7pFT8alQl7SmbXo6pssYbRRk5V0tU3qlr3U7XupW/ZSr93L5LSvRlKsr2dN CJs22hitTQgbNqrb9lRv0FPdtqd6g56uradr0DdnYT1Er0HfmAW9oRT05lLQ G0phDf0ujR4WHiwTlTnqhQdLRLqqJb2iJV3V0qqYYBGJi2Jbfl5WxZwMS6pY eF5Sha7hQtdzoWu40Cu5uKoa36sV43tVNVRXK4bqqkbqV/VSv6oR2VWtyEyo qCqiTlUddaqKqFOtQJiqgqVaCUtVM5qqbjRV1cColQOjaqSqlrMuORB9tePt mM/yy0gOkv7FoNfz7PXlwNzsD87SJi76IssYoe/jNGWEPsVd5Ac2aVydg3m7 Nl3EyCaL3jQ9MjlpMvLM/YLlMolpb3gpBdzxPO9SjnTKQqz7Z6P+wKatFU18 9pO+lyde85bQZKd/mv7tr+5fnuPagmw0uuzHeiRNwV1b7dkV+08yKdrr2Xo/ DvTcZ3Y56qs+77OzXm9vL62kkNJ5u7Z+0/ms0/e8fAi/7uxX99TSfobkUz/l YvpwIE0PzL17e9NqHuzs/7mz36CL2RBso4t2kNMG2nUyHb/FPiat+gjJF7qd PkKS9jGdCWnRR3pa0sfT9fuot4lVTTNlbQVW7Q6septoLZikdt10BVe9Tbxq i1fdGrDaGWC3NpSl0zxVOtr15pxQnjOtlENJC+WDXxRLISX7xlardIpqtYAy RjYSUC1u1haQvkYI5cZhexjSW8CQvkYQrbIsjlCkt4CiawTReG1LVAh+SXp7 uL7QxutZp2l8fMNM1HhtI+VKdmtAbh3Z6WsF3tr2y4309LaQp68VemubNlfS 2xL2rgN6y1P/24rBFlu6pbHY8rLFtmKyJYHd0thsec1lazHaYlO3NVZbXjHa Wsy2JLLbGbuVrXNdXwy33PptjuXKFuyuL6YrkeVtju3Klh6vMcZbbv5Wx3pl q6jXGPOVSPM2xn4rbGMTYTQwbjfBmm0w55/10uWk//YGc5U9adJP7Ww0t2sB NpkSz/p5K+bEayKXNsarcThyI4KQmnCjrQAa2embETnUxQjtRKDdYkBvGQSr HXtbEThFwfZAcLXRqnxK7nSdc3vd3GQ5N6Vfo5/fdDzHq0a0BaCvVtj15OaZ tatP89uJnIlArykC7+e+stuNHr1+2Xv65NGbt6+f9F6+e+L91UN73v17nr1+ enbBTE0fveGFYfbQ8+7dX2eXFQ5okO6ywpT4XT8sbLJKdPypd94b2F1k3q6y 7eT5SX/A+Kj/2bA7f5/lN9KPcSqp6k1WsyaMtUu7Oqs4rSytovnuqrTtrW3n UBYSkyba7HRQZviVCzNXkPk2ulkY7nbdNGPpInbd4mhOtji2H860AqfjuU1j trKrba1ZfffXsedbxHS+F7Ya1m2jtHqs3yAZbKTYaQUNNbuw21cO9Ln3NfM1 AcQo9TWBH6AupNbXTERgHZJ3L/N0eiCkemCdht20u3tv70N23zJiXxrtFcR0 0vbZ36Ze7uLy0rqgVDaz8vxCXnJpbgzBnIvbs0JeLgSbFEKLhYbY/PijrqOZ XThp+2ypo9YUrOpoRlfT0ZWF0GIh09G9B3/uWf89t1V+dwjmtsjbz7MiCw+8 3a/mlu3fhZoQDoH30LPXD4wYDXZ7z+RAXvb5bhq7lki0L9Ke7p3sgW5GUiH5 bGdqL1WR3nB0ORNjvtO6Qobze1r39mrbsbpY3dAKWC7kmw2assa/uqkVwFgI g+ua0jXi09Xi0+vJT9cJUK8QoF5TgrpOhHqFCPWaMsztdGVrDUzWms2t7FwD w1FsLlV4m8LIs0ROk5UXA2PtP8rLPE3JzUEy8q2Wd4cwtwiFW5n/oCCEqf+g PsDdALX1H8vwLIfVvKPIThQo3cfTEMuVJnXWnDWWqMYrNGN/0fxXsF+D2Mbs z2w9urP1d7b+ztaXWsOV798vmL/qEiVqU1lZA0XKH6dtD2H6GK6vZ6X3YSP9 WxjWhua4/KWDhhrUxBjvuWC8xBCXv07igvGJGV5fk9qKfC2dcyBz7U7odRq8 vtSbaHlvnKlm1zjKlYdqzIo10fe5an8opR87V/s8BrsO1R87V/4G7GuX4ndu Atx1oNkAODcEsyh4v9kRHatcf2nJ1SahvPIfwyqU7Xm/VSFB2VsOtys0KNsR fstChLL3AK4xVFjcu1kTMlQXX8dO/IAhRPnu8VsXSpS/UHD7QoryHdO3MLQo 30i/rRBjstxWsyPk576yx632enx4phP7f0fUHzw7XepLDi1x3KTU5DhaP4gB kJRGXMkQEoZ4CFRMiQiRjCPmcx/COATi8DCWPgiVL0gEOBNMxOYvizFgUpg6 MI5gSIVgUZPjaOc5WXUy7XxJO8EcgqiLvX37C6VH1L579Bp7u//87fWz497/ dr2KOdTEPLHnkZhf9NT+9JP+3k6B+O0KYl1DXGy4vqm3c6XL696fle5Oz0mt KXg8LZhUFkTz7Z9O2y8vlheqLHI8V1NSWSwvVFPELmCkJVRaQhVLPCuyXanB VfWXUTehqmlxDcpaiuMG/UvWoW5CVdPiGpTVFHABBJMhnns4B6SyAt38MLQi NBYfJsvtvs0f6hKmpu1eTdtdrHquQFn1cwXyJlYZbXvg9rlYNnnZ/YlhBkEc +dKXElEsmI9CJiWkPEQIxypQyo+BhNJnh4cYch6HMSSAhhBLGjEZUUJiEEPk SyWp4JQyiVca5knbpaZ48swaX0Ts0p75abcg7ni7WdjaO78QJkQayUs2uri0 7q2HvQ/vIDl64b2jz1+c7K0qiopFvXf+cU35wJQvlNyvLknmS3qzWnkv3fLS 0YNkKHnHlDt+4x95716/+u3fR72n6cX097+mF6+mFy/NxY73008/pZ8eZbef vCN+evXqybP0929vDeUre/Xo8fG0DEaWNl0ojXAXAm8fRn4X4lScaY1PX5oK X2aE5vq48CG9NlcvH/371cv0ekLz8sWryQ3v3fHbx9OrN6/fHx0/7h3PLt9O CMznx0fHv08epZdvJ5f5PXvHAPzx0TNTbucgpZt+nj6yhbOL7M77o2ePJ/fS y7d2gNpR5nQwlV36+3jyOyN5PnlgLlIW84aezxoyl1k38+ucdnqz0JRpelLl +6OcmbQT3s7BHM7srq8UY/949e6N92E3xVnH/HzaMWmZBZz55B+bT5nkzB9b 5mla5sWkzNO0jPm0BOPm1c9Xm/UkbWy++gL2TbiZ1Z/oobJ1/+Pdm6Pem997 T02XO0la5ezWW6Mk6S0DXqOlkyIWRl72J3+Sl3z57pUFfl7Z5HP2PMU+9qmx IPvYbjCDE+jn1c1gO6HPwTttYIbeJV5maC6Wnavr8ZTVOcIc6dOSM8BOaprC Nm3zYJF0rtwEzLOaMkinJTKNaEm8QAqPigXhfD3PZ91ZbPH5YsemajJrdKos Ja1mylMsusB/Ravvj2YiKMOjRT5MAfnmX/TI69AMim/+ZdDldSCZfjQ21Otg lA3gT+ktY3q9DvGnJaixgPP09rOtIYMfQanpxSHoQjQ1vT9N1Maolk08+ufn PQwzZst1M80EL5lN97wP3kRHX8czDX0tVpHbfawFwmmbdEY/vWUZN/Uc1DMC C4ywAiO8jhG4zEhYwkiwqp7HvSf/fPIyrSj1553018REpebr6EXRfB2ttHzP Z7VNjd8c9fNK6ne9ZNyTZ/I8BVPGSpyz4XVOZ9VczQzoacF65vbzqgyseYwx M5MmgCha0aL9LMprnjqzi4Y0N5C56TzJgBqE6Wsf9u2PiZ0sr8kakWe/H5mq ZmZsZsCqOUiLTKkKHnklxftnU5pSb19FBzOiohdfVfz187xDz2cdej7t0Cq6 4wLhovNfTZrTFYKDlRTvc0kshgsF+SUDr3PPqtD5xedfLEx/7diNYx92Tb7k 7Z6zET/tXQxNrQPxN4t8O3uVeMDY0N6l/NhPRja7yp53vM7Dq+5V97I7+Tmx aBQBaGdFKIKki0KSYmX2Qk+nk72ZM2k0U5POmRx8HJ12UkN5ks5zP3hg/3sf ponaSXZrviuLW807dpqutDOpYlX3I1W43SwEz8p+WK7ghQdNk/L84vI/BeK3 xr0Y5n7K40C7jd7zTuyPzptHr589edN7/ujd5EWsv3oLt3pP//n7ozedyWZ6 73L0xbsYJh/QyYP0s51zNBwPLryH3usnz1797u1Omk4+gJO9rJAlACemxEc5 6Jkaeqakt/vmhR3gbkZeKAlPPFM0rwVOWrrQo6E245GcZ8Ld7aSSPVSQ/DH6 yyfQ9f7yBHa6poZJXYUBte8qVAyoXzGgC6l6xQxF3ajPF//FhpG/TnG9vwLX pBoLf50HwyR5W6jjl5lb+LUSFcWgo4wFVMHCVQaoqeVZgacl2OCTBUQUwDKH gDIApLArPslBqLzd/zFunZ8PDSwyKXe6adRlAP1L7uR+9R4+9CBJ+V2BKJ0j 6sNfzqHB1Sd0UgSW3QBcU8VkpGctr6zQJVLHVVgdr4vW8XeE12pSYzWx1/k8 vCyjfDtMSU/aQN3fCtQzJSo+wc6VYJiM/hj8MUpBMdpQG+br2kwt1nLIFZO0 NXPUDTVkgex7tOvHN8GwX4tt73r6y+jK+xk6N/LlNTux9svLHcvInl/uaQft Oyew4ASO77zABnqzpjvYRIEWHMOcEiWz9do6tXACf2foLyRy66Dw5mRrVUPu NHcb16fj42+bkFviJROEVpqg7zSHn7cIGybztBIQSWEXRz02bpbSbwaWW2cn mvkId/i4qpu9m56MssJY2BnwpsbClv2wXEGD2bv339vs3dWhwsi5B7CbW/KN LHUjm+HL7kRZObwv1hjeF62H9zb69KuJim5nIMf1ujn+ttq5iXV+/7268qvR pppNKwGRFPaQ1WPj2+v3ZgC5ze77auTENuRQmA6z/DI0XOQDbbfCzsVqy2Ea qBjeLP8txmigPEazm4vKIrS9k+m+qxVq/N//rlZjed4fTeRnB2OK31nQA3/N u1gcyW5hPPYykf72+6snVpg18ioJcJeFhhoLDVXQV8urHtWNhFLsR2PJLG04 HclklOj+SNpPhyN2+VGOpts57xtlujRs9HlyPz+m5pBPtn62oNwZyCtP9c9k uolnutN0spO14Z/Dw4iQgIeChAgCSGIRcs4VFkSoII5BFPoEQSIDnG5hvS/k 5/sDfXZW2LTahnO7fA66diNmF6V7LPbv3/O+euLjgbjw+MX50PbK+9O+n5E/ YUL0R/2LATs7uBjai8TrHJyzS3760LT2mR7Cg/PDc9Yf7Nu9s2roHZynh+8c sLj/8JRdCu/gd9Sxtc5Vm/xff3jQV17n2FzYWa/BhRlNPbroeF/vHZi/f3pf TTtqqB/e68yu0xJ/Tljc2f+5P+Bn2oxCZ/IOxeFpx96fO7dOXVyUnTJXcsZc 4RijucMSp0wbZWRn5jLhbHDAkkSex2fSWLp8ITvr55S7RS7gOmw4YGFTPcGo rZ5YSjd6QlWIQCwQZSjCNKBBGDAZsVAKZC7ikAtJUaioKz1JOf+x9GR6zudM T+bO5KzWE/sK2dogTVPGEj0pcAHXYcMBCxvqSdLanyQO/Yli2KgBUoIAP0Yo iBnAlIRYqgiHscJhSI1rYY70JLkef3IjlKRwVn+qIovH6lcqSNLSkSSLjmSe A9icBQfNb6ocrZ1I4s6JYMpUJAnhKIYRxJghqGjII9/oi9EOIKiKYhIJV8px PU7kpijHnP9YPJ++Wjlaeo9k0XvMcwCbs+Cg+U2Vg7bVDepKNRiNfQ6VxAZ6 kiMuRYSQICRWgYhUEPgqRjhC3JVq0B9JM+gXa6VnmkEbKQZtAcz4MKFLalFo HjZuf/PGN1QK3Tqc0u7CKeMNmCFEEsmYKYKYr0IOiYmsMKCBYHEoIMKhK4+h f6BwSi/GU7pxQKVbBlR6MaDSSxGV3mpIpV2GVLp1SKXdhVQ8ljSUGIYBECEU Ahp/IZmikBAhsOQg4BQKSFwpyA8UUunFmEo3Dqp0y6BKLwZVeimq0lsNq7TL sEq3Dau0s7AqDAgOZUypQIBLLGUsMMCmLiQF5QhzajIRDKUr9aA/lHbMxVW6 aWCl2wVWmi6rxnxkpbcZWmlXodXkC1faqEZO6mhOFyguFMexIkSFWBCFZARl EMuIxYxyHgcMMBW6UI4Z6wX1yM6guFv8WIRo/p0833TpofQY7bawLanIUQCk fBQpjHBMeBCFMJRIgBDjIGBhTBiBNIq5DKErEJd15G7+dYrluW8rz2RUDu+S 89kz+gnRholFo5nadsw6ZNSxdrbLRyoqcqOdiPggAoACHvs+DkSgGAggkiY9 8amCEAoeRkwEW9LOH3sCuALwWbF1tHOazbQEfaOpYkfMOmTUrXZqV77T4exa xH1CCGSIRT5XcaiwTwIqZaAiIDkVkiAipPS3o513k22OvKd27T0bTst9Z/5T u/KfDqf3IiyVDASUmJpwVuI4tvcjxQmGAaJxSLgfRVRuSUN/9Nk+Vx5Ub+hB G84L3gQfqrfoQ8fuMtCxyxyUwVgaxcTAj0QQKoCJEIJKBn1EQEQDAWKpOI22 o6Xjuyy03jEtfI/zsInWjpfz0q43XE8fRu5y01ZdcMy+c3125XPHTvcpqQCG OGa+z2gYRBAQgrBCnOMI+ShgGDGmIPW3ps93eWudG2upz4t+uIVCOMtmv40+ J1v1z9qdf3aY5/ogiDAIVRgyCEKgGEFQcCJYHEUm5wUAmgw48MG29Pku092a h9bb8NDt89/v0Udrdz7aYWbsS+jzgAmfC+OMgxgiJeKIUxDyQAgeqAgBYrz4 1nT6LjfelpfWDry0w4z5G+n0Nvz08ncgbqjZZRU6Wtc12o0A9n3JmJAxCgBj MaAYi0BEOAiQMH7b58qxfpd26C6zbjvlW/almzd+nXee6Zs3X738RaCOtdid l459qYCPlIm3cUSCGIcgiiAiEQ+JhFSQADEBMd+yFt/l0xtNC5d98+yNXw92 qMXJNfhi7doXu1wnDlFMBAQ4MP+kjxEkYSziEDEQCuhD452JcLTJvK5Dd1m0 M298W9aNb5k/1q79scOsmZiUWCqlKKJBEGKfKaAUI5FUIeBKABZQipmbN3Dr OnSXOzvzyLdlfdmlJl+DTx67z5CdrjtLQELFGPLtnuc4gjjyMQ8CDCHCgGDM hK8Ai+R2tflu/dn1xHD5t8/fynXoxa7czLnuZYG79uFO16cBFJFJm6OIiBiG ygTnPgt5TFlIaSA5Ysw8VZhsXe/v8mqnk8dlAr6l69XO9T65Fn+v3ft7h3k4 xFgpjI1LRzEnNPQDGDEem0BeUhVzjBjhPojUtvX+LhPfuse/zevat9Tna/c+ 32Hmruz5WEIEUChp0ncpWBByStNQHwVA+CiKYxFuX/fvcvdte/3bvP7tXved +v0N8nmHebvdo0IwQ1wASQWORaywz4FETEQRjpS5pRjkzl68T67nxftbfErk RErf+JzGlIv2XshhhklUQAw+jYORMWaRj02cSQCSgEshGQkJ4xH2obM3GpYy ye8bobWZZAVCWx0r5Hr9coMcyWEuZHcPhAEN4lApQhiUwB5LTQCJpAQRQ2EQ RoIh5Aqh+geyoW2PhpvI6RsfzZZy0d6KutyjymgkBYEqZAyxgNqN5sDYzYAI blArDFRFDANnMbv+gaxos9i8AqMt7ajbWHS8yTFQY5cHQQEQE6qw8mMCQhkg hBHkPgwoZ+a2lIqEKELA2S6t8d1RUOVHQTVLtcazw6FaJFRuD4jaaInU7Uu4 BBlbyiEFAWS+8f+UQXMDA0Rjuwoa+1FoTDFyB+K7tKodepMN0Ju4Rm/7QMHp kp70cUwiwiMY25fUOFQUIeWrUFIlhE8AxUBJDB2i9y7laofe2ezcN17E2mi5 yunCVBRB6PuIUsR5xHkIQhWxEGCfxwQFkDBAYo5w4A69d+lYW/zqDayvdmx9 9SbW12GiFiMqAsQjJWy8EMUQ8zhmxg6zAPJAkRhyTCUCDvF7l6q1xe8G9tdh AnfV+ovZclJHL8pRA0/JwpgqGBkjCwMQMOoDDBhWUcwMjglFjrb0XpV8NdsP kLq1+mq2ibC+8Rejpd/i3R6oDkNcATgzllVwA1YEcMgDCWEsQ6IkCU3wCwhC MHB0Uu/VD7+m0BChbr7/aVOE6vYIdRgGCBnFWERC4TjmkSQxCQKCCMFEsIhF IQQohj5krhD6wwcBDTHq5us0NsXoeBOHP3bp8qEiyIeh5EwFUSg4oxRLGtMY YwIkU4xznyIQucLp+M7plzv9BjHrVHztYtarkeNQYLxJMOB0xgvaL7gzQCaU +fYoJj8WccA4jThRiBIIgghJxIA7EN8FBO3Qm2yA3sQxevUm6HUYKjDuRyCC XCKJMQaxL4I4QooqHOIwQCIyqReNGXGH3rtgoS1+9Qb4nQ8hdv4fPwOKJJIH AQA= --_002_DBBPR08MB477565EB3A26B42AADED3D759B710DBBPR08MB4775eurp_--