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Thu, 14 Nov 2019 19:14:04 +0000 From: Srinath Parvathaneni To: "gcc-patches@gcc.gnu.org" CC: Richard Earnshaw , Kyrylo Tkachov Subject: [PATCH][ARM][GCC][14x]: MVE ACLE whole vector left shift with carry intrinsics. Date: Thu, 14 Nov 2019 19:16:00 -0000 Message-ID: References: <157375666998.31400.16652205595246718910.scripted-patch-series@arm.com> In-Reply-To: <157375666998.31400.16652205595246718910.scripted-patch-series@arm.com> Authentication-Results-Original: spf=none (sender IP is ) smtp.mailfrom=Srinath.Parvathaneni@arm.com; X-MS-Exchange-PUrlCount: 1 x-ms-exchange-transport-forked: True x-checkrecipientrouted: true x-ms-oob-tlc-oobclassifiers: OLM:34;OLM:34; X-Forefront-Antispam-Report-Untrusted: SFV:NSPM;SFS:(10009020)(4636009)(39860400002)(396003)(366004)(376002)(346002)(136003)(54534003)(199004)(189003)(81156014)(316002)(81166006)(30864003)(2501003)(44832011)(4326008)(74316002)(7696005)(99286004)(478600001)(186003)(11346002)(26005)(54906003)(76176011)(52536014)(5660300002)(446003)(25786009)(71190400001)(71200400001)(33656002)(66946007)(52116002)(305945005)(66556008)(7736002)(66446008)(6666004)(66476007)(66616009)(64756008)(14444005)(256004)(5024004)(9686003)(966005)(5640700003)(3846002)(66066001)(6916009)(86362001)(486006)(6506007)(6436002)(14454004)(8936002)(2906002)(6116002)(2351001)(55016002)(8676002)(102836004)(386003)(476003)(6306002);DIR:OUT;SFP:1101;SCL:1;SRVR:DBBPR08MB4807;H:DBBPR08MB4775.eurprd08.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: /PL6/v10BoM+7XYAMXgQBVRlrOcE73C7JFYisjCayccDGQEuFKX0RQWWQL5Buxkq2UQ7A9LIFxO1xhl6gxhyIrEKma5Byzh00PMlzWOIpQet50C48atBrhHBFmhF6MtMdmVXKtcBIVh8/XmGBpQ35VNcrYXIHQ7psNDNjGDOzriiXM82nzuuOCHhNSGQl/KePG4mmYtto5l4rGwN0YGLQdRvKQ/ED0JJFsnv5c1te2H50nve6BCVcDm4476+J7J2LVCGEP4ZgFbd+Cr93tdjqb0pyXt65S60eKZfT9U6moc2u6PxxomgGFfZyhd1nRqm2h0JA85fEcd29kihuloEqDPU1nhltPN1cj1JaCH+rO87SYD4OoAvbFC2daSUn7/9jmGWUMn/TUa7OAA1IZB05K3ObneTIzVSIUJeIp51B1E6zQ3ABK/2JBaqLhZ1VcwWVmwb+8xVPQvzAkikO8LZFD2ZoNWe+8bW3cwJZVW1mu8= Content-Type: multipart/mixed; boundary="_002_DBBPR08MB477591A15A5B507BAFE60D0C9B710DBBPR08MB4775eurp_" MIME-Version: 1.0 Original-Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Srinath.Parvathaneni@arm.com; Return-Path: Srinath.Parvathaneni@arm.com X-MS-Exchange-Transport-CrossTenantHeadersStripped: VE1EUR03FT032.eop-EUR03.prod.protection.outlook.com X-MS-Office365-Filtering-Correlation-Id-Prvs: 96bf4648-99fe-4380-311b-08d76936c070 X-IsSubscribed: yes X-SW-Source: 2019-11/txt/msg01283.txt.bz2 --_002_DBBPR08MB477591A15A5B507BAFE60D0C9B710DBBPR08MB4775eurp_ Content-Type: text/plain; charset="us-ascii" Content-ID: <5D7C3AD7BAEC1F48A8DFA4594994951A@eurprd08.prod.outlook.com> Content-Transfer-Encoding: quoted-printable Content-length: 16786 Hello, This patch supports following MVE ACLE whole vector left shift with carry i= ntrinsics. vshlcq_m_s8, vshlcq_m_s16, vshlcq_m_s32, vshlcq_m_u8, vshlcq_m_u16, vshlcq_= m_u32. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more d= etails. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/heli= um/mve-intrinsics Regression tested on arm-none-eabi and found no regressions. Ok for trunk? Thanks, Srinath. gcc/ChangeLog: 2019-11-09 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm_mve.h (vshlcq_m_s8): Define macro. (vshlcq_m_u8): Likewise. (vshlcq_m_s16): Likewise. (vshlcq_m_u16): Likewise. (vshlcq_m_s32): Likewise. (vshlcq_m_u32): Likewise. (__arm_vshlcq_m_s8): Define intrinsic. (__arm_vshlcq_m_u8): Likewise. (__arm_vshlcq_m_s16): Likewise. (__arm_vshlcq_m_u16): Likewise. (__arm_vshlcq_m_s32): Likewise. (__arm_vshlcq_m_u32): Likewise. (vshlcq_m): Define polymorphic variant. * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_UNONE_IMM_UNONE): Use builtin qualifier. (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise. * config/arm/mve.md (mve_vshlcq_m_vec_): Define RTL pattern. (mve_vshlcq_m_carry_): Likewise. (mve_vshlcq_m_): Likewise. gcc/testsuite/ChangeLog: 2019-11-09 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c: New test. * gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c: Likewise. ############### Attachment also inlined for ease of reply ##########= ##### diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 2adae7f8b21f44aa3b80231b89bd68bcd0812611..5d385081a0affacc4dd21d010b0= 1bceb38a9b699 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -2542,6 +2542,12 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define urshrl(__p0, __p1) __arm_urshrl(__p0, __p1) #define lsll(__p0, __p1) __arm_lsll(__p0, __p1) #define asrl(__p0, __p1) __arm_asrl(__p0, __p1) +#define vshlcq_m_s8(__a, __b, __imm, __p) __arm_vshlcq_m_s8(__a, __b, = __imm, __p) +#define vshlcq_m_u8(__a, __b, __imm, __p) __arm_vshlcq_m_u8(__a, __b, = __imm, __p) +#define vshlcq_m_s16(__a, __b, __imm, __p) __arm_vshlcq_m_s16(__a, __b,= __imm, __p) +#define vshlcq_m_u16(__a, __b, __imm, __p) __arm_vshlcq_m_u16(__a, __b,= __imm, __p) +#define vshlcq_m_s32(__a, __b, __imm, __p) __arm_vshlcq_m_s32(__a, __b,= __imm, __p) +#define vshlcq_m_u32(__a, __b, __imm, __p) __arm_vshlcq_m_u32(__a, __b,= __imm, __p) #endif =20 /* For big-endian, GCC's vector indices are reversed within each 64 bits @@ -16667,6 +16673,60 @@ __arm_srshr (int32_t value, const int shift) return __builtin_mve_srshr_si (value, shift); } =20 +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlcq_m_s8 (int8x16_t __a, uint32_t * __b, const int __imm, mve_pre= d16_t __p) +{ + int8x16_t __res =3D __builtin_mve_vshlcq_m_vec_sv16qi (__a, *__b, __imm,= __p); + *__b =3D __builtin_mve_vshlcq_m_carry_sv16qi (__a, *__b, __imm, __p); + return __res; +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlcq_m_u8 (uint8x16_t __a, uint32_t * __b, const int __imm, mve_pr= ed16_t __p) +{ + uint8x16_t __res =3D __builtin_mve_vshlcq_m_vec_uv16qi (__a, *__b, __imm= , __p); + *__b =3D __builtin_mve_vshlcq_m_carry_uv16qi (__a, *__b, __imm, __p); + return __res; +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlcq_m_s16 (int16x8_t __a, uint32_t * __b, const int __imm, mve_pr= ed16_t __p) +{ + int16x8_t __res =3D __builtin_mve_vshlcq_m_vec_sv8hi (__a, *__b, __imm, = __p); + *__b =3D __builtin_mve_vshlcq_m_carry_sv8hi (__a, *__b, __imm, __p); + return __res; +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlcq_m_u16 (uint16x8_t __a, uint32_t * __b, const int __imm, mve_p= red16_t __p) +{ + uint16x8_t __res =3D __builtin_mve_vshlcq_m_vec_uv8hi (__a, *__b, __imm,= __p); + *__b =3D __builtin_mve_vshlcq_m_carry_uv8hi (__a, *__b, __imm, __p); + return __res; +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlcq_m_s32 (int32x4_t __a, uint32_t * __b, const int __imm, mve_pr= ed16_t __p) +{ + int32x4_t __res =3D __builtin_mve_vshlcq_m_vec_sv4si (__a, *__b, __imm, = __p); + *__b =3D __builtin_mve_vshlcq_m_carry_sv4si (__a, *__b, __imm, __p); + return __res; +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlcq_m_u32 (uint32x4_t __a, uint32_t * __b, const int __imm, mve_p= red16_t __p) +{ + uint32x4_t __res =3D __builtin_mve_vshlcq_m_vec_uv4si (__a, *__b, __imm,= __p); + *__b =3D __builtin_mve_vshlcq_m_carry_uv4si (__a, *__b, __imm, __p); + return __res; +} + #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ =20 __extension__ extern __inline void @@ -26645,6 +26705,16 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint32_t][__ARM_mve_type_uint32x4_t]: __arm_vsetq= _lane_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x= 4_t), p2), \ int (*)[__ARM_mve_type_uint64_t][__ARM_mve_type_uint64x2_t]: __arm_vsetq= _lane_u64 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint64x= 2_t), p2));}) =20 +#define vshlcq_m(p0,p1,p2,p3) __arm_vshlcq_m(p0,p1,p2,p3) +#define __arm_vshlcq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 =3D (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vshlcq_m_s8 (__ARM_mve_coerce(_= _p0, int8x16_t), p1, p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vshlcq_m_s16 (__ARM_mve_coerce(= __p0, int16x8_t), p1, p2, p3), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vshlcq_m_s32 (__ARM_mve_coerce(= __p0, int32x4_t), p1, p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshlcq_m_u8 (__ARM_mve_coerce(= __p0, uint8x16_t), p1, p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshlcq_m_u16 (__ARM_mve_coerce= (__p0, uint16x8_t), p1, p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshlcq_m_u32 (__ARM_mve_coerce= (__p0, uint32x4_t), p1, p2, p3));}) + #endif /* MVE Floating point. */ =20 #ifdef __cplusplus diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_b= uiltins.def index c23fe88ad05f8ee6c03127066fdf5afa593df944..08f2a72df4b26980c473dac9199= 3eb4583c60727 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -890,3 +890,7 @@ VAR1 (UQSHL, urshr_, si) VAR1 (UQSHL, urshrl_, di) VAR1 (UQSHL, uqshl_, si) VAR1 (UQSHL, uqshll_, di) +VAR3 (QUADOP_NONE_NONE_UNONE_IMM_UNONE, vshlcq_m_vec_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_UNONE_IMM_UNONE, vshlcq_m_carry_s, v16qi, v8hi, v4s= i) +VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vshlcq_m_vec_u, v16qi, v8hi, v4s= i) +VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vshlcq_m_carry_u, v16qi, v8hi, v= 4si) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index bbd54ad71d0b85fd4711007dd93af7a2788b2cf4..8a51c25ce26405d65aac0804499= 3c92cfb557661 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -215,8 +215,8 @@ VADCQ_M_S VSBCIQ_U VSBCIQ_S VSBCIQ_M_U VSBCIQ_M_S VSBCQ_U VSBCQ_S VSBCQ_M_U VSBCQ_M_S VADCIQ_U VADCIQ_M_U VADCIQ_S VADCIQ_M_S VLD2Q VLD4Q VST2Q SRSHRL SRSHR - URSHR URSHRL SQRSHR UQRSHL UQRSHLL_64 - UQRSHLL_48 SQRSHRL_64 SQRSHRL_48]) + URSHR URSHRL SQRSHR UQRSHL UQRSHLL_64 VSHLCQ_M_U + UQRSHLL_48 SQRSHRL_64 SQRSHRL_48 VSHLCQ_M_S]) =20 (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI") (V4SF "V4SI")]) @@ -394,7 +394,8 @@ (VADCQ_U "u") (VADCQ_M_U "u") (VADCQ_S "s") (VADCIQ_U "u") (VADCIQ_M_U "u") (VADCIQ_S "s") (VADCIQ_M_S "s") (SQRSHRL_64 "64") (SQRSHRL_48 "48") - (UQRSHLL_64 "64") (UQRSHLL_48 "48")]) + (UQRSHLL_64 "64") (UQRSHLL_48 "48") (VSHLCQ_M_S "s") + (VSHLCQ_M_U "u")]) =20 (define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32") (VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16") @@ -659,6 +660,7 @@ (define_int_iterator VADCQ_M [VADCQ_M_U VADCQ_M_S]) (define_int_iterator UQRSHLLQ [UQRSHLL_64 UQRSHLL_48]) (define_int_iterator SQRSHRLQ [SQRSHRL_64 SQRSHRL_48]) +(define_int_iterator VSHLCQ_M [VSHLCQ_M_S VSHLCQ_M_U]) =20 (define_insn "*mve_mov" [(set (match_operand:MVE_types 0 "s_register_operand" "=3Dw,w,r,w,w,r,w") @@ -11127,3 +11129,57 @@ "TARGET_HAVE_MVE" "sqshll%?\\t%Q1, %R1, %2" [(set_attr "predicable" "yes")]) + +;; +;; [vshlcq_m_u vshlcq_m_s] +;; +(define_expand "mve_vshlcq_m_vec_" + [(match_operand:MVE_2 0 "s_register_operand") + (match_operand:MVE_2 1 "s_register_operand") + (match_operand:SI 2 "s_register_operand") + (match_operand:SI 3 "mve_imm_32") + (match_operand:HI 4 "vpr_register_operand") + (unspec:MVE_2 [(const_int 0)] VSHLCQ_M)] + "TARGET_HAVE_MVE" +{ + rtx ignore_wb =3D gen_reg_rtx (SImode); + emit_insn (gen_mve_vshlcq_m_ (operands[0], ignore_wb, operan= ds[1], + operands[2], operands[3], + operands[4])); + DONE; +}) + +(define_expand "mve_vshlcq_m_carry_" + [(match_operand:SI 0 "s_register_operand") + (match_operand:MVE_2 1 "s_register_operand") + (match_operand:SI 2 "s_register_operand") + (match_operand:SI 3 "mve_imm_32") + (match_operand:HI 4 "vpr_register_operand") + (unspec:MVE_2 [(const_int 0)] VSHLCQ_M)] + "TARGET_HAVE_MVE" +{ + rtx ignore_vec =3D gen_reg_rtx (mode); + emit_insn (gen_mve_vshlcq_m_ (ignore_vec, operands[0], + operands[1], operands[2], + operands[3], operands[4])); + DONE; +}) + +(define_insn "mve_vshlcq_m_" + [(set (match_operand:MVE_2 0 "s_register_operand" "=3Dw") + (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0") + (match_operand:SI 3 "s_register_operand" "1") + (match_operand:SI 4 "mve_imm_32" "Rf") + (match_operand:HI 5 "vpr_register_operand" "Up")] + VSHLCQ_M)) + (set (match_operand:SI 1 "s_register_operand" "=3Dr") + (unspec:SI [(match_dup 2) + (match_dup 3) + (match_dup 4) + (match_dup 5)] + VSHLCQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vshlct\t%q0, %1, %4" + [(set_attr "type" "mve_move") + (set_attr "length" "8")]) diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c b/g= cc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c new file mode 100644 index 0000000000000000000000000000000000000000..279c229c3423748f67164bc981f= 4484bf73172d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, uint32_t * b, mve_pred16_t p) +{ + return vshlcq_m_s16 (a, b, 32, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlct" } } */ + +int16x8_t +foo1 (int16x8_t a, uint32_t * b, mve_pred16_t p) +{ + return vshlcq_m (a, b, 32, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlct" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c b/g= cc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c new file mode 100644 index 0000000000000000000000000000000000000000..29bc2cb1bcb45bea7f0d6a7a8eb= 9ab88dbde6eda --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, uint32_t * b, mve_pred16_t p) +{ + return vshlcq_m_s32 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlct" } } */ + +int32x4_t +foo1 (int32x4_t a, uint32_t * b, mve_pred16_t p) +{ + return vshlcq_m (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlct" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c b/gc= c/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c new file mode 100644 index 0000000000000000000000000000000000000000..6253ad84ab74c709b63c17f849d= ed956c8a78c36 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, uint32_t * b, mve_pred16_t p) +{ + return vshlcq_m_s8 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlct" } } */ + +int8x16_t +foo1 (int8x16_t a, uint32_t * b, mve_pred16_t p) +{ + return vshlcq_m (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlct" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c b/g= cc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c new file mode 100644 index 0000000000000000000000000000000000000000..5db18b1ef87cd60cd79dc0915ed= ed03c50a7ab38 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint32_t * b, mve_pred16_t p) +{ + return vshlcq_m_u16 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlct" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint32_t * b, mve_pred16_t p) +{ + return vshlcq_m (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlct" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c b/g= cc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c new file mode 100644 index 0000000000000000000000000000000000000000..cab75f2d73b5f4519640b265b7a= 8c6016788b11b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32_t * b, mve_pred16_t p) +{ + return vshlcq_m_u32 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlct" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32_t * b, mve_pred16_t p) +{ + return vshlcq_m (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlct" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c b/gc= c/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c new file mode 100644 index 0000000000000000000000000000000000000000..98a1470aee4240b585113369e63= a2c0129d7dc26 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint32_t * b, mve_pred16_t p) +{ + return vshlcq_m_u8 (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlct" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint32_t * b, mve_pred16_t p) +{ + return vshlcq_m (a, b, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlct" } } */ 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