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Thu, 14 Nov 2019 19:13:19 +0000 From: Srinath Parvathaneni To: "gcc-patches@gcc.gnu.org" CC: Richard Earnshaw , Kyrylo Tkachov Subject: [PATCH][ARM][GCC][2/5x]: MVE load intrinsics. Date: Thu, 14 Nov 2019 19:15:00 -0000 Message-ID: References: <157375666998.31400.16652205595246718910.scripted-patch-series@arm.com> In-Reply-To: <157375666998.31400.16652205595246718910.scripted-patch-series@arm.com> Authentication-Results-Original: spf=none (sender IP is ) smtp.mailfrom=Srinath.Parvathaneni@arm.com; X-MS-Exchange-PUrlCount: 1 x-ms-exchange-transport-forked: True x-checkrecipientrouted: true x-ms-oob-tlc-oobclassifiers: OLM:13;OLM:13; X-Forefront-Antispam-Report-Untrusted: SFV:NSPM;SFS:(10009020)(1496009)(4636009)(39860400002)(396003)(366004)(376002)(346002)(136003)(54534003)(199004)(189003)(81156014)(316002)(81166006)(30864003)(2501003)(44832011)(4326008)(74316002)(7696005)(99286004)(478600001)(186003)(11346002)(26005)(54906003)(76176011)(52536014)(5660300002)(446003)(25786009)(71190400001)(71200400001)(33656002)(66946007)(52116002)(305945005)(66556008)(7736002)(66446008)(66476007)(66616009)(64756008)(256004)(5024004)(9686003)(966005)(5640700003)(3846002)(66066001)(6916009)(86362001)(486006)(6506007)(6436002)(14454004)(8936002)(2906002)(6116002)(2351001)(55016002)(8676002)(102836004)(386003)(476003)(6306002)(579004)(559001);DIR:OUT;SFP:1101;SCL:1;SRVR:DBBPR08MB4807;H:DBBPR08MB4775.eurprd08.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: gWeQqGl+/aSJ/hL4vEfD+mJd2eaHMUQ/hV8od6AuxEnTKiAvzWfIh0vMH706KoOhUonpst0U6kjVci990l1vPN/iwJGRDONuLBzZtkZ6jBbekme+T43KvgWDy/JanIe5lKcWAEeSlxTmIF70sTHMvdZZ5/PcqUYIx422vnmdp2pbsQ7zs4J5xx2oXSxoQzIISSasjq5yTJlM2Mis3gncvOxChqhOyJlVr8ihQ/L1+ZTuPXPOBDy+xLNb/yQIzT77MMbkhb7VEa4WOotB0jR/UZHytBdUZjd+1i7rZ9J2EMIJqkskfNwc7EOYS2agn/BbgEDLFjfGQ3erVtSoSQSZ+3pnaxTvMPesM7n9O7NEYcydJvePyWEhXNmpYjZQfhXntR55RODl5+hmactXW2ufKlh847caNwxgOfz09wOf+PEZbQyZyBIst7qb9sIkXrAflTTlvgXeBS5jW+zd+B/DwGbTSyUSQhiVpDhqAvV1FyI= Content-Type: multipart/mixed; boundary="_002_DBBPR08MB47759EE364526D126D90139D9B710DBBPR08MB4775eurp_" MIME-Version: 1.0 Original-Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Srinath.Parvathaneni@arm.com; Return-Path: Srinath.Parvathaneni@arm.com X-MS-Exchange-Transport-CrossTenantHeadersStripped: DB5EUR03FT005.eop-EUR03.prod.protection.outlook.com X-MS-Office365-Filtering-Correlation-Id-Prvs: 82912f8c-d5f4-430a-6561-08d76936b57b X-IsSubscribed: yes X-SW-Source: 2019-11/txt/msg01266.txt.bz2 --_002_DBBPR08MB47759EE364526D126D90139D9B710DBBPR08MB4775eurp_ Content-Type: text/plain; charset="us-ascii" Content-ID: Content-Transfer-Encoding: quoted-printable Content-length: 28413 Hello, This patch supports the following MVE ACLE load intrinsics. vldrbq_gather_offset_u8, vldrbq_gather_offset_s8, vldrbq_s8, vldrbq_u8, vldrbq_gather_offset_u16, vldrbq_gather_offset_s16, vldrbq_s16, vldrbq_u16, vldrbq_gather_offset_u32, vldrbq_gather_offset_s32, vldrbq_s32, vldrbq_u32, vldrwq_gather_base_s32, vldrwq_gather_base_u32. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more d= etails. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/hel= ium/mve-intrinsics Regression tested on arm-none-eabi and found no regressions. Ok for trunk? Thanks, Srinath. gcc/ChangeLog: 2019-11-01 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-builtins.c (LDRGU_QUALIFIERS): Define builtin qualifier. (LDRGS_QUALIFIERS): Likewise. (LDRS_QUALIFIERS): Likewise. (LDRU_QUALIFIERS): Likewise. (LDRGBS_QUALIFIERS): Likewise. (LDRGBU_QUALIFIERS): Likewise. * config/arm/arm_mve.h (vldrbq_gather_offset_u8): Define macro. (vldrbq_gather_offset_s8): Likewise. (vldrbq_s8): Likewise. (vldrbq_u8): Likewise. (vldrbq_gather_offset_u16): Likewise. (vldrbq_gather_offset_s16): Likewise. (vldrbq_s16): Likewise. (vldrbq_u16): Likewise. (vldrbq_gather_offset_u32): Likewise. (vldrbq_gather_offset_s32): Likewise. (vldrbq_s32): Likewise. (vldrbq_u32): Likewise. (vldrwq_gather_base_s32): Likewise. (vldrwq_gather_base_u32): Likewise. (__arm_vldrbq_gather_offset_u8): Define intrinsic. (__arm_vldrbq_gather_offset_s8): Likewise. (__arm_vldrbq_s8): Likewise. (__arm_vldrbq_u8): Likewise. (__arm_vldrbq_gather_offset_u16): Likewise. (__arm_vldrbq_gather_offset_s16): Likewise. (__arm_vldrbq_s16): Likewise. (__arm_vldrbq_u16): Likewise. (__arm_vldrbq_gather_offset_u32): Likewise. (__arm_vldrbq_gather_offset_s32): Likewise. (__arm_vldrbq_s32): Likewise. (__arm_vldrbq_u32): Likewise. (__arm_vldrwq_gather_base_s32): Likewise. (__arm_vldrwq_gather_base_u32): Likewise. (vldrbq_gather_offset): Define polymorphic variant. * config/arm/arm_mve_builtins.def (LDRGU_QUALIFIERS): Use builtin qualifier. (LDRGS_QUALIFIERS): Likewise. (LDRS_QUALIFIERS): Likewise. (LDRU_QUALIFIERS): Likewise. (LDRGBS_QUALIFIERS): Likewise. (LDRGBU_QUALIFIERS): Likewise. * config/arm/mve.md (VLDRBGOQ): Define iterator. (VLDRBQ): Likewise.=20 (VLDRWGBQ): Likewise. (mve_vldrbq_gather_offset_): Define RTL pattern. (mve_vldrbq_): Likewise. (mve_vldrwq_gather_base_v4si): Likewise. gcc/testsuite/ChangeLog: 2019-11-01 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c: New test. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrbq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c: Likewise. ############### Attachment also inlined for ease of reply ##########= ##### diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index ec88199bb5e7e9c15a346061c70841f3086004ef..02ea297937b18099f33a50c8089= 64d1dd7eac1b3 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -588,6 +588,36 @@ arm_strsbu_qualifiers[SIMD_MAX_BUILTIN_ARGS] qualifier_unsigned}; #define STRSBU_QUALIFIERS (arm_strsbu_qualifiers) =20 +static enum arm_type_qualifiers +arm_ldrgu_qualifiers[SIMD_MAX_BUILTIN_ARGS] + =3D { qualifier_unsigned, qualifier_pointer, qualifier_unsigned}; +#define LDRGU_QUALIFIERS (arm_ldrgu_qualifiers) + +static enum arm_type_qualifiers +arm_ldrgs_qualifiers[SIMD_MAX_BUILTIN_ARGS] + =3D { qualifier_none, qualifier_pointer, qualifier_unsigned}; +#define LDRGS_QUALIFIERS (arm_ldrgs_qualifiers) + +static enum arm_type_qualifiers +arm_ldrs_qualifiers[SIMD_MAX_BUILTIN_ARGS] + =3D { qualifier_none, qualifier_pointer}; +#define LDRS_QUALIFIERS (arm_ldrs_qualifiers) + +static enum arm_type_qualifiers +arm_ldru_qualifiers[SIMD_MAX_BUILTIN_ARGS] + =3D { qualifier_unsigned, qualifier_pointer}; +#define LDRU_QUALIFIERS (arm_ldru_qualifiers) + +static enum arm_type_qualifiers +arm_ldrgbs_qualifiers[SIMD_MAX_BUILTIN_ARGS] + =3D { qualifier_none, qualifier_unsigned, qualifier_immediate}; +#define LDRGBS_QUALIFIERS (arm_ldrgbs_qualifiers) + +static enum arm_type_qualifiers +arm_ldrgbu_qualifiers[SIMD_MAX_BUILTIN_ARGS] + =3D { qualifier_unsigned, qualifier_unsigned, qualifier_immediate}; +#define LDRGBU_QUALIFIERS (arm_ldrgbu_qualifiers) + /* End of Qualifier for MVE builtins. */ =20 /* void ([T element type] *, T, immediate). */ diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 3d64033dd23636b041cbd6ecb3eb18c3b9db3aed..c123de1f3d37054b779a9ee9085= 25c242b2bc4ab 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -1716,6 +1716,20 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vstrbq_scatter_offset_s32( __base, __offset, __value) __arm_vstrbq= _scatter_offset_s32( __base, __offset, __value) #define vstrwq_scatter_base_s32(__addr, __offset, __value) __arm_vstrwq_s= catter_base_s32(__addr, __offset, __value) #define vstrwq_scatter_base_u32(__addr, __offset, __value) __arm_vstrwq_s= catter_base_u32(__addr, __offset, __value) +#define vldrbq_gather_offset_u8(__base, __offset) __arm_vldrbq_gather_offs= et_u8(__base, __offset) +#define vldrbq_gather_offset_s8(__base, __offset) __arm_vldrbq_gather_offs= et_s8(__base, __offset) +#define vldrbq_s8(__base) __arm_vldrbq_s8(__base) +#define vldrbq_u8(__base) __arm_vldrbq_u8(__base) +#define vldrbq_gather_offset_u16(__base, __offset) __arm_vldrbq_gather_off= set_u16(__base, __offset) +#define vldrbq_gather_offset_s16(__base, __offset) __arm_vldrbq_gather_off= set_s16(__base, __offset) +#define vldrbq_s16(__base) __arm_vldrbq_s16(__base) +#define vldrbq_u16(__base) __arm_vldrbq_u16(__base) +#define vldrbq_gather_offset_u32(__base, __offset) __arm_vldrbq_gather_off= set_u32(__base, __offset) +#define vldrbq_gather_offset_s32(__base, __offset) __arm_vldrbq_gather_off= set_s32(__base, __offset) +#define vldrbq_s32(__base) __arm_vldrbq_s32(__base) +#define vldrbq_u32(__base) __arm_vldrbq_u32(__base) +#define vldrwq_gather_base_s32(__addr, __offset) __arm_vldrwq_gather_base= _s32(__addr, __offset) +#define vldrwq_gather_base_u32(__addr, __offset) __arm_vldrwq_gather_base= _u32(__addr, __offset) #endif =20 __extension__ extern __inline void @@ -11106,6 +11120,105 @@ __arm_vstrwq_scatter_base_u32 (uint32x4_t __addr,= const int __offset, uint32x4_t { __builtin_mve_vstrwq_scatter_base_uv4si (__addr, __offset, __value); } + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_gather_offset_u8 (uint8_t const * __base, uint8x16_t __offset) +{ + return __builtin_mve_vldrbq_gather_offset_uv16qi ((__builtin_neon_qi *) = __base, __offset); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_gather_offset_s8 (int8_t const * __base, uint8x16_t __offset) +{ + return __builtin_mve_vldrbq_gather_offset_sv16qi ((__builtin_neon_qi *) = __base, __offset); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_s8 (int8_t const * __base) +{ + return __builtin_mve_vldrbq_sv16qi ((__builtin_neon_qi *) __base); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_u8 (uint8_t const * __base) +{ + return __builtin_mve_vldrbq_uv16qi ((__builtin_neon_qi *) __base); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_gather_offset_u16 (uint8_t const * __base, uint16x8_t __offse= t) +{ + return __builtin_mve_vldrbq_gather_offset_uv8hi ((__builtin_neon_qi *) _= _base, __offset); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_gather_offset_s16 (int8_t const * __base, uint16x8_t __offset) +{ + return __builtin_mve_vldrbq_gather_offset_sv8hi ((__builtin_neon_qi *) _= _base, __offset); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_s16 (int8_t const * __base) +{ + return __builtin_mve_vldrbq_sv8hi ((__builtin_neon_qi *) __base); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_u16 (uint8_t const * __base) +{ + return __builtin_mve_vldrbq_uv8hi ((__builtin_neon_qi *) __base); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_gather_offset_u32 (uint8_t const * __base, uint32x4_t __offse= t) +{ + return __builtin_mve_vldrbq_gather_offset_uv4si ((__builtin_neon_qi *) _= _base, __offset); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_gather_offset_s32 (int8_t const * __base, uint32x4_t __offset) +{ + return __builtin_mve_vldrbq_gather_offset_sv4si ((__builtin_neon_qi *) _= _base, __offset); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_s32 (int8_t const * __base) +{ + return __builtin_mve_vldrbq_sv4si ((__builtin_neon_qi *) __base); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrbq_u32 (uint8_t const * __base) +{ + return __builtin_mve_vldrbq_uv4si ((__builtin_neon_qi *) __base); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_gather_base_s32 (uint32x4_t __addr, const int __offset) +{ + return __builtin_mve_vldrwq_gather_base_sv4si (__addr, __offset); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vldrwq_gather_base_u32 (uint32x4_t __addr, const int __offset) +{ + return __builtin_mve_vldrwq_gather_base_uv4si (__addr, __offset); +} + #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ =20 __extension__ extern __inline void @@ -17682,6 +17795,17 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_base_s32(p0, p1,= __ARM_mve_coerce(__p2, int32x4_t)), \ int (*)[__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_base_u32(p0, p1= , __ARM_mve_coerce(__p2, uint32x4_t)));}) =20 +#define vldrbq_gather_offset(p0,p1) __arm_vldrbq_gather_offset(p0,p1) +#define __arm_vldrbq_gather_offset(p0,p1) ({ __typeof(p0) __p0 =3D (p0); \ + __typeof(p1) __p1 =3D (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8_t_const_ptr][__ARM_mve_type_uint8x16_t]: __a= rm_vldrbq_gather_offset_s8 (__ARM_mve_coerce(__p0, int8_t const *), __ARM_m= ve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_int8_t_const_ptr][__ARM_mve_type_uint16x8_t]: __a= rm_vldrbq_gather_offset_s16 (__ARM_mve_coerce(__p0, int8_t const *), __ARM_= mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_int8_t_const_ptr][__ARM_mve_type_uint32x4_t]: __a= rm_vldrbq_gather_offset_s32 (__ARM_mve_coerce(__p0, int8_t const *), __ARM_= mve_coerce(__p1, uint32x4_t)), \ + int (*)[__ARM_mve_type_uint8_t_const_ptr][__ARM_mve_type_uint8x16_t]: __= arm_vldrbq_gather_offset_u8 (__ARM_mve_coerce(__p0, uint8_t const *), __ARM= _mve_coerce(__p1, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint8_t_const_ptr][__ARM_mve_type_uint16x8_t]: __= arm_vldrbq_gather_offset_u16 (__ARM_mve_coerce(__p0, uint8_t const *), __AR= M_mve_coerce(__p1, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint8_t_const_ptr][__ARM_mve_type_uint32x4_t]: __= arm_vldrbq_gather_offset_u32 (__ARM_mve_coerce(__p0, uint8_t const *), __AR= M_mve_coerce(__p1, uint32x4_t)));}) + #endif /* MVE Floating point. */ =20 #ifdef __cplusplus diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_b= uiltins.def index 149c4115b6167e3f2f0eb43fbdeaa8708ba5d723..60e50767a2ac80a05303e3df851= 2f2612c8bc8ef 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -691,3 +691,9 @@ VAR3 (STRSS, vstrbq_scatter_offset_s, v16qi, v8hi, v4si) VAR3 (STRSU, vstrbq_scatter_offset_u, v16qi, v8hi, v4si) VAR1 (STRSBS, vstrwq_scatter_base_s, v4si) VAR1 (STRSBU, vstrwq_scatter_base_u, v4si) +VAR3 (LDRGU, vldrbq_gather_offset_u, v16qi, v8hi, v4si) +VAR3 (LDRGS, vldrbq_gather_offset_s, v16qi, v8hi, v4si) +VAR3 (LDRS, vldrbq_s, v16qi, v8hi, v4si) +VAR3 (LDRU, vldrbq_u, v16qi, v8hi, v4si) +VAR1 (LDRGBS, vldrwq_gather_base_s, v4si) +VAR1 (LDRGBU, vldrwq_gather_base_u, v4si) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index eb365166e934f32f7695e5354258151202f378c0..7b416f9a4e04f8c02547953d601= 9787817688a36 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -192,7 +192,8 @@ VCMULQ_ROT270_M_F VCMULQ_ROT90_M_F VFMAQ_M_F VFMAQ_M_N_F VFMASQ_M_N_F VFMSQ_M_F VMAXNMQ_M_F VMINNMQ_M_F VSUBQ_M_F VSTRWQSB_S VSTRWQSB_U - VSTRBQSO_S VSTRBQSO_U VSTRBQ_S VSTRBQ_U]) + VSTRBQSO_S VSTRBQSO_U VSTRBQ_S VSTRBQ_U VLDRBQGO_S + VLDRBQGO_U VLDRBQ_S VLDRBQ_U VLDRWQGB_S VLDRWQGB_U]) =20 (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI") (V4SF "V4SI")]) @@ -345,7 +346,9 @@ (VMLALDAVAXQ_P_S "s") (VMLALDAVAXQ_P_U "u") (VMLALDAVAQ_P_S "s") (VMLALDAVAQ_P_U "u") (VSTRWQSB_S "s") (VSTRWQSB_U "u") (VSTRBQSO_S "s") - (VSTRBQSO_U "u") (VSTRBQ_S "s") (VSTRBQ_U "u")]) + (VSTRBQSO_U "u") (VSTRBQ_S "s") (VSTRBQ_U "u") + (VLDRBQGO_S "s") (VLDRBQGO_U "u") (VLDRBQ_S "s") + (VLDRBQ_U "u") (VLDRWQGB_S "s") (VLDRWQGB_U "u")]) =20 (define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32") (VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16") @@ -569,6 +572,9 @@ (define_int_iterator VSTRWSBQ [VSTRWQSB_S VSTRWQSB_U]) (define_int_iterator VSTRBSOQ [VSTRBQSO_S VSTRBQSO_U]) (define_int_iterator VSTRBQ [VSTRBQ_S VSTRBQ_U]) +(define_int_iterator VLDRBGOQ [VLDRBQGO_S VLDRBQGO_U]) +(define_int_iterator VLDRBQ [VLDRBQ_S VLDRBQ_U]) +(define_int_iterator VLDRWGBQ [VLDRWQGB_S VLDRWQGB_U]) =20 (define_insn "*mve_mov" [(set (match_operand:MVE_types 0 "s_register_operand" "=3Dw,w,r,w,w,r,w") @@ -8002,3 +8008,65 @@ return ""; } [(set_attr "length" "4")]) + +;; +;; [vldrbq_gather_offset_s vldrbq_gather_offset_u] +;; +(define_insn "mve_vldrbq_gather_offset_" + [(set (match_operand:MVE_2 0 "s_register_operand" "=3D&w") + (unspec:MVE_2 [(match_operand: 1 "memory_operand" "Us") + (match_operand:MVE_2 2 "s_register_operand" "w")] + VLDRBGOQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] =3D operands[0]; + ops[1] =3D operands[1]; + ops[2] =3D operands[2]; + if (!strcmp ("","s") && =3D=3D 8) + output_asm_insn ("vldrb.u8\t%q0, [%m1, %q2]",ops); + else + output_asm_insn ("vldrb.\t%q0, [%m1, %q2]",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vldrbq_s vldrbq_u] +;; +(define_insn "mve_vldrbq_" + [(set (match_operand:MVE_2 0 "s_register_operand" "=3Dw") + (unspec:MVE_2 [(match_operand: 1 "memory_operand" "Us")] + VLDRBQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[2]; + int regno =3D REGNO (operands[0]); + ops[0] =3D gen_rtx_REG (TImode, regno); + ops[1] =3D operands[1]; + output_asm_insn ("vldrb.\t%q0, %E1",ops); + return ""; +} + [(set_attr "length" "4")]) + +;; +;; [vldrwq_gather_base_s vldrwq_gather_base_u] +;; +(define_insn "mve_vldrwq_gather_base_v4si" + [(set (match_operand:V4SI 0 "s_register_operand" "=3D&w") + (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") + (match_operand:SI 2 "immediate_operand" "i")] + VLDRWGBQ)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[3]; + ops[0] =3D operands[0]; + ops[1] =3D operands[1]; + ops[2] =3D operands[2]; + output_asm_insn ("vldrw.u32\t%q0, [%q1, %2]",ops); + return ""; +} + [(set_attr "length" "4")]) diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offs= et_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset= _s16.c new file mode 100644 index 0000000000000000000000000000000000000000..f7763b8a1f668e25c5b34ed429d= d5dc9a5455676 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int16x8_t +foo (int8_t const * base, uint16x8_t offset) +{ + return vldrbq_gather_offset_s16 (base, offset); +} + +/* { dg-final { scan-assembler "vldrb.s16" } } */ + +int16x8_t +foo1 (int8_t const * base, uint16x8_t offset) +{ + return vldrbq_gather_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrb.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offs= et_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset= _s32.c new file mode 100644 index 0000000000000000000000000000000000000000..768a4325beae64496e174f55932= 554a961cbc886 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int32x4_t +foo (int8_t const * base, uint32x4_t offset) +{ + return vldrbq_gather_offset_s32 (base, offset); +} + +/* { dg-final { scan-assembler "vldrb.s32" } } */ + +int32x4_t +foo1 (int8_t const * base, uint32x4_t offset) +{ + return vldrbq_gather_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrb.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offs= et_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_= s8.c new file mode 100644 index 0000000000000000000000000000000000000000..4c52b5a009507bf68b6bd83699c= d78e85b291572 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8_t const * base, uint8x16_t offset) +{ + return vldrbq_gather_offset_s8 (base, offset); +} + +/* { dg-final { scan-assembler "vldrb.u8" } } */ + +int8x16_t +foo1 (int8_t const * base, uint8x16_t offset) +{ + return vldrbq_gather_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrb.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offs= et_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset= _u16.c new file mode 100644 index 0000000000000000000000000000000000000000..44b310add69aa8e7b74cf2c5010= 13b136d5da041 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint8_t const * base, uint16x8_t offset) +{ + return vldrbq_gather_offset_u16 (base, offset); +} + +/* { dg-final { scan-assembler "vldrb.u16" } } */ + +uint16x8_t +foo1 (uint8_t const * base, uint16x8_t offset) +{ + return vldrbq_gather_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrb.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offs= et_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset= _u32.c new file mode 100644 index 0000000000000000000000000000000000000000..8415ea701327b2a296e1e28e375= 37045b69ff6a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint8_t const * base, uint32x4_t offset) +{ + return vldrbq_gather_offset_u32 (base, offset); +} + +/* { dg-final { scan-assembler "vldrb.u32" } } */ + +uint32x4_t +foo1 (uint8_t const * base, uint32x4_t offset) +{ + return vldrbq_gather_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrb.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offs= et_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_= u8.c new file mode 100644 index 0000000000000000000000000000000000000000..9fbe1aa419d572ffad9b319d3ad= 24d9ac913b7e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8_t const * base, uint8x16_t offset) +{ + return vldrbq_gather_offset_u8 (base, offset); +} + +/* { dg-final { scan-assembler "vldrb.u8" } } */ + +uint8x16_t +foo1 (uint8_t const * base, uint8x16_t offset) +{ + return vldrbq_gather_offset (base, offset); +} + +/* { dg-final { scan-assembler "vldrb.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s16.c b/gcc= /testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s16.c new file mode 100644 index 0000000000000000000000000000000000000000..a63c7367e9ae24b78f4819aea95= e6e5d0ec85891 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s16.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int16x8_t +foo (int8_t const * base) +{ + return vldrbq_s16 (base); +} + +/* { dg-final { scan-assembler "vldrb.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s32.c b/gcc= /testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s32.c new file mode 100644 index 0000000000000000000000000000000000000000..040c58d44c5e6bf09ad61d13c44= f53dfd987e8e4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s32.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int32x4_t +foo (int8_t const * base) +{ + return vldrbq_s32 (base); +} + +/* { dg-final { scan-assembler "vldrb.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s8.c b/gcc/= testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s8.c new file mode 100644 index 0000000000000000000000000000000000000000..e5cc3deb79b909a19cbbcafe921= 3c91b67ac337a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s8.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8_t const * base) +{ + return vldrbq_s8 (base); +} + +/* { dg-final { scan-assembler "vldrb.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u16.c b/gcc= /testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u16.c new file mode 100644 index 0000000000000000000000000000000000000000..7dedbde6eeae066fdc04e9d6fb6= fe626af4580db --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u16.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint8_t const * base) +{ + return vldrbq_u16 (base); +} + +/* { dg-final { scan-assembler "vldrb.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u32.c b/gcc= /testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u32.c new file mode 100644 index 0000000000000000000000000000000000000000..3c3ec6c4ffe6b014bf58d0b7c2a= 2d501ddf8301b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u32.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint8_t const * base) +{ + return vldrbq_u32 (base); +} + +/* { dg-final { scan-assembler "vldrb.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u8.c b/gcc/= testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u8.c new file mode 100644 index 0000000000000000000000000000000000000000..5328d99bab94d62bd032d4da350= 9cd2c55a7841a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u8.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8_t const * base) +{ + return vldrbq_u8 (base); +} + +/* { dg-final { scan-assembler "vldrb.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base= _s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32= .c new file mode 100644 index 0000000000000000000000000000000000000000..14831a91b65900d040f74b90c59= 2bc195af42874 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +int32x4_t +foo (uint32x4_t addr) +{ + return vldrwq_gather_base_s32 (addr, 4); +} + +/* { dg-final { scan-assembler "vldrw.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base= _u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32= .c new file mode 100644 index 0000000000000000000000000000000000000000..7753ea6a7c9ec83b90f3e723683= c156b20617e23 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t addr) +{ + return vldrwq_gather_base_u32 (addr, 4); +} + +/* { dg-final { scan-assembler "vldrw.u32" } } */ --_002_DBBPR08MB47759EE364526D126D90139D9B710DBBPR08MB4775eurp_ Content-Type: text/plain; name="diff21.patch" Content-Description: diff21.patch Content-Disposition: attachment; filename="diff21.patch"; size=24227; creation-date="Thu, 14 Nov 2019 19:13:19 GMT"; modification-date="Thu, 14 Nov 2019 19:13:19 GMT" Content-ID: <109FDF4A789DB24A8CCBE60A5C71445B@eurprd08.prod.outlook.com> Content-Transfer-Encoding: base64 Content-length: 32843 ZGlmZiAtLWdpdCBhL2djYy9jb25maWcvYXJtL2FybS1idWlsdGlucy5jIGIv Z2NjL2NvbmZpZy9hcm0vYXJtLWJ1aWx0aW5zLmMKaW5kZXggZWM4ODE5OWJi NWU3ZTljMTVhMzQ2MDYxYzcwODQxZjMwODYwMDRlZi4uMDJlYTI5NzkzN2Ix ODA5OWYzM2E1MGM4MDg5NjRkMWRkN2VhYzFiMyAxMDA2NDQKLS0tIGEvZ2Nj L2NvbmZpZy9hcm0vYXJtLWJ1aWx0aW5zLmMKKysrIGIvZ2NjL2NvbmZpZy9h cm0vYXJtLWJ1aWx0aW5zLmMKQEAgLTU4OCw2ICs1ODgsMzYgQEAgYXJtX3N0 cnNidV9xdWFsaWZpZXJzW1NJTURfTUFYX0JVSUxUSU5fQVJHU10KICAgICAg IHF1YWxpZmllcl91bnNpZ25lZH07CiAjZGVmaW5lIFNUUlNCVV9RVUFMSUZJ RVJTIChhcm1fc3Ryc2J1X3F1YWxpZmllcnMpCiAKK3N0YXRpYyBlbnVtIGFy bV90eXBlX3F1YWxpZmllcnMKK2FybV9sZHJndV9xdWFsaWZpZXJzW1NJTURf TUFYX0JVSUxUSU5fQVJHU10KKyAgPSB7IHF1YWxpZmllcl91bnNpZ25lZCwg cXVhbGlmaWVyX3BvaW50ZXIsIHF1YWxpZmllcl91bnNpZ25lZH07CisjZGVm aW5lIExEUkdVX1FVQUxJRklFUlMgKGFybV9sZHJndV9xdWFsaWZpZXJzKQor CitzdGF0aWMgZW51bSBhcm1fdHlwZV9xdWFsaWZpZXJzCithcm1fbGRyZ3Nf cXVhbGlmaWVyc1tTSU1EX01BWF9CVUlMVElOX0FSR1NdCisgID0geyBxdWFs aWZpZXJfbm9uZSwgcXVhbGlmaWVyX3BvaW50ZXIsIHF1YWxpZmllcl91bnNp Z25lZH07CisjZGVmaW5lIExEUkdTX1FVQUxJRklFUlMgKGFybV9sZHJnc19x dWFsaWZpZXJzKQorCitzdGF0aWMgZW51bSBhcm1fdHlwZV9xdWFsaWZpZXJz Cithcm1fbGRyc19xdWFsaWZpZXJzW1NJTURfTUFYX0JVSUxUSU5fQVJHU10K KyAgPSB7IHF1YWxpZmllcl9ub25lLCBxdWFsaWZpZXJfcG9pbnRlcn07Cisj ZGVmaW5lIExEUlNfUVVBTElGSUVSUyAoYXJtX2xkcnNfcXVhbGlmaWVycykK Kworc3RhdGljIGVudW0gYXJtX3R5cGVfcXVhbGlmaWVycworYXJtX2xkcnVf cXVhbGlmaWVyc1tTSU1EX01BWF9CVUlMVElOX0FSR1NdCisgID0geyBxdWFs aWZpZXJfdW5zaWduZWQsIHF1YWxpZmllcl9wb2ludGVyfTsKKyNkZWZpbmUg TERSVV9RVUFMSUZJRVJTIChhcm1fbGRydV9xdWFsaWZpZXJzKQorCitzdGF0 aWMgZW51bSBhcm1fdHlwZV9xdWFsaWZpZXJzCithcm1fbGRyZ2JzX3F1YWxp ZmllcnNbU0lNRF9NQVhfQlVJTFRJTl9BUkdTXQorICA9IHsgcXVhbGlmaWVy X25vbmUsIHF1YWxpZmllcl91bnNpZ25lZCwgcXVhbGlmaWVyX2ltbWVkaWF0 ZX07CisjZGVmaW5lIExEUkdCU19RVUFMSUZJRVJTIChhcm1fbGRyZ2JzX3F1 YWxpZmllcnMpCisKK3N0YXRpYyBlbnVtIGFybV90eXBlX3F1YWxpZmllcnMK K2FybV9sZHJnYnVfcXVhbGlmaWVyc1tTSU1EX01BWF9CVUlMVElOX0FSR1Nd CisgID0geyBxdWFsaWZpZXJfdW5zaWduZWQsIHF1YWxpZmllcl91bnNpZ25l ZCwgcXVhbGlmaWVyX2ltbWVkaWF0ZX07CisjZGVmaW5lIExEUkdCVV9RVUFM SUZJRVJTIChhcm1fbGRyZ2J1X3F1YWxpZmllcnMpCisKIC8qIEVuZCBvZiBR dWFsaWZpZXIgZm9yIE1WRSBidWlsdGlucy4gICovCiAKICAgIC8qIHZvaWQg KFtUIGVsZW1lbnQgdHlwZV0gKiwgVCwgaW1tZWRpYXRlKS4gICovCmRpZmYg LS1naXQgYS9nY2MvY29uZmlnL2FybS9hcm1fbXZlLmggYi9nY2MvY29uZmln L2FybS9hcm1fbXZlLmgKaW5kZXggM2Q2NDAzM2RkMjM2MzZiMDQxY2JkNmVj YjNlYjE4YzNiOWRiM2FlZC4uYzEyM2RlMWYzZDM3MDU0Yjc3OWE5ZWU5MDg1 MjVjMjQyYjJiYzRhYiAxMDA2NDQKLS0tIGEvZ2NjL2NvbmZpZy9hcm0vYXJt X212ZS5oCisrKyBiL2djYy9jb25maWcvYXJtL2FybV9tdmUuaApAQCAtMTcx Niw2ICsxNzE2LDIwIEBAIHR5cGVkZWYgc3RydWN0IHsgdWludDh4MTZfdCB2 YWxbNF07IH0gdWludDh4MTZ4NF90OwogI2RlZmluZSB2c3RyYnFfc2NhdHRl cl9vZmZzZXRfczMyKCBfX2Jhc2UsIF9fb2Zmc2V0LCBfX3ZhbHVlKSBfX2Fy bV92c3RyYnFfc2NhdHRlcl9vZmZzZXRfczMyKCBfX2Jhc2UsIF9fb2Zmc2V0 LCBfX3ZhbHVlKQogI2RlZmluZSB2c3Ryd3Ffc2NhdHRlcl9iYXNlX3MzMihf X2FkZHIsICBfX29mZnNldCwgX192YWx1ZSkgX19hcm1fdnN0cndxX3NjYXR0 ZXJfYmFzZV9zMzIoX19hZGRyLCAgX19vZmZzZXQsIF9fdmFsdWUpCiAjZGVm aW5lIHZzdHJ3cV9zY2F0dGVyX2Jhc2VfdTMyKF9fYWRkciwgIF9fb2Zmc2V0 LCBfX3ZhbHVlKSBfX2FybV92c3Ryd3Ffc2NhdHRlcl9iYXNlX3UzMihfX2Fk ZHIsICBfX29mZnNldCwgX192YWx1ZSkKKyNkZWZpbmUgdmxkcmJxX2dhdGhl cl9vZmZzZXRfdTgoX19iYXNlLCBfX29mZnNldCkgX19hcm1fdmxkcmJxX2dh dGhlcl9vZmZzZXRfdTgoX19iYXNlLCBfX29mZnNldCkKKyNkZWZpbmUgdmxk cmJxX2dhdGhlcl9vZmZzZXRfczgoX19iYXNlLCBfX29mZnNldCkgX19hcm1f dmxkcmJxX2dhdGhlcl9vZmZzZXRfczgoX19iYXNlLCBfX29mZnNldCkKKyNk ZWZpbmUgdmxkcmJxX3M4KF9fYmFzZSkgX19hcm1fdmxkcmJxX3M4KF9fYmFz ZSkKKyNkZWZpbmUgdmxkcmJxX3U4KF9fYmFzZSkgX19hcm1fdmxkcmJxX3U4 KF9fYmFzZSkKKyNkZWZpbmUgdmxkcmJxX2dhdGhlcl9vZmZzZXRfdTE2KF9f YmFzZSwgX19vZmZzZXQpIF9fYXJtX3ZsZHJicV9nYXRoZXJfb2Zmc2V0X3Ux NihfX2Jhc2UsIF9fb2Zmc2V0KQorI2RlZmluZSB2bGRyYnFfZ2F0aGVyX29m ZnNldF9zMTYoX19iYXNlLCBfX29mZnNldCkgX19hcm1fdmxkcmJxX2dhdGhl cl9vZmZzZXRfczE2KF9fYmFzZSwgX19vZmZzZXQpCisjZGVmaW5lIHZsZHJi cV9zMTYoX19iYXNlKSBfX2FybV92bGRyYnFfczE2KF9fYmFzZSkKKyNkZWZp bmUgdmxkcmJxX3UxNihfX2Jhc2UpIF9fYXJtX3ZsZHJicV91MTYoX19iYXNl KQorI2RlZmluZSB2bGRyYnFfZ2F0aGVyX29mZnNldF91MzIoX19iYXNlLCBf X29mZnNldCkgX19hcm1fdmxkcmJxX2dhdGhlcl9vZmZzZXRfdTMyKF9fYmFz ZSwgX19vZmZzZXQpCisjZGVmaW5lIHZsZHJicV9nYXRoZXJfb2Zmc2V0X3Mz MihfX2Jhc2UsIF9fb2Zmc2V0KSBfX2FybV92bGRyYnFfZ2F0aGVyX29mZnNl dF9zMzIoX19iYXNlLCBfX29mZnNldCkKKyNkZWZpbmUgdmxkcmJxX3MzMihf X2Jhc2UpIF9fYXJtX3ZsZHJicV9zMzIoX19iYXNlKQorI2RlZmluZSB2bGRy YnFfdTMyKF9fYmFzZSkgX19hcm1fdmxkcmJxX3UzMihfX2Jhc2UpCisjZGVm aW5lIHZsZHJ3cV9nYXRoZXJfYmFzZV9zMzIoX19hZGRyLCAgX19vZmZzZXQp IF9fYXJtX3ZsZHJ3cV9nYXRoZXJfYmFzZV9zMzIoX19hZGRyLCAgX19vZmZz ZXQpCisjZGVmaW5lIHZsZHJ3cV9nYXRoZXJfYmFzZV91MzIoX19hZGRyLCAg X19vZmZzZXQpIF9fYXJtX3ZsZHJ3cV9nYXRoZXJfYmFzZV91MzIoX19hZGRy LCAgX19vZmZzZXQpCiAjZW5kaWYKIAogX19leHRlbnNpb25fXyBleHRlcm4g X19pbmxpbmUgdm9pZApAQCAtMTExMDYsNiArMTExMjAsMTA1IEBAIF9fYXJt X3ZzdHJ3cV9zY2F0dGVyX2Jhc2VfdTMyICh1aW50MzJ4NF90IF9fYWRkciwg Y29uc3QgaW50IF9fb2Zmc2V0LCB1aW50MzJ4NF90CiB7CiAgIF9fYnVpbHRp bl9tdmVfdnN0cndxX3NjYXR0ZXJfYmFzZV91djRzaSAoX19hZGRyLCBfX29m ZnNldCwgX192YWx1ZSk7CiB9CisKK19fZXh0ZW5zaW9uX18gZXh0ZXJuIF9f aW5saW5lIHVpbnQ4eDE2X3QKK19fYXR0cmlidXRlX18gKChfX2Fsd2F5c19p bmxpbmVfXywgX19nbnVfaW5saW5lX18sIF9fYXJ0aWZpY2lhbF9fKSkKK19f YXJtX3ZsZHJicV9nYXRoZXJfb2Zmc2V0X3U4ICh1aW50OF90IGNvbnN0ICog X19iYXNlLCB1aW50OHgxNl90IF9fb2Zmc2V0KQoreworICByZXR1cm4gX19i dWlsdGluX212ZV92bGRyYnFfZ2F0aGVyX29mZnNldF91djE2cWkgKChfX2J1 aWx0aW5fbmVvbl9xaSAqKSBfX2Jhc2UsIF9fb2Zmc2V0KTsKK30KKworX19l eHRlbnNpb25fXyBleHRlcm4gX19pbmxpbmUgaW50OHgxNl90CitfX2F0dHJp YnV0ZV9fICgoX19hbHdheXNfaW5saW5lX18sIF9fZ251X2lubGluZV9fLCBf X2FydGlmaWNpYWxfXykpCitfX2FybV92bGRyYnFfZ2F0aGVyX29mZnNldF9z OCAoaW50OF90IGNvbnN0ICogX19iYXNlLCB1aW50OHgxNl90IF9fb2Zmc2V0 KQoreworICByZXR1cm4gX19idWlsdGluX212ZV92bGRyYnFfZ2F0aGVyX29m ZnNldF9zdjE2cWkgKChfX2J1aWx0aW5fbmVvbl9xaSAqKSBfX2Jhc2UsIF9f b2Zmc2V0KTsKK30KKworX19leHRlbnNpb25fXyBleHRlcm4gX19pbmxpbmUg aW50OHgxNl90CitfX2F0dHJpYnV0ZV9fICgoX19hbHdheXNfaW5saW5lX18s IF9fZ251X2lubGluZV9fLCBfX2FydGlmaWNpYWxfXykpCitfX2FybV92bGRy YnFfczggKGludDhfdCBjb25zdCAqIF9fYmFzZSkKK3sKKyAgcmV0dXJuIF9f YnVpbHRpbl9tdmVfdmxkcmJxX3N2MTZxaSAoKF9fYnVpbHRpbl9uZW9uX3Fp ICopIF9fYmFzZSk7Cit9CisKK19fZXh0ZW5zaW9uX18gZXh0ZXJuIF9faW5s aW5lIHVpbnQ4eDE2X3QKK19fYXR0cmlidXRlX18gKChfX2Fsd2F5c19pbmxp bmVfXywgX19nbnVfaW5saW5lX18sIF9fYXJ0aWZpY2lhbF9fKSkKK19fYXJt X3ZsZHJicV91OCAodWludDhfdCBjb25zdCAqIF9fYmFzZSkKK3sKKyAgcmV0 dXJuIF9fYnVpbHRpbl9tdmVfdmxkcmJxX3V2MTZxaSAoKF9fYnVpbHRpbl9u ZW9uX3FpICopIF9fYmFzZSk7Cit9CisKK19fZXh0ZW5zaW9uX18gZXh0ZXJu IF9faW5saW5lIHVpbnQxNng4X3QKK19fYXR0cmlidXRlX18gKChfX2Fsd2F5 c19pbmxpbmVfXywgX19nbnVfaW5saW5lX18sIF9fYXJ0aWZpY2lhbF9fKSkK K19fYXJtX3ZsZHJicV9nYXRoZXJfb2Zmc2V0X3UxNiAodWludDhfdCBjb25z dCAqIF9fYmFzZSwgdWludDE2eDhfdCBfX29mZnNldCkKK3sKKyAgcmV0dXJu IF9fYnVpbHRpbl9tdmVfdmxkcmJxX2dhdGhlcl9vZmZzZXRfdXY4aGkgKChf X2J1aWx0aW5fbmVvbl9xaSAqKSBfX2Jhc2UsIF9fb2Zmc2V0KTsKK30KKwor X19leHRlbnNpb25fXyBleHRlcm4gX19pbmxpbmUgaW50MTZ4OF90CitfX2F0 dHJpYnV0ZV9fICgoX19hbHdheXNfaW5saW5lX18sIF9fZ251X2lubGluZV9f LCBfX2FydGlmaWNpYWxfXykpCitfX2FybV92bGRyYnFfZ2F0aGVyX29mZnNl dF9zMTYgKGludDhfdCBjb25zdCAqIF9fYmFzZSwgdWludDE2eDhfdCBfX29m ZnNldCkKK3sKKyAgcmV0dXJuIF9fYnVpbHRpbl9tdmVfdmxkcmJxX2dhdGhl cl9vZmZzZXRfc3Y4aGkgKChfX2J1aWx0aW5fbmVvbl9xaSAqKSBfX2Jhc2Us IF9fb2Zmc2V0KTsKK30KKworX19leHRlbnNpb25fXyBleHRlcm4gX19pbmxp bmUgaW50MTZ4OF90CitfX2F0dHJpYnV0ZV9fICgoX19hbHdheXNfaW5saW5l X18sIF9fZ251X2lubGluZV9fLCBfX2FydGlmaWNpYWxfXykpCitfX2FybV92 bGRyYnFfczE2IChpbnQ4X3QgY29uc3QgKiBfX2Jhc2UpCit7CisgIHJldHVy biBfX2J1aWx0aW5fbXZlX3ZsZHJicV9zdjhoaSAoKF9fYnVpbHRpbl9uZW9u X3FpICopIF9fYmFzZSk7Cit9CisKK19fZXh0ZW5zaW9uX18gZXh0ZXJuIF9f aW5saW5lIHVpbnQxNng4X3QKK19fYXR0cmlidXRlX18gKChfX2Fsd2F5c19p bmxpbmVfXywgX19nbnVfaW5saW5lX18sIF9fYXJ0aWZpY2lhbF9fKSkKK19f YXJtX3ZsZHJicV91MTYgKHVpbnQ4X3QgY29uc3QgKiBfX2Jhc2UpCit7Cisg IHJldHVybiBfX2J1aWx0aW5fbXZlX3ZsZHJicV91djhoaSAoKF9fYnVpbHRp bl9uZW9uX3FpICopIF9fYmFzZSk7Cit9CisKK19fZXh0ZW5zaW9uX18gZXh0 ZXJuIF9faW5saW5lIHVpbnQzMng0X3QKK19fYXR0cmlidXRlX18gKChfX2Fs d2F5c19pbmxpbmVfXywgX19nbnVfaW5saW5lX18sIF9fYXJ0aWZpY2lhbF9f KSkKK19fYXJtX3ZsZHJicV9nYXRoZXJfb2Zmc2V0X3UzMiAodWludDhfdCBj b25zdCAqIF9fYmFzZSwgdWludDMyeDRfdCBfX29mZnNldCkKK3sKKyAgcmV0 dXJuIF9fYnVpbHRpbl9tdmVfdmxkcmJxX2dhdGhlcl9vZmZzZXRfdXY0c2kg KChfX2J1aWx0aW5fbmVvbl9xaSAqKSBfX2Jhc2UsIF9fb2Zmc2V0KTsKK30K KworX19leHRlbnNpb25fXyBleHRlcm4gX19pbmxpbmUgaW50MzJ4NF90Citf X2F0dHJpYnV0ZV9fICgoX19hbHdheXNfaW5saW5lX18sIF9fZ251X2lubGlu ZV9fLCBfX2FydGlmaWNpYWxfXykpCitfX2FybV92bGRyYnFfZ2F0aGVyX29m ZnNldF9zMzIgKGludDhfdCBjb25zdCAqIF9fYmFzZSwgdWludDMyeDRfdCBf X29mZnNldCkKK3sKKyAgcmV0dXJuIF9fYnVpbHRpbl9tdmVfdmxkcmJxX2dh dGhlcl9vZmZzZXRfc3Y0c2kgKChfX2J1aWx0aW5fbmVvbl9xaSAqKSBfX2Jh c2UsIF9fb2Zmc2V0KTsKK30KKworX19leHRlbnNpb25fXyBleHRlcm4gX19p bmxpbmUgaW50MzJ4NF90CitfX2F0dHJpYnV0ZV9fICgoX19hbHdheXNfaW5s aW5lX18sIF9fZ251X2lubGluZV9fLCBfX2FydGlmaWNpYWxfXykpCitfX2Fy bV92bGRyYnFfczMyIChpbnQ4X3QgY29uc3QgKiBfX2Jhc2UpCit7CisgIHJl dHVybiBfX2J1aWx0aW5fbXZlX3ZsZHJicV9zdjRzaSAoKF9fYnVpbHRpbl9u ZW9uX3FpICopIF9fYmFzZSk7Cit9CisKK19fZXh0ZW5zaW9uX18gZXh0ZXJu IF9faW5saW5lIHVpbnQzMng0X3QKK19fYXR0cmlidXRlX18gKChfX2Fsd2F5 c19pbmxpbmVfXywgX19nbnVfaW5saW5lX18sIF9fYXJ0aWZpY2lhbF9fKSkK K19fYXJtX3ZsZHJicV91MzIgKHVpbnQ4X3QgY29uc3QgKiBfX2Jhc2UpCit7 CisgIHJldHVybiBfX2J1aWx0aW5fbXZlX3ZsZHJicV91djRzaSAoKF9fYnVp bHRpbl9uZW9uX3FpICopIF9fYmFzZSk7Cit9CisKK19fZXh0ZW5zaW9uX18g ZXh0ZXJuIF9faW5saW5lIGludDMyeDRfdAorX19hdHRyaWJ1dGVfXyAoKF9f YWx3YXlzX2lubGluZV9fLCBfX2dudV9pbmxpbmVfXywgX19hcnRpZmljaWFs X18pKQorX19hcm1fdmxkcndxX2dhdGhlcl9iYXNlX3MzMiAodWludDMyeDRf dCBfX2FkZHIsIGNvbnN0IGludCBfX29mZnNldCkKK3sKKyAgcmV0dXJuIF9f YnVpbHRpbl9tdmVfdmxkcndxX2dhdGhlcl9iYXNlX3N2NHNpIChfX2FkZHIs IF9fb2Zmc2V0KTsKK30KKworX19leHRlbnNpb25fXyBleHRlcm4gX19pbmxp bmUgdWludDMyeDRfdAorX19hdHRyaWJ1dGVfXyAoKF9fYWx3YXlzX2lubGlu ZV9fLCBfX2dudV9pbmxpbmVfXywgX19hcnRpZmljaWFsX18pKQorX19hcm1f dmxkcndxX2dhdGhlcl9iYXNlX3UzMiAodWludDMyeDRfdCBfX2FkZHIsIGNv bnN0IGludCBfX29mZnNldCkKK3sKKyAgcmV0dXJuIF9fYnVpbHRpbl9tdmVf dmxkcndxX2dhdGhlcl9iYXNlX3V2NHNpIChfX2FkZHIsIF9fb2Zmc2V0KTsK K30KKwogI2lmIChfX0FSTV9GRUFUVVJFX01WRSAmIDIpIC8qIE1WRSBGbG9h dGluZyBwb2ludC4gICovCiAKIF9fZXh0ZW5zaW9uX18gZXh0ZXJuIF9faW5s aW5lIHZvaWQKQEAgLTE3NjgyLDYgKzE3Nzk1LDE3IEBAIGV4dGVybiB2b2lk ICpfX0FSTV91bmRlZjsKICAgaW50ICgqKVtfX0FSTV9tdmVfdHlwZV9pbnQz Mng0X3RdOiBfX2FybV92c3Ryd3Ffc2NhdHRlcl9iYXNlX3MzMihwMCwgcDEs IF9fQVJNX212ZV9jb2VyY2UoX19wMiwgaW50MzJ4NF90KSksIFwKICAgaW50 ICgqKVtfX0FSTV9tdmVfdHlwZV91aW50MzJ4NF90XTogX19hcm1fdnN0cndx X3NjYXR0ZXJfYmFzZV91MzIocDAsIHAxLCBfX0FSTV9tdmVfY29lcmNlKF9f cDIsIHVpbnQzMng0X3QpKSk7fSkKIAorI2RlZmluZSB2bGRyYnFfZ2F0aGVy X29mZnNldChwMCxwMSkgX19hcm1fdmxkcmJxX2dhdGhlcl9vZmZzZXQocDAs cDEpCisjZGVmaW5lIF9fYXJtX3ZsZHJicV9nYXRoZXJfb2Zmc2V0KHAwLHAx KSAoeyBfX3R5cGVvZihwMCkgX19wMCA9IChwMCk7IFwKKyAgX190eXBlb2Yo cDEpIF9fcDEgPSAocDEpOyBcCisgIF9HZW5lcmljKCAoaW50ICgqKVtfX0FS TV9tdmVfdHlwZWlkKF9fcDApXVtfX0FSTV9tdmVfdHlwZWlkKF9fcDEpXSkw LCBcCisgIGludCAoKilbX19BUk1fbXZlX3R5cGVfaW50OF90X2NvbnN0X3B0 cl1bX19BUk1fbXZlX3R5cGVfdWludDh4MTZfdF06IF9fYXJtX3ZsZHJicV9n YXRoZXJfb2Zmc2V0X3M4IChfX0FSTV9tdmVfY29lcmNlKF9fcDAsIGludDhf dCBjb25zdCAqKSwgX19BUk1fbXZlX2NvZXJjZShfX3AxLCB1aW50OHgxNl90 KSksIFwKKyAgaW50ICgqKVtfX0FSTV9tdmVfdHlwZV9pbnQ4X3RfY29uc3Rf cHRyXVtfX0FSTV9tdmVfdHlwZV91aW50MTZ4OF90XTogX19hcm1fdmxkcmJx X2dhdGhlcl9vZmZzZXRfczE2IChfX0FSTV9tdmVfY29lcmNlKF9fcDAsIGlu dDhfdCBjb25zdCAqKSwgX19BUk1fbXZlX2NvZXJjZShfX3AxLCB1aW50MTZ4 OF90KSksIFwKKyAgaW50ICgqKVtfX0FSTV9tdmVfdHlwZV9pbnQ4X3RfY29u c3RfcHRyXVtfX0FSTV9tdmVfdHlwZV91aW50MzJ4NF90XTogX19hcm1fdmxk cmJxX2dhdGhlcl9vZmZzZXRfczMyIChfX0FSTV9tdmVfY29lcmNlKF9fcDAs IGludDhfdCBjb25zdCAqKSwgX19BUk1fbXZlX2NvZXJjZShfX3AxLCB1aW50 MzJ4NF90KSksIFwKKyAgaW50ICgqKVtfX0FSTV9tdmVfdHlwZV91aW50OF90 X2NvbnN0X3B0cl1bX19BUk1fbXZlX3R5cGVfdWludDh4MTZfdF06IF9fYXJt X3ZsZHJicV9nYXRoZXJfb2Zmc2V0X3U4IChfX0FSTV9tdmVfY29lcmNlKF9f cDAsIHVpbnQ4X3QgY29uc3QgKiksIF9fQVJNX212ZV9jb2VyY2UoX19wMSwg dWludDh4MTZfdCkpLCBcCisgIGludCAoKilbX19BUk1fbXZlX3R5cGVfdWlu dDhfdF9jb25zdF9wdHJdW19fQVJNX212ZV90eXBlX3VpbnQxNng4X3RdOiBf X2FybV92bGRyYnFfZ2F0aGVyX29mZnNldF91MTYgKF9fQVJNX212ZV9jb2Vy Y2UoX19wMCwgdWludDhfdCBjb25zdCAqKSwgX19BUk1fbXZlX2NvZXJjZShf X3AxLCB1aW50MTZ4OF90KSksIFwKKyAgaW50ICgqKVtfX0FSTV9tdmVfdHlw ZV91aW50OF90X2NvbnN0X3B0cl1bX19BUk1fbXZlX3R5cGVfdWludDMyeDRf dF06IF9fYXJtX3ZsZHJicV9nYXRoZXJfb2Zmc2V0X3UzMiAoX19BUk1fbXZl X2NvZXJjZShfX3AwLCB1aW50OF90IGNvbnN0ICopLCBfX0FSTV9tdmVfY29l cmNlKF9fcDEsIHVpbnQzMng0X3QpKSk7fSkKKwogI2VuZGlmIC8qIE1WRSBG bG9hdGluZyBwb2ludC4gICovCiAKICNpZmRlZiBfX2NwbHVzcGx1cwpkaWZm IC0tZ2l0IGEvZ2NjL2NvbmZpZy9hcm0vYXJtX212ZV9idWlsdGlucy5kZWYg Yi9nY2MvY29uZmlnL2FybS9hcm1fbXZlX2J1aWx0aW5zLmRlZgppbmRleCAx NDljNDExNWI2MTY3ZTNmMmYwZWI0M2ZiZGVhYTg3MDhiYTVkNzIzLi42MGU1 MDc2N2EyYWM4MGEwNTMwM2UzZGY4NTEyZjI2MTJjOGJjOGVmIDEwMDY0NAot LS0gYS9nY2MvY29uZmlnL2FybS9hcm1fbXZlX2J1aWx0aW5zLmRlZgorKysg Yi9nY2MvY29uZmlnL2FybS9hcm1fbXZlX2J1aWx0aW5zLmRlZgpAQCAtNjkx LDMgKzY5MSw5IEBAIFZBUjMgKFNUUlNTLCB2c3RyYnFfc2NhdHRlcl9vZmZz ZXRfcywgdjE2cWksIHY4aGksIHY0c2kpCiBWQVIzIChTVFJTVSwgdnN0cmJx X3NjYXR0ZXJfb2Zmc2V0X3UsIHYxNnFpLCB2OGhpLCB2NHNpKQogVkFSMSAo U1RSU0JTLCB2c3Ryd3Ffc2NhdHRlcl9iYXNlX3MsIHY0c2kpCiBWQVIxIChT VFJTQlUsIHZzdHJ3cV9zY2F0dGVyX2Jhc2VfdSwgdjRzaSkKK1ZBUjMgKExE UkdVLCB2bGRyYnFfZ2F0aGVyX29mZnNldF91LCB2MTZxaSwgdjhoaSwgdjRz aSkKK1ZBUjMgKExEUkdTLCB2bGRyYnFfZ2F0aGVyX29mZnNldF9zLCB2MTZx aSwgdjhoaSwgdjRzaSkKK1ZBUjMgKExEUlMsIHZsZHJicV9zLCB2MTZxaSwg djhoaSwgdjRzaSkKK1ZBUjMgKExEUlUsIHZsZHJicV91LCB2MTZxaSwgdjho aSwgdjRzaSkKK1ZBUjEgKExEUkdCUywgdmxkcndxX2dhdGhlcl9iYXNlX3Ms IHY0c2kpCitWQVIxIChMRFJHQlUsIHZsZHJ3cV9nYXRoZXJfYmFzZV91LCB2 NHNpKQpkaWZmIC0tZ2l0IGEvZ2NjL2NvbmZpZy9hcm0vbXZlLm1kIGIvZ2Nj L2NvbmZpZy9hcm0vbXZlLm1kCmluZGV4IGViMzY1MTY2ZTkzNGYzMmY3Njk1 ZTUzNTQyNTgxNTEyMDJmMzc4YzAuLjdiNDE2ZjlhNGUwNGY4YzAyNTQ3OTUz ZDYwMTk3ODc4MTc2ODhhMzYgMTAwNjQ0Ci0tLSBhL2djYy9jb25maWcvYXJt L212ZS5tZAorKysgYi9nY2MvY29uZmlnL2FybS9tdmUubWQKQEAgLTE5Miw3 ICsxOTIsOCBAQAogCQkJIFZDTVVMUV9ST1QyNzBfTV9GIFZDTVVMUV9ST1Q5 MF9NX0YgVkZNQVFfTV9GCiAJCQkgVkZNQVFfTV9OX0YgVkZNQVNRX01fTl9G IFZGTVNRX01fRiBWTUFYTk1RX01fRgogCQkJIFZNSU5OTVFfTV9GIFZTVUJR X01fRiBWU1RSV1FTQl9TIFZTVFJXUVNCX1UKLQkJCSBWU1RSQlFTT19TIFZT VFJCUVNPX1UgVlNUUkJRX1MgVlNUUkJRX1VdKQorCQkJIFZTVFJCUVNPX1Mg VlNUUkJRU09fVSBWU1RSQlFfUyBWU1RSQlFfVSBWTERSQlFHT19TCisJCQkg VkxEUkJRR09fVSBWTERSQlFfUyBWTERSQlFfVSBWTERSV1FHQl9TIFZMRFJX UUdCX1VdKQogCiAoZGVmaW5lX21vZGVfYXR0ciBNVkVfQ05WVCBbKFY4SEkg IlY4SEYiKSAoVjRTSSAiVjRTRiIpCiAJCQkgICAgKFY4SEYgIlY4SEkiKSAo VjRTRiAiVjRTSSIpXSkKQEAgLTM0NSw3ICszNDYsOSBAQAogCQkgICAgICAg KFZNTEFMREFWQVhRX1BfUyAicyIpIChWTUxBTERBVkFYUV9QX1UgInUiKQog CQkgICAgICAgKFZNTEFMREFWQVFfUF9TICJzIikgKFZNTEFMREFWQVFfUF9V ICJ1IikKIAkJICAgICAgIChWU1RSV1FTQl9TICJzIikgKFZTVFJXUVNCX1Ug InUiKSAoVlNUUkJRU09fUyAicyIpCi0JCSAgICAgICAoVlNUUkJRU09fVSAi dSIpIChWU1RSQlFfUyAicyIpIChWU1RSQlFfVSAidSIpXSkKKwkJICAgICAg IChWU1RSQlFTT19VICJ1IikgKFZTVFJCUV9TICJzIikgKFZTVFJCUV9VICJ1 IikKKwkJICAgICAgIChWTERSQlFHT19TICJzIikgKFZMRFJCUUdPX1UgInUi KSAoVkxEUkJRX1MgInMiKQorCQkgICAgICAgKFZMRFJCUV9VICJ1IikgKFZM RFJXUUdCX1MgInMiKSAoVkxEUldRR0JfVSAidSIpXSkKIAogKGRlZmluZV9p bnRfYXR0ciBtb2RlMSBbKFZDVFA4USAiOCIpIChWQ1RQMTZRICIxNiIpIChW Q1RQMzJRICIzMiIpCiAJCQkoVkNUUDY0USAiNjQiKSAoVkNUUDhRX00gIjgi KSAoVkNUUDE2UV9NICIxNiIpCkBAIC01NjksNiArNTcyLDkgQEAKIChkZWZp bmVfaW50X2l0ZXJhdG9yIFZTVFJXU0JRIFtWU1RSV1FTQl9TIFZTVFJXUVNC X1VdKQogKGRlZmluZV9pbnRfaXRlcmF0b3IgVlNUUkJTT1EgW1ZTVFJCUVNP X1MgVlNUUkJRU09fVV0pCiAoZGVmaW5lX2ludF9pdGVyYXRvciBWU1RSQlEg W1ZTVFJCUV9TIFZTVFJCUV9VXSkKKyhkZWZpbmVfaW50X2l0ZXJhdG9yIFZM RFJCR09RIFtWTERSQlFHT19TIFZMRFJCUUdPX1VdKQorKGRlZmluZV9pbnRf aXRlcmF0b3IgVkxEUkJRIFtWTERSQlFfUyBWTERSQlFfVV0pCisoZGVmaW5l X2ludF9pdGVyYXRvciBWTERSV0dCUSBbVkxEUldRR0JfUyBWTERSV1FHQl9V XSkKIAogKGRlZmluZV9pbnNuICIqbXZlX21vdjxtb2RlPiIKICAgWyhzZXQg KG1hdGNoX29wZXJhbmQ6TVZFX3R5cGVzIDAgInNfcmVnaXN0ZXJfb3BlcmFu ZCIgIj13LHcscix3LHcscix3IikKQEAgLTgwMDIsMyArODAwOCw2NSBAQAog ICAgcmV0dXJuICIiOwogfQogICBbKHNldF9hdHRyICJsZW5ndGgiICI0Iild KQorCis7OworOzsgW3ZsZHJicV9nYXRoZXJfb2Zmc2V0X3MgdmxkcmJxX2dh dGhlcl9vZmZzZXRfdV0KKzs7CisoZGVmaW5lX2luc24gIm12ZV92bGRyYnFf Z2F0aGVyX29mZnNldF88c3VwZj48bW9kZT4iCisgIFsoc2V0IChtYXRjaF9v cGVyYW5kOk1WRV8yIDAgInNfcmVnaXN0ZXJfb3BlcmFuZCIgIj0mdyIpCisJ KHVuc3BlYzpNVkVfMiBbKG1hdGNoX29wZXJhbmQ6PE1WRV9CX0VMRU0+IDEg Im1lbW9yeV9vcGVyYW5kIiAiVXMiKQorCQkgICAgICAgKG1hdGNoX29wZXJh bmQ6TVZFXzIgMiAic19yZWdpc3Rlcl9vcGVyYW5kIiAidyIpXQorCSBWTERS QkdPUSkpCisgIF0KKyAgIlRBUkdFVF9IQVZFX01WRSIKK3sKKyAgIHJ0eCBv cHNbM107CisgICBvcHNbMF0gPSBvcGVyYW5kc1swXTsKKyAgIG9wc1sxXSA9 IG9wZXJhbmRzWzFdOworICAgb3BzWzJdID0gb3BlcmFuZHNbMl07CisgICBp ZiAoIXN0cmNtcCAoIjxzdXBmPiIsInMiKSAmJiA8Vl9zel9lbGVtPiA9PSA4 KQorICAgICBvdXRwdXRfYXNtX2luc24gKCJ2bGRyYi51OFx0JXEwLCBbJW0x LCAlcTJdIixvcHMpOworICAgZWxzZQorICAgICBvdXRwdXRfYXNtX2luc24g KCJ2bGRyYi48c3VwZj48Vl9zel9lbGVtPlx0JXEwLCBbJW0xLCAlcTJdIixv cHMpOworICAgcmV0dXJuICIiOworfQorICBbKHNldF9hdHRyICJsZW5ndGgi ICI0IildKQorCis7OworOzsgW3ZsZHJicV9zIHZsZHJicV91XQorOzsKKyhk ZWZpbmVfaW5zbiAibXZlX3ZsZHJicV88c3VwZj48bW9kZT4iCisgIFsoc2V0 IChtYXRjaF9vcGVyYW5kOk1WRV8yIDAgInNfcmVnaXN0ZXJfb3BlcmFuZCIg Ij13IikKKwkodW5zcGVjOk1WRV8yIFsobWF0Y2hfb3BlcmFuZDo8TVZFX0Jf RUxFTT4gMSAibWVtb3J5X29wZXJhbmQiICJVcyIpXQorCSBWTERSQlEpKQor ICBdCisgICJUQVJHRVRfSEFWRV9NVkUiCit7CisgICBydHggb3BzWzJdOwor ICAgaW50IHJlZ25vID0gUkVHTk8gKG9wZXJhbmRzWzBdKTsKKyAgIG9wc1sw XSA9IGdlbl9ydHhfUkVHIChUSW1vZGUsIHJlZ25vKTsKKyAgIG9wc1sxXSAg PSBvcGVyYW5kc1sxXTsKKyAgIG91dHB1dF9hc21faW5zbiAoInZsZHJiLjxz dXBmPjxWX3N6X2VsZW0+XHQlcTAsICVFMSIsb3BzKTsKKyAgIHJldHVybiAi IjsKK30KKyAgWyhzZXRfYXR0ciAibGVuZ3RoIiAiNCIpXSkKKworOzsKKzs7 IFt2bGRyd3FfZ2F0aGVyX2Jhc2VfcyB2bGRyd3FfZ2F0aGVyX2Jhc2VfdV0K Kzs7CisoZGVmaW5lX2luc24gIm12ZV92bGRyd3FfZ2F0aGVyX2Jhc2VfPHN1 cGY+djRzaSIKKyAgWyhzZXQgKG1hdGNoX29wZXJhbmQ6VjRTSSAwICJzX3Jl Z2lzdGVyX29wZXJhbmQiICI9JnciKQorCSh1bnNwZWM6VjRTSSBbKG1hdGNo X29wZXJhbmQ6VjRTSSAxICJzX3JlZ2lzdGVyX29wZXJhbmQiICJ3IikKKwkJ ICAgICAgKG1hdGNoX29wZXJhbmQ6U0kgMiAiaW1tZWRpYXRlX29wZXJhbmQi ICJpIildCisJIFZMRFJXR0JRKSkKKyAgXQorICAiVEFSR0VUX0hBVkVfTVZF IgoreworICAgcnR4IG9wc1szXTsKKyAgIG9wc1swXSA9IG9wZXJhbmRzWzBd OworICAgb3BzWzFdID0gb3BlcmFuZHNbMV07CisgICBvcHNbMl0gPSBvcGVy YW5kc1syXTsKKyAgIG91dHB1dF9hc21faW5zbiAoInZsZHJ3LnUzMlx0JXEw LCBbJXExLCAlMl0iLG9wcyk7CisgICByZXR1cm4gIiI7Cit9CisgIFsoc2V0 X2F0dHIgImxlbmd0aCIgIjQiKV0pCmRpZmYgLS1naXQgYS9nY2MvdGVzdHN1 aXRlL2djYy50YXJnZXQvYXJtL212ZS9pbnRyaW5zaWNzL3ZsZHJicV9nYXRo ZXJfb2Zmc2V0X3MxNi5jIGIvZ2NjL3Rlc3RzdWl0ZS9nY2MudGFyZ2V0L2Fy bS9tdmUvaW50cmluc2ljcy92bGRyYnFfZ2F0aGVyX29mZnNldF9zMTYuYwpu ZXcgZmlsZSBtb2RlIDEwMDY0NAppbmRleCAwMDAwMDAwMDAwMDAwMDAwMDAw MDAwMDAwMDAwMDAwMDAwMDAwMDAwLi5mNzc2M2I4YTFmNjY4ZTI1YzViMzRl ZDQyOWRkNWRjOWE1NDU1Njc2Ci0tLSAvZGV2L251bGwKKysrIGIvZ2NjL3Rl c3RzdWl0ZS9nY2MudGFyZ2V0L2FybS9tdmUvaW50cmluc2ljcy92bGRyYnFf Z2F0aGVyX29mZnNldF9zMTYuYwpAQCAtMCwwICsxLDIxIEBACisvKiB7IGRn LWRvIGNvbXBpbGUgIH0gKi8KKy8qIHsgZGctYWRkaXRpb25hbC1vcHRpb25z ICItbWFyY2g9YXJtdjguMS1tLm1haW4rbXZlIC1tZmxvYXQtYWJpPWhhcmQg LU8yIiAgfSAgKi8KKy8qIHsgZGctc2tpcC1pZiAiU2tpcCBpZiBub3QgYXV0 byIgeyotKi0qfSB7Ii1tZnB1PSoifSB7Ii1tZnB1PWF1dG8ifSB9ICovCisK KyNpbmNsdWRlICJhcm1fbXZlLmgiCisKK2ludDE2eDhfdAorZm9vIChpbnQ4 X3QgY29uc3QgKiBiYXNlLCB1aW50MTZ4OF90IG9mZnNldCkKK3sKKyAgcmV0 dXJuIHZsZHJicV9nYXRoZXJfb2Zmc2V0X3MxNiAoYmFzZSwgb2Zmc2V0KTsK K30KKworLyogeyBkZy1maW5hbCB7IHNjYW4tYXNzZW1ibGVyICJ2bGRyYi5z MTYiICB9ICB9ICovCisKK2ludDE2eDhfdAorZm9vMSAoaW50OF90IGNvbnN0 ICogYmFzZSwgdWludDE2eDhfdCBvZmZzZXQpCit7CisgIHJldHVybiB2bGRy YnFfZ2F0aGVyX29mZnNldCAoYmFzZSwgb2Zmc2V0KTsKK30KKworLyogeyBk Zy1maW5hbCB7IHNjYW4tYXNzZW1ibGVyICJ2bGRyYi5zMTYiICB9ICB9ICov CmRpZmYgLS1naXQgYS9nY2MvdGVzdHN1aXRlL2djYy50YXJnZXQvYXJtL212 ZS9pbnRyaW5zaWNzL3ZsZHJicV9nYXRoZXJfb2Zmc2V0X3MzMi5jIGIvZ2Nj L3Rlc3RzdWl0ZS9nY2MudGFyZ2V0L2FybS9tdmUvaW50cmluc2ljcy92bGRy YnFfZ2F0aGVyX29mZnNldF9zMzIuYwpuZXcgZmlsZSBtb2RlIDEwMDY0NApp bmRleCAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAw Li43NjhhNDMyNWJlYWU2NDQ5NmUxNzRmNTU5MzI1NTRhOTYxY2JjODg2Ci0t LSAvZGV2L251bGwKKysrIGIvZ2NjL3Rlc3RzdWl0ZS9nY2MudGFyZ2V0L2Fy bS9tdmUvaW50cmluc2ljcy92bGRyYnFfZ2F0aGVyX29mZnNldF9zMzIuYwpA QCAtMCwwICsxLDIxIEBACisvKiB7IGRnLWRvIGNvbXBpbGUgIH0gKi8KKy8q IHsgZGctYWRkaXRpb25hbC1vcHRpb25zICItbWFyY2g9YXJtdjguMS1tLm1h aW4rbXZlIC1tZmxvYXQtYWJpPWhhcmQgLU8yIiAgfSAgKi8KKy8qIHsgZGct c2tpcC1pZiAiU2tpcCBpZiBub3QgYXV0byIgeyotKi0qfSB7Ii1tZnB1PSoi fSB7Ii1tZnB1PWF1dG8ifSB9ICovCisKKyNpbmNsdWRlICJhcm1fbXZlLmgi CisKK2ludDMyeDRfdAorZm9vIChpbnQ4X3QgY29uc3QgKiBiYXNlLCB1aW50 MzJ4NF90IG9mZnNldCkKK3sKKyAgcmV0dXJuIHZsZHJicV9nYXRoZXJfb2Zm c2V0X3MzMiAoYmFzZSwgb2Zmc2V0KTsKK30KKworLyogeyBkZy1maW5hbCB7 IHNjYW4tYXNzZW1ibGVyICJ2bGRyYi5zMzIiICB9ICB9ICovCisKK2ludDMy eDRfdAorZm9vMSAoaW50OF90IGNvbnN0ICogYmFzZSwgdWludDMyeDRfdCBv ZmZzZXQpCit7CisgIHJldHVybiB2bGRyYnFfZ2F0aGVyX29mZnNldCAoYmFz ZSwgb2Zmc2V0KTsKK30KKworLyogeyBkZy1maW5hbCB7IHNjYW4tYXNzZW1i bGVyICJ2bGRyYi5zMzIiICB9ICB9ICovCmRpZmYgLS1naXQgYS9nY2MvdGVz dHN1aXRlL2djYy50YXJnZXQvYXJtL212ZS9pbnRyaW5zaWNzL3ZsZHJicV9n YXRoZXJfb2Zmc2V0X3M4LmMgYi9nY2MvdGVzdHN1aXRlL2djYy50YXJnZXQv YXJtL212ZS9pbnRyaW5zaWNzL3ZsZHJicV9nYXRoZXJfb2Zmc2V0X3M4LmMK bmV3IGZpbGUgbW9kZSAxMDA2NDQKaW5kZXggMDAwMDAwMDAwMDAwMDAwMDAw MDAwMDAwMDAwMDAwMDAwMDAwMDAwMC4uNGM1MmI1YTAwOTUwN2JmNjhiNmJk ODM2OTljZDc4ZTg1YjI5MTU3MgotLS0gL2Rldi9udWxsCisrKyBiL2djYy90 ZXN0c3VpdGUvZ2NjLnRhcmdldC9hcm0vbXZlL2ludHJpbnNpY3MvdmxkcmJx X2dhdGhlcl9vZmZzZXRfczguYwpAQCAtMCwwICsxLDIxIEBACisvKiB7IGRn LWRvIGNvbXBpbGUgIH0gKi8KKy8qIHsgZGctYWRkaXRpb25hbC1vcHRpb25z ICItbWFyY2g9YXJtdjguMS1tLm1haW4rbXZlIC1tZmxvYXQtYWJpPWhhcmQg LU8yIiAgfSAgKi8KKy8qIHsgZGctc2tpcC1pZiAiU2tpcCBpZiBub3QgYXV0 byIgeyotKi0qfSB7Ii1tZnB1PSoifSB7Ii1tZnB1PWF1dG8ifSB9ICovCisK KyNpbmNsdWRlICJhcm1fbXZlLmgiCisKK2ludDh4MTZfdAorZm9vIChpbnQ4 X3QgY29uc3QgKiBiYXNlLCB1aW50OHgxNl90IG9mZnNldCkKK3sKKyAgcmV0 dXJuIHZsZHJicV9nYXRoZXJfb2Zmc2V0X3M4IChiYXNlLCBvZmZzZXQpOwor fQorCisvKiB7IGRnLWZpbmFsIHsgc2Nhbi1hc3NlbWJsZXIgInZsZHJiLnU4 IiAgfSAgfSAqLworCitpbnQ4eDE2X3QKK2ZvbzEgKGludDhfdCBjb25zdCAq IGJhc2UsIHVpbnQ4eDE2X3Qgb2Zmc2V0KQoreworICByZXR1cm4gdmxkcmJx X2dhdGhlcl9vZmZzZXQgKGJhc2UsIG9mZnNldCk7Cit9CisKKy8qIHsgZGct ZmluYWwgeyBzY2FuLWFzc2VtYmxlciAidmxkcmIudTgiICB9ICB9ICovCmRp ZmYgLS1naXQgYS9nY2MvdGVzdHN1aXRlL2djYy50YXJnZXQvYXJtL212ZS9p bnRyaW5zaWNzL3ZsZHJicV9nYXRoZXJfb2Zmc2V0X3UxNi5jIGIvZ2NjL3Rl c3RzdWl0ZS9nY2MudGFyZ2V0L2FybS9tdmUvaW50cmluc2ljcy92bGRyYnFf Z2F0aGVyX29mZnNldF91MTYuYwpuZXcgZmlsZSBtb2RlIDEwMDY0NAppbmRl eCAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwLi40 NGIzMTBhZGQ2OWFhOGU3Yjc0Y2YyYzUwMTAxM2IxMzZkNWRhMDQxCi0tLSAv ZGV2L251bGwKKysrIGIvZ2NjL3Rlc3RzdWl0ZS9nY2MudGFyZ2V0L2FybS9t dmUvaW50cmluc2ljcy92bGRyYnFfZ2F0aGVyX29mZnNldF91MTYuYwpAQCAt MCwwICsxLDIxIEBACisvKiB7IGRnLWRvIGNvbXBpbGUgIH0gKi8KKy8qIHsg ZGctYWRkaXRpb25hbC1vcHRpb25zICItbWFyY2g9YXJtdjguMS1tLm1haW4r bXZlIC1tZmxvYXQtYWJpPWhhcmQgLU8yIiAgfSAgKi8KKy8qIHsgZGctc2tp cC1pZiAiU2tpcCBpZiBub3QgYXV0byIgeyotKi0qfSB7Ii1tZnB1PSoifSB7 Ii1tZnB1PWF1dG8ifSB9ICovCisKKyNpbmNsdWRlICJhcm1fbXZlLmgiCisK K3VpbnQxNng4X3QKK2ZvbyAodWludDhfdCBjb25zdCAqIGJhc2UsIHVpbnQx Nng4X3Qgb2Zmc2V0KQoreworICByZXR1cm4gdmxkcmJxX2dhdGhlcl9vZmZz ZXRfdTE2IChiYXNlLCBvZmZzZXQpOworfQorCisvKiB7IGRnLWZpbmFsIHsg c2Nhbi1hc3NlbWJsZXIgInZsZHJiLnUxNiIgIH0gIH0gKi8KKwordWludDE2 eDhfdAorZm9vMSAodWludDhfdCBjb25zdCAqIGJhc2UsIHVpbnQxNng4X3Qg b2Zmc2V0KQoreworICByZXR1cm4gdmxkcmJxX2dhdGhlcl9vZmZzZXQgKGJh c2UsIG9mZnNldCk7Cit9CisKKy8qIHsgZGctZmluYWwgeyBzY2FuLWFzc2Vt YmxlciAidmxkcmIudTE2IiAgfSAgfSAqLwpkaWZmIC0tZ2l0IGEvZ2NjL3Rl c3RzdWl0ZS9nY2MudGFyZ2V0L2FybS9tdmUvaW50cmluc2ljcy92bGRyYnFf Z2F0aGVyX29mZnNldF91MzIuYyBiL2djYy90ZXN0c3VpdGUvZ2NjLnRhcmdl dC9hcm0vbXZlL2ludHJpbnNpY3MvdmxkcmJxX2dhdGhlcl9vZmZzZXRfdTMy LmMKbmV3IGZpbGUgbW9kZSAxMDA2NDQKaW5kZXggMDAwMDAwMDAwMDAwMDAw MDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMC4uODQxNWVhNzAxMzI3YjJhMjk2 ZTFlMjhlMzc1MzcwNDViNjlmZjZhOQotLS0gL2Rldi9udWxsCisrKyBiL2dj Yy90ZXN0c3VpdGUvZ2NjLnRhcmdldC9hcm0vbXZlL2ludHJpbnNpY3Mvdmxk cmJxX2dhdGhlcl9vZmZzZXRfdTMyLmMKQEAgLTAsMCArMSwyMSBAQAorLyog eyBkZy1kbyBjb21waWxlICB9ICovCisvKiB7IGRnLWFkZGl0aW9uYWwtb3B0 aW9ucyAiLW1hcmNoPWFybXY4LjEtbS5tYWluK212ZSAtbWZsb2F0LWFiaT1o YXJkIC1PMiIgIH0gICovCisvKiB7IGRnLXNraXAtaWYgIlNraXAgaWYgbm90 IGF1dG8iIHsqLSotKn0geyItbWZwdT0qIn0geyItbWZwdT1hdXRvIn0gfSAq LworCisjaW5jbHVkZSAiYXJtX212ZS5oIgorCit1aW50MzJ4NF90Citmb28g KHVpbnQ4X3QgY29uc3QgKiBiYXNlLCB1aW50MzJ4NF90IG9mZnNldCkKK3sK KyAgcmV0dXJuIHZsZHJicV9nYXRoZXJfb2Zmc2V0X3UzMiAoYmFzZSwgb2Zm c2V0KTsKK30KKworLyogeyBkZy1maW5hbCB7IHNjYW4tYXNzZW1ibGVyICJ2 bGRyYi51MzIiICB9ICB9ICovCisKK3VpbnQzMng0X3QKK2ZvbzEgKHVpbnQ4 X3QgY29uc3QgKiBiYXNlLCB1aW50MzJ4NF90IG9mZnNldCkKK3sKKyAgcmV0 dXJuIHZsZHJicV9nYXRoZXJfb2Zmc2V0IChiYXNlLCBvZmZzZXQpOworfQor CisvKiB7IGRnLWZpbmFsIHsgc2Nhbi1hc3NlbWJsZXIgInZsZHJiLnUzMiIg IH0gIH0gKi8KZGlmZiAtLWdpdCBhL2djYy90ZXN0c3VpdGUvZ2NjLnRhcmdl dC9hcm0vbXZlL2ludHJpbnNpY3MvdmxkcmJxX2dhdGhlcl9vZmZzZXRfdTgu YyBiL2djYy90ZXN0c3VpdGUvZ2NjLnRhcmdldC9hcm0vbXZlL2ludHJpbnNp Y3MvdmxkcmJxX2dhdGhlcl9vZmZzZXRfdTguYwpuZXcgZmlsZSBtb2RlIDEw MDY0NAppbmRleCAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAw MDAwMDAwLi45ZmJlMWFhNDE5ZDU3MmZmYWQ5YjMxOWQzYWQyNGQ5YWM5MTNi N2U2Ci0tLSAvZGV2L251bGwKKysrIGIvZ2NjL3Rlc3RzdWl0ZS9nY2MudGFy Z2V0L2FybS9tdmUvaW50cmluc2ljcy92bGRyYnFfZ2F0aGVyX29mZnNldF91 OC5jCkBAIC0wLDAgKzEsMjEgQEAKKy8qIHsgZGctZG8gY29tcGlsZSAgfSAq LworLyogeyBkZy1hZGRpdGlvbmFsLW9wdGlvbnMgIi1tYXJjaD1hcm12OC4x LW0ubWFpbittdmUgLW1mbG9hdC1hYmk9aGFyZCAtTzIiICB9ICAqLworLyog eyBkZy1za2lwLWlmICJTa2lwIGlmIG5vdCBhdXRvIiB7Ki0qLSp9IHsiLW1m cHU9KiJ9IHsiLW1mcHU9YXV0byJ9IH0gKi8KKworI2luY2x1ZGUgImFybV9t dmUuaCIKKwordWludDh4MTZfdAorZm9vICh1aW50OF90IGNvbnN0ICogYmFz ZSwgdWludDh4MTZfdCBvZmZzZXQpCit7CisgIHJldHVybiB2bGRyYnFfZ2F0 aGVyX29mZnNldF91OCAoYmFzZSwgb2Zmc2V0KTsKK30KKworLyogeyBkZy1m aW5hbCB7IHNjYW4tYXNzZW1ibGVyICJ2bGRyYi51OCIgIH0gIH0gKi8KKwor dWludDh4MTZfdAorZm9vMSAodWludDhfdCBjb25zdCAqIGJhc2UsIHVpbnQ4 eDE2X3Qgb2Zmc2V0KQoreworICByZXR1cm4gdmxkcmJxX2dhdGhlcl9vZmZz ZXQgKGJhc2UsIG9mZnNldCk7Cit9CisKKy8qIHsgZGctZmluYWwgeyBzY2Fu LWFzc2VtYmxlciAidmxkcmIudTgiICB9ICB9ICovCmRpZmYgLS1naXQgYS9n Y2MvdGVzdHN1aXRlL2djYy50YXJnZXQvYXJtL212ZS9pbnRyaW5zaWNzL3Zs ZHJicV9zMTYuYyBiL2djYy90ZXN0c3VpdGUvZ2NjLnRhcmdldC9hcm0vbXZl L2ludHJpbnNpY3MvdmxkcmJxX3MxNi5jCm5ldyBmaWxlIG1vZGUgMTAwNjQ0 CmluZGV4IDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAw MDAuLmE2M2M3MzY3ZTlhZTI0Yjc4ZjQ4MTlhZWE5NWU2ZTVkMGVjODU4OTEK LS0tIC9kZXYvbnVsbAorKysgYi9nY2MvdGVzdHN1aXRlL2djYy50YXJnZXQv YXJtL212ZS9pbnRyaW5zaWNzL3ZsZHJicV9zMTYuYwpAQCAtMCwwICsxLDEz IEBACisvKiB7IGRnLWRvIGNvbXBpbGUgIH0gKi8KKy8qIHsgZGctYWRkaXRp b25hbC1vcHRpb25zICItbWFyY2g9YXJtdjguMS1tLm1haW4rbXZlIC1tZmxv YXQtYWJpPWhhcmQgLU8yIiAgfSAgKi8KKy8qIHsgZGctc2tpcC1pZiAiU2tp cCBpZiBub3QgYXV0byIgeyotKi0qfSB7Ii1tZnB1PSoifSB7Ii1tZnB1PWF1 dG8ifSB9ICovCisKKyNpbmNsdWRlICJhcm1fbXZlLmgiCisKK2ludDE2eDhf dAorZm9vIChpbnQ4X3QgY29uc3QgKiBiYXNlKQoreworICByZXR1cm4gdmxk cmJxX3MxNiAoYmFzZSk7Cit9CisKKy8qIHsgZGctZmluYWwgeyBzY2FuLWFz c2VtYmxlciAidmxkcmIuczE2IiAgfSAgfSAqLwpkaWZmIC0tZ2l0IGEvZ2Nj L3Rlc3RzdWl0ZS9nY2MudGFyZ2V0L2FybS9tdmUvaW50cmluc2ljcy92bGRy YnFfczMyLmMgYi9nY2MvdGVzdHN1aXRlL2djYy50YXJnZXQvYXJtL212ZS9p bnRyaW5zaWNzL3ZsZHJicV9zMzIuYwpuZXcgZmlsZSBtb2RlIDEwMDY0NApp bmRleCAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAw Li4wNDBjNThkNDRjNWU2YmYwOWFkNjFkMTNjNDRmNTNkZmQ5ODdlOGU0Ci0t LSAvZGV2L251bGwKKysrIGIvZ2NjL3Rlc3RzdWl0ZS9nY2MudGFyZ2V0L2Fy bS9tdmUvaW50cmluc2ljcy92bGRyYnFfczMyLmMKQEAgLTAsMCArMSwxMyBA QAorLyogeyBkZy1kbyBjb21waWxlICB9ICovCisvKiB7IGRnLWFkZGl0aW9u YWwtb3B0aW9ucyAiLW1hcmNoPWFybXY4LjEtbS5tYWluK212ZSAtbWZsb2F0 LWFiaT1oYXJkIC1PMiIgIH0gICovCisvKiB7IGRnLXNraXAtaWYgIlNraXAg aWYgbm90IGF1dG8iIHsqLSotKn0geyItbWZwdT0qIn0geyItbWZwdT1hdXRv In0gfSAqLworCisjaW5jbHVkZSAiYXJtX212ZS5oIgorCitpbnQzMng0X3QK K2ZvbyAoaW50OF90IGNvbnN0ICogYmFzZSkKK3sKKyAgcmV0dXJuIHZsZHJi cV9zMzIgKGJhc2UpOworfQorCisvKiB7IGRnLWZpbmFsIHsgc2Nhbi1hc3Nl bWJsZXIgInZsZHJiLnMzMiIgIH0gIH0gKi8KZGlmZiAtLWdpdCBhL2djYy90 ZXN0c3VpdGUvZ2NjLnRhcmdldC9hcm0vbXZlL2ludHJpbnNpY3MvdmxkcmJx X3M4LmMgYi9nY2MvdGVzdHN1aXRlL2djYy50YXJnZXQvYXJtL212ZS9pbnRy aW5zaWNzL3ZsZHJicV9zOC5jCm5ldyBmaWxlIG1vZGUgMTAwNjQ0CmluZGV4 IDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAuLmU1 Y2MzZGViNzliOTA5YTE5Y2JiY2FmZTkyMTNjOTFiNjdhYzMzN2EKLS0tIC9k ZXYvbnVsbAorKysgYi9nY2MvdGVzdHN1aXRlL2djYy50YXJnZXQvYXJtL212 ZS9pbnRyaW5zaWNzL3ZsZHJicV9zOC5jCkBAIC0wLDAgKzEsMTMgQEAKKy8q IHsgZGctZG8gY29tcGlsZSAgfSAqLworLyogeyBkZy1hZGRpdGlvbmFsLW9w dGlvbnMgIi1tYXJjaD1hcm12OC4xLW0ubWFpbittdmUgLW1mbG9hdC1hYmk9 aGFyZCAtTzIiICB9ICAqLworLyogeyBkZy1za2lwLWlmICJTa2lwIGlmIG5v dCBhdXRvIiB7Ki0qLSp9IHsiLW1mcHU9KiJ9IHsiLW1mcHU9YXV0byJ9IH0g Ki8KKworI2luY2x1ZGUgImFybV9tdmUuaCIKKworaW50OHgxNl90Citmb28g KGludDhfdCBjb25zdCAqIGJhc2UpCit7CisgIHJldHVybiB2bGRyYnFfczgg KGJhc2UpOworfQorCisvKiB7IGRnLWZpbmFsIHsgc2Nhbi1hc3NlbWJsZXIg InZsZHJiLnM4IiAgfSAgfSAqLwpkaWZmIC0tZ2l0IGEvZ2NjL3Rlc3RzdWl0 ZS9nY2MudGFyZ2V0L2FybS9tdmUvaW50cmluc2ljcy92bGRyYnFfdTE2LmMg Yi9nY2MvdGVzdHN1aXRlL2djYy50YXJnZXQvYXJtL212ZS9pbnRyaW5zaWNz L3ZsZHJicV91MTYuYwpuZXcgZmlsZSBtb2RlIDEwMDY0NAppbmRleCAwMDAw MDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwLi43ZGVkYmRl NmVlYWUwNjZmZGMwNGU5ZDZmYjZmZTYyNmFmNDU4MGRiCi0tLSAvZGV2L251 bGwKKysrIGIvZ2NjL3Rlc3RzdWl0ZS9nY2MudGFyZ2V0L2FybS9tdmUvaW50 cmluc2ljcy92bGRyYnFfdTE2LmMKQEAgLTAsMCArMSwxMyBAQAorLyogeyBk Zy1kbyBjb21waWxlICB9ICovCisvKiB7IGRnLWFkZGl0aW9uYWwtb3B0aW9u cyAiLW1hcmNoPWFybXY4LjEtbS5tYWluK212ZSAtbWZsb2F0LWFiaT1oYXJk IC1PMiIgIH0gICovCisvKiB7IGRnLXNraXAtaWYgIlNraXAgaWYgbm90IGF1 dG8iIHsqLSotKn0geyItbWZwdT0qIn0geyItbWZwdT1hdXRvIn0gfSAqLwor CisjaW5jbHVkZSAiYXJtX212ZS5oIgorCit1aW50MTZ4OF90Citmb28gKHVp bnQ4X3QgY29uc3QgKiBiYXNlKQoreworICByZXR1cm4gdmxkcmJxX3UxNiAo YmFzZSk7Cit9CisKKy8qIHsgZGctZmluYWwgeyBzY2FuLWFzc2VtYmxlciAi dmxkcmIudTE2IiAgfSAgfSAqLwpkaWZmIC0tZ2l0IGEvZ2NjL3Rlc3RzdWl0 ZS9nY2MudGFyZ2V0L2FybS9tdmUvaW50cmluc2ljcy92bGRyYnFfdTMyLmMg Yi9nY2MvdGVzdHN1aXRlL2djYy50YXJnZXQvYXJtL212ZS9pbnRyaW5zaWNz L3ZsZHJicV91MzIuYwpuZXcgZmlsZSBtb2RlIDEwMDY0NAppbmRleCAwMDAw MDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwLi4zYzNlYzZj NGZmZTZiMDE0YmY1OGQwYjdjMmEyZDUwMWRkZjgzMDFiCi0tLSAvZGV2L251 bGwKKysrIGIvZ2NjL3Rlc3RzdWl0ZS9nY2MudGFyZ2V0L2FybS9tdmUvaW50 cmluc2ljcy92bGRyYnFfdTMyLmMKQEAgLTAsMCArMSwxMyBAQAorLyogeyBk Zy1kbyBjb21waWxlICB9ICovCisvKiB7IGRnLWFkZGl0aW9uYWwtb3B0aW9u cyAiLW1hcmNoPWFybXY4LjEtbS5tYWluK212ZSAtbWZsb2F0LWFiaT1oYXJk IC1PMiIgIH0gICovCisvKiB7IGRnLXNraXAtaWYgIlNraXAgaWYgbm90IGF1 dG8iIHsqLSotKn0geyItbWZwdT0qIn0geyItbWZwdT1hdXRvIn0gfSAqLwor CisjaW5jbHVkZSAiYXJtX212ZS5oIgorCit1aW50MzJ4NF90Citmb28gKHVp bnQ4X3QgY29uc3QgKiBiYXNlKQoreworICByZXR1cm4gdmxkcmJxX3UzMiAo YmFzZSk7Cit9CisKKy8qIHsgZGctZmluYWwgeyBzY2FuLWFzc2VtYmxlciAi dmxkcmIudTMyIiAgfSAgfSAqLwpkaWZmIC0tZ2l0IGEvZ2NjL3Rlc3RzdWl0 ZS9nY2MudGFyZ2V0L2FybS9tdmUvaW50cmluc2ljcy92bGRyYnFfdTguYyBi L2djYy90ZXN0c3VpdGUvZ2NjLnRhcmdldC9hcm0vbXZlL2ludHJpbnNpY3Mv dmxkcmJxX3U4LmMKbmV3IGZpbGUgbW9kZSAxMDA2NDQKaW5kZXggMDAwMDAw MDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMC4uNTMyOGQ5OWJh Yjk0ZDYyYmQwMzJkNGRhMzUwOWNkMmM1NWE3ODQxYQotLS0gL2Rldi9udWxs CisrKyBiL2djYy90ZXN0c3VpdGUvZ2NjLnRhcmdldC9hcm0vbXZlL2ludHJp bnNpY3MvdmxkcmJxX3U4LmMKQEAgLTAsMCArMSwxMyBAQAorLyogeyBkZy1k byBjb21waWxlICB9ICovCisvKiB7IGRnLWFkZGl0aW9uYWwtb3B0aW9ucyAi LW1hcmNoPWFybXY4LjEtbS5tYWluK212ZSAtbWZsb2F0LWFiaT1oYXJkIC1P MiIgIH0gICovCisvKiB7IGRnLXNraXAtaWYgIlNraXAgaWYgbm90IGF1dG8i IHsqLSotKn0geyItbWZwdT0qIn0geyItbWZwdT1hdXRvIn0gfSAqLworCisj aW5jbHVkZSAiYXJtX212ZS5oIgorCit1aW50OHgxNl90Citmb28gKHVpbnQ4 X3QgY29uc3QgKiBiYXNlKQoreworICByZXR1cm4gdmxkcmJxX3U4IChiYXNl KTsKK30KKworLyogeyBkZy1maW5hbCB7IHNjYW4tYXNzZW1ibGVyICJ2bGRy Yi51OCIgIH0gIH0gKi8KZGlmZiAtLWdpdCBhL2djYy90ZXN0c3VpdGUvZ2Nj LnRhcmdldC9hcm0vbXZlL2ludHJpbnNpY3MvdmxkcndxX2dhdGhlcl9iYXNl X3MzMi5jIGIvZ2NjL3Rlc3RzdWl0ZS9nY2MudGFyZ2V0L2FybS9tdmUvaW50 cmluc2ljcy92bGRyd3FfZ2F0aGVyX2Jhc2VfczMyLmMKbmV3IGZpbGUgbW9k ZSAxMDA2NDQKaW5kZXggMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAw MDAwMDAwMDAwMC4uMTQ4MzFhOTFiNjU5MDBkMDQwZjc0YjkwYzU5MmJjMTk1 YWY0Mjg3NAotLS0gL2Rldi9udWxsCisrKyBiL2djYy90ZXN0c3VpdGUvZ2Nj LnRhcmdldC9hcm0vbXZlL2ludHJpbnNpY3MvdmxkcndxX2dhdGhlcl9iYXNl X3MzMi5jCkBAIC0wLDAgKzEsMTMgQEAKKy8qIHsgZGctZG8gY29tcGlsZSAg fSAqLworLyogeyBkZy1hZGRpdGlvbmFsLW9wdGlvbnMgIi1tYXJjaD1hcm12 OC4xLW0ubWFpbittdmUgLW1mbG9hdC1hYmk9aGFyZCAtTzIiICB9ICAqLwor LyogeyBkZy1za2lwLWlmICJTa2lwIGlmIG5vdCBhdXRvIiB7Ki0qLSp9IHsi LW1mcHU9KiJ9IHsiLW1mcHU9YXV0byJ9IH0gKi8KKworI2luY2x1ZGUgImFy bV9tdmUuaCIKKworaW50MzJ4NF90Citmb28gKHVpbnQzMng0X3QgYWRkcikK K3sKKyAgcmV0dXJuIHZsZHJ3cV9nYXRoZXJfYmFzZV9zMzIgKGFkZHIsIDQp OworfQorCisvKiB7IGRnLWZpbmFsIHsgc2Nhbi1hc3NlbWJsZXIgInZsZHJ3 LnUzMiIgIH0gIH0gKi8KZGlmZiAtLWdpdCBhL2djYy90ZXN0c3VpdGUvZ2Nj LnRhcmdldC9hcm0vbXZlL2ludHJpbnNpY3MvdmxkcndxX2dhdGhlcl9iYXNl X3UzMi5jIGIvZ2NjL3Rlc3RzdWl0ZS9nY2MudGFyZ2V0L2FybS9tdmUvaW50 cmluc2ljcy92bGRyd3FfZ2F0aGVyX2Jhc2VfdTMyLmMKbmV3IGZpbGUgbW9k ZSAxMDA2NDQKaW5kZXggMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAwMDAw MDAwMDAwMDAwMC4uNzc1M2VhNmE3YzllYzgzYjkwZjNlNzIzNjgzYzE1NmIy MDYxN2UyMwotLS0gL2Rldi9udWxsCisrKyBiL2djYy90ZXN0c3VpdGUvZ2Nj LnRhcmdldC9hcm0vbXZlL2ludHJpbnNpY3MvdmxkcndxX2dhdGhlcl9iYXNl X3UzMi5jCkBAIC0wLDAgKzEsMTMgQEAKKy8qIHsgZGctZG8gY29tcGlsZSAg fSAqLworLyogeyBkZy1hZGRpdGlvbmFsLW9wdGlvbnMgIi1tYXJjaD1hcm12 OC4xLW0ubWFpbittdmUgLW1mbG9hdC1hYmk9aGFyZCAtTzIiICB9ICAqLwor LyogeyBkZy1za2lwLWlmICJTa2lwIGlmIG5vdCBhdXRvIiB7Ki0qLSp9IHsi LW1mcHU9KiJ9IHsiLW1mcHU9YXV0byJ9IH0gKi8KKworI2luY2x1ZGUgImFy bV9tdmUuaCIKKwordWludDMyeDRfdAorZm9vICh1aW50MzJ4NF90IGFkZHIp Cit7CisgIHJldHVybiB2bGRyd3FfZ2F0aGVyX2Jhc2VfdTMyIChhZGRyLCA0 KTsKK30KKworLyogeyBkZy1maW5hbCB7IHNjYW4tYXNzZW1ibGVyICJ2bGRy dy51MzIiICB9ICB9ICovCgo= --_002_DBBPR08MB47759EE364526D126D90139D9B710DBBPR08MB4775eurp_--