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Thu, 14 Nov 2019 19:12:58 +0000 From: Srinath Parvathaneni To: "gcc-patches@gcc.gnu.org" CC: Richard Earnshaw , Kyrylo Tkachov Subject: [PATCH][ARM][GCC][4/x]: MVE ACLE vector interleaving store intrinsics. Date: Thu, 14 Nov 2019 19:13:00 -0000 Message-ID: References: <157375666998.31400.16652205595246718910.scripted-patch-series@arm.com> In-Reply-To: <157375666998.31400.16652205595246718910.scripted-patch-series@arm.com> Authentication-Results-Original: spf=none (sender IP is ) smtp.mailfrom=Srinath.Parvathaneni@arm.com; X-MS-Exchange-PUrlCount: 2 x-ms-exchange-transport-forked: True x-checkrecipientrouted: true x-ms-oob-tlc-oobclassifiers: OLM:2276;OLM:2276; X-Forefront-Antispam-Report-Untrusted: SFV:NSPM;SFS:(10009020)(4636009)(39860400002)(396003)(366004)(376002)(346002)(136003)(54534003)(199004)(189003)(81156014)(316002)(81166006)(30864003)(2501003)(44832011)(4326008)(74316002)(7696005)(99286004)(478600001)(186003)(11346002)(26005)(54906003)(76176011)(52536014)(5660300002)(446003)(25786009)(71190400001)(71200400001)(33656002)(66946007)(52116002)(305945005)(66556008)(7736002)(66446008)(66476007)(66616009)(64756008)(14444005)(256004)(5024004)(9686003)(966005)(5640700003)(3846002)(66066001)(4001150100001)(6916009)(86362001)(486006)(6506007)(6436002)(14454004)(8936002)(2906002)(6116002)(2351001)(55016002)(8676002)(102836004)(386003)(476003)(6306002)(2004002)(579004)(559001)(569006);DIR:OUT;SFP:1101;SCL:1;SRVR:DBBPR08MB4807;H:DBBPR08MB4775.eurprd08.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: YsHvLoaeigOMbBOzK/J3bFMRoHkb2ad7+rwafF1RluwgO0Q0KEUio5x4z4EurNmSH5tB7jAkKAcC7C3A7FfhMwk1CXaG2+VzSDwYzMprMrj6j4qP2ll7ksgk/eH5baeZCpNnnFqqtbgxMZD46YBAORqDGE+v0ZlqKKDdLqRd2LdVYB0WhkNob/x3A5wpEw9YE9W8L1pZmvcF8ilPYHZpsLyGlUobZ4y0aDK4EQTkQLUPo/aGA+mW0j97yfKbV577TefvbeHgkqYTQsbn2R07lNsmzgOOX6CDovtg1zq3b2i0WLHaP3Tb+IpyT8hMv8LjfYmzW3udFy8Qa7Dzd5WWIcVqdTZ+/uQ33U+yQEZAn6MT/LSFTBYvgMjdZIsXaWM/+l2I4dMLoYK0Juh39povqj+2fN3BBajX+eBYJCa6zcCboscwtTe0uKC/6zYtl0nbQoiQ6sE38xVWTidAOMCM/aKhgr3fizKKGsRhfT3Nun4= Content-Type: multipart/mixed; boundary="_002_DBBPR08MB4775B9A53768600ABCC63EB79B710DBBPR08MB4775eurp_" MIME-Version: 1.0 Original-Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Srinath.Parvathaneni@arm.com; Return-Path: Srinath.Parvathaneni@arm.com X-MS-Exchange-Transport-CrossTenantHeadersStripped: AM5EUR03FT037.eop-EUR03.prod.protection.outlook.com X-MS-Office365-Filtering-Correlation-Id-Prvs: 527289c0-44c2-47a6-9d4a-08d76936a91f X-IsSubscribed: yes X-SW-Source: 2019-11/txt/msg01250.txt.bz2 --_002_DBBPR08MB4775B9A53768600ABCC63EB79B710DBBPR08MB4775eurp_ Content-Type: text/plain; charset="us-ascii" Content-ID: <9467027A8492C14BBC59D6DDA950DD66@eurprd08.prod.outlook.com> Content-Transfer-Encoding: quoted-printable Content-length: 37858 Hello, This patch supports MVE ACLE intrinsics vst4q_s8, vst4q_s16, vst4q_s32, vst= 4q_u8, vst4q_u16, vst4q_u32, vst4q_f16 and vst4q_f32. In this patch arm_mve_builtins.def file is added to the source code in whic= h the builtins for MVE ACLE intrinsics are defined using builtin qualifiers. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more d= etails. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/heli= um/mve-intrinsics Regression tested on arm-none-eabi and found no regressions. Ok for trunk? Thanks, Srinath. gcc/ChangeLog: 2019-11-12 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-builtins.c (CF): Define mve_builtin_data. (VAR1): Define. (ARM_BUILTIN_MVE_PATTERN_START): Define. (arm_init_mve_builtins): Define function. (arm_init_builtins): Add TARGET_HAVE_MVE check. (arm_expand_builtin_1): Check the range of fcode. (arm_expand_mve_builtin): Define function to expand MVE builtins. (arm_expand_builtin): Check the range of fcode. * config/arm/arm_mve.h (__ARM_FEATURE_MVE): Define MVE floating point types. (__ARM_MVE_PRESERVE_USER_NAMESPACE): Define to protect user namespace. (vst4q_s8): Define macro. (vst4q_s16): Likewise. (vst4q_s32): Likewise. (vst4q_u8): Likewise. (vst4q_u16): Likewise. (vst4q_u32): Likewise. (vst4q_f16): Likewise. (vst4q_f32): Likewise. (__arm_vst4q_s8): Define inline builtin. (__arm_vst4q_s16): Likewise. (__arm_vst4q_s32): Likewise. (__arm_vst4q_u8): Likewise. (__arm_vst4q_u16): Likewise. (__arm_vst4q_u32): Likewise. (__arm_vst4q_f16): Likewise. (__arm_vst4q_f32): Likewise. (__ARM_mve_typeid): Define macro with MVE types. (__ARM_mve_coerce): Define macro with _Generic feature. (vst4q): Define polymorphic variant for different vst4q builtins. * config/arm/arm_mve_builtins.def: New file. * config/arm/mve.md (MVE_VLD_ST): Define iterator. (unspec): Define unspec. (mve_vst4q): Define RTL pattern. * config/arm/t-arm (arm.o): Add entry for arm_mve_builtins.def. (arm-builtins.o): Likewise. gcc/testsuite/ChangeLog: 2019-11-12 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vst4q_f16.c: New test. * gcc.target/arm/mve/intrinsics/vst4q_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vst4q_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vst4q_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vst4q_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vst4q_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vst4q_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vst4q_u8.c: Likewise. ############### Attachment also inlined for ease of reply ##########= ##### diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index d4cb0ea3deb49b10266d1620c85e243ed34aee4d..a9f76971ef310118bf7edea6a8d= d3de1da46b46b 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -401,6 +401,13 @@ static arm_builtin_datum neon_builtin_data[] =3D }; =20 #undef CF +#define CF(N,X) CODE_FOR_mve_##N##X +static arm_builtin_datum mve_builtin_data[] =3D +{ +#include "arm_mve_builtins.def" +}; + +#undef CF #undef VAR1 #define VAR1(T, N, A) \ {#N, UP (A), CODE_FOR_arm_##N, 0, T##_QUALIFIERS}, @@ -705,6 +712,13 @@ enum arm_builtins =20 #include "arm_acle_builtins.def" =20 + ARM_BUILTIN_MVE_BASE, + +#undef VAR1 +#define VAR1(T, N, X) \ + ARM_BUILTIN_MVE_##N##X, +#include "arm_mve_builtins.def" + ARM_BUILTIN_MAX }; =20 @@ -714,6 +728,9 @@ enum arm_builtins #define ARM_BUILTIN_NEON_PATTERN_START \ (ARM_BUILTIN_NEON_BASE + 1) =20 +#define ARM_BUILTIN_MVE_PATTERN_START \ + (ARM_BUILTIN_MVE_BASE + 1) + #define ARM_BUILTIN_ACLE_PATTERN_START \ (ARM_BUILTIN_ACLE_BASE + 1) =20 @@ -1219,6 +1236,22 @@ arm_init_acle_builtins (void) } } =20 +/* Set up all the MVE builtins mentioned in arm_mve_builtins.def file. */ +static void +arm_init_mve_builtins (void) +{ + volatile unsigned int i, fcode =3D ARM_BUILTIN_MVE_PATTERN_START; + + arm_init_simd_builtin_scalar_types (); + arm_init_simd_builtin_types (); + + for (i =3D 0; i < ARRAY_SIZE (mve_builtin_data); i++, fcode++) + { + arm_builtin_datum *d =3D &mve_builtin_data[i]; + arm_init_builtin (fcode, d, "__builtin_mve"); + } +} + /* Set up all the NEON builtins, even builtins for instructions that are n= ot in the current target ISA to allow the user to compile particular modul= es with different target specific options that differ from the command line @@ -1961,8 +1994,10 @@ arm_init_builtins (void) =3D add_builtin_function ("__builtin_arm_lane_check", lane_check_fpr, ARM_BUILTIN_SIMD_LANE_CHECK, BUILT_IN_MD, NULL, NULL_TREE); - - arm_init_neon_builtins (); + if (TARGET_HAVE_MVE) + arm_init_mve_builtins (); + else + arm_init_neon_builtins (); arm_init_vfp_builtins (); arm_init_crypto_builtins (); } @@ -2492,10 +2527,14 @@ arm_expand_builtin_1 (int fcode, tree exp, rtx targ= et, int is_void =3D 0; int k; bool neon =3D false; + bool mve =3D false; =20 if (IN_RANGE (fcode, ARM_BUILTIN_VFP_BASE, ARM_BUILTIN_ACLE_BASE - 1)) neon =3D true; =20 + if (IN_RANGE (fcode, ARM_BUILTIN_MVE_BASE, ARM_BUILTIN_MAX - 1)) + mve =3D true; + is_void =3D !!(d->qualifiers[0] & qualifier_void); =20 num_args +=3D is_void; @@ -2535,7 +2574,7 @@ arm_expand_builtin_1 (int fcode, tree exp, rtx target, } else if (d->qualifiers[qualifiers_k] & qualifier_pointer) { - if (neon) + if (neon || mve) args[k] =3D ARG_BUILTIN_NEON_MEMORY; else args[k] =3D ARG_BUILTIN_MEMORY; @@ -2585,6 +2624,26 @@ arm_expand_acle_builtin (int fcode, tree exp, rtx ta= rget) return arm_expand_builtin_1 (fcode, exp, target, d); } =20 +/* Expand an MVE builtin, i.e. those registered only if their respective t= arget + constraints are met. This check happens within arm_expand_builtin. */ + +static rtx +arm_expand_mve_builtin (int fcode, tree exp, rtx target) +{ + if (fcode >=3D ARM_BUILTIN_MVE_BASE && !TARGET_HAVE_MVE) + { + fatal_error (input_location, + "You must enable MVE instructions" + " to use these intrinsics"); + return const0_rtx; + } + + arm_builtin_datum *d + =3D &mve_builtin_data[fcode - ARM_BUILTIN_MVE_PATTERN_START]; + + return arm_expand_builtin_1 (fcode, exp, target, d); +} + /* Expand a Neon builtin, i.e. those registered only if TARGET_NEON holds. Most of these are "special" because they don't have symbolic constants defined per-instruction or per instruction-variant. Instead,= the @@ -2678,6 +2737,8 @@ arm_expand_builtin (tree exp, /* Don't generate any RTL. */ return const0_rtx; } + if (fcode >=3D ARM_BUILTIN_MVE_BASE) + return arm_expand_mve_builtin (fcode, exp, target); =20 if (fcode >=3D ARM_BUILTIN_ACLE_BASE) return arm_expand_acle_builtin (fcode, exp, target); diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 5ffb466596b5d8fc330616a6fcc7ee37d3e28def..39c6a1551a72700292dde8ef6ce= a44ba0907af8d 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -42,6 +42,13 @@ typedef __simd128_float16_t float16x8_t; typedef __simd128_float32_t float32x4_t; #endif =20 +#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ +typedef struct { float16x8_t val[2]; } float16x8x2_t; +typedef struct { float16x8_t val[4]; } float16x8x4_t; +typedef struct { float32x4_t val[2]; } float32x4x2_t; +typedef struct { float32x4_t val[4]; } float32x4x4_t; +#endif + typedef uint16_t mve_pred16_t; typedef __simd128_uint8_t uint8x16_t; typedef __simd128_uint16_t uint16x8_t; @@ -52,6 +59,330 @@ typedef __simd128_int16_t int16x8_t; typedef __simd128_int32_t int32x4_t; typedef __simd128_int64_t int64x2_t; =20 +typedef struct { int16x8_t val[2]; } int16x8x2_t; +typedef struct { int16x8_t val[4]; } int16x8x4_t; +typedef struct { int32x4_t val[2]; } int32x4x2_t; +typedef struct { int32x4_t val[4]; } int32x4x4_t; +typedef struct { int8x16_t val[2]; } int8x16x2_t; +typedef struct { int8x16_t val[4]; } int8x16x4_t; +typedef struct { uint16x8_t val[2]; } uint16x8x2_t; +typedef struct { uint16x8_t val[4]; } uint16x8x4_t; +typedef struct { uint32x4_t val[2]; } uint32x4x2_t; +typedef struct { uint32x4_t val[4]; } uint32x4x4_t; +typedef struct { uint8x16_t val[2]; } uint8x16x2_t; +typedef struct { uint8x16_t val[4]; } uint8x16x4_t; + +#ifndef __ARM_MVE_PRESERVE_USER_NAMESPACE +#define vst4q_s8( __addr, __value) __arm_vst4q_s8( __addr, __value) +#define vst4q_s16( __addr, __value) __arm_vst4q_s16( __addr, __value) +#define vst4q_s32( __addr, __value) __arm_vst4q_s32( __addr, __value) +#define vst4q_u8( __addr, __value) __arm_vst4q_u8( __addr, __value) +#define vst4q_u16( __addr, __value) __arm_vst4q_u16( __addr, __value) +#define vst4q_u32( __addr, __value) __arm_vst4q_u32( __addr, __value) +#define vst4q_f16( __addr, __value) __arm_vst4q_f16( __addr, __value) +#define vst4q_f32( __addr, __value) __arm_vst4q_f32( __addr, __value) +#endif + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst4q_s8 (int8_t * __addr, int8x16x4_t __value) +{ + union { int8x16x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__i =3D __value; + __builtin_mve_vst4qv16qi ((__builtin_neon_qi *) __addr, __rv.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst4q_s16 (int16_t * __addr, int16x8x4_t __value) +{ + union { int16x8x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__i =3D __value; + __builtin_mve_vst4qv8hi ((__builtin_neon_hi *) __addr, __rv.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst4q_s32 (int32_t * __addr, int32x4x4_t __value) +{ + union { int32x4x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__i =3D __value; + __builtin_mve_vst4qv4si ((__builtin_neon_si *) __addr, __rv.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst4q_u8 (uint8_t * __addr, uint8x16x4_t __value) +{ + union { uint8x16x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__i =3D __value; + __builtin_mve_vst4qv16qi ((__builtin_neon_qi *) __addr, __rv.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst4q_u16 (uint16_t * __addr, uint16x8x4_t __value) +{ + union { uint16x8x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__i =3D __value; + __builtin_mve_vst4qv8hi ((__builtin_neon_hi *) __addr, __rv.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst4q_u32 (uint32_t * __addr, uint32x4x4_t __value) +{ + union { uint32x4x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__i =3D __value; + __builtin_mve_vst4qv4si ((__builtin_neon_si *) __addr, __rv.__o); +} + +#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst4q_f16 (float16_t * __addr, float16x8x4_t __value) +{ + union { float16x8x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__i =3D __value; + __builtin_mve_vst4qv8hf (__addr, __rv.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vst4q_f32 (float32_t * __addr, float32x4x4_t __value) +{ + union { float32x4x4_t __i; __builtin_neon_xi __o; } __rv; + __rv.__i =3D __value; + __builtin_mve_vst4qv4sf (__addr, __rv.__o); +} + +#endif + +enum { + __ARM_mve_type_float16_t =3D 1, + __ARM_mve_type_float16_t_ptr, + __ARM_mve_type_float16_t_const_ptr, + __ARM_mve_type_float16x8_t, + __ARM_mve_type_float16x8x2_t, + __ARM_mve_type_float16x8x4_t, + __ARM_mve_type_float32_t, + __ARM_mve_type_float32_t_ptr, + __ARM_mve_type_float32_t_const_ptr, + __ARM_mve_type_float32x4_t, + __ARM_mve_type_float32x4x2_t, + __ARM_mve_type_float32x4x4_t, + __ARM_mve_type_int16_t, + __ARM_mve_type_int16_t_ptr, + __ARM_mve_type_int16_t_const_ptr, + __ARM_mve_type_int16x8_t, + __ARM_mve_type_int16x8x2_t, + __ARM_mve_type_int16x8x4_t, + __ARM_mve_type_int32_t, + __ARM_mve_type_int32_t_ptr, + __ARM_mve_type_int32_t_const_ptr, + __ARM_mve_type_int32x4_t, + __ARM_mve_type_int32x4x2_t, + __ARM_mve_type_int32x4x4_t, + __ARM_mve_type_int64_t, + __ARM_mve_type_int64_t_ptr, + __ARM_mve_type_int64_t_const_ptr, + __ARM_mve_type_int64x2_t, + __ARM_mve_type_int8_t, + __ARM_mve_type_int8_t_ptr, + __ARM_mve_type_int8_t_const_ptr, + __ARM_mve_type_int8x16_t, + __ARM_mve_type_int8x16x2_t, + __ARM_mve_type_int8x16x4_t, + __ARM_mve_type_uint16_t, + __ARM_mve_type_uint16_t_ptr, + __ARM_mve_type_uint16_t_const_ptr, + __ARM_mve_type_uint16x8_t, + __ARM_mve_type_uint16x8x2_t, + __ARM_mve_type_uint16x8x4_t, + __ARM_mve_type_uint32_t, + __ARM_mve_type_uint32_t_ptr, + __ARM_mve_type_uint32_t_const_ptr, + __ARM_mve_type_uint32x4_t, + __ARM_mve_type_uint32x4x2_t, + __ARM_mve_type_uint32x4x4_t, + __ARM_mve_type_uint64_t, + __ARM_mve_type_uint64_t_ptr, + __ARM_mve_type_uint64_t_const_ptr, + __ARM_mve_type_uint64x2_t, + __ARM_mve_type_uint8_t, + __ARM_mve_type_uint8_t_ptr, + __ARM_mve_type_uint8_t_const_ptr, + __ARM_mve_type_uint8x16_t, + __ARM_mve_type_uint8x16x2_t, + __ARM_mve_type_uint8x16x4_t, + __ARM_mve_unsupported_type +}; + +#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ +#define __ARM_mve_typeid(x) _Generic(x, \ + float16_t: __ARM_mve_type_float16_t, \ + float16_t *: __ARM_mve_type_float16_t_ptr, \ + float16_t const *: __ARM_mve_type_float16_t_const_ptr, \ + float16x8_t: __ARM_mve_type_float16x8_t, \ + float16x8x2_t: __ARM_mve_type_float16x8x2_t, \ + float16x8x4_t: __ARM_mve_type_float16x8x4_t, \ + float32_t: __ARM_mve_type_float32_t, \ + float32_t *: __ARM_mve_type_float32_t_ptr, \ + float32_t const *: __ARM_mve_type_float32_t_const_ptr, \ + float32x4_t: __ARM_mve_type_float32x4_t, \ + float32x4x2_t: __ARM_mve_type_float32x4x2_t, \ + float32x4x4_t: __ARM_mve_type_float32x4x4_t, \ + int16_t: __ARM_mve_type_int16_t, \ + int16_t *: __ARM_mve_type_int16_t_ptr, \ + int16_t const *: __ARM_mve_type_int16_t_const_ptr, \ + int16x8_t: __ARM_mve_type_int16x8_t, \ + int16x8x2_t: __ARM_mve_type_int16x8x2_t, \ + int16x8x4_t: __ARM_mve_type_int16x8x4_t, \ + int32_t: __ARM_mve_type_int32_t, \ + int32_t *: __ARM_mve_type_int32_t_ptr, \ + int32_t const *: __ARM_mve_type_int32_t_const_ptr, \ + int32x4_t: __ARM_mve_type_int32x4_t, \ + int32x4x2_t: __ARM_mve_type_int32x4x2_t, \ + int32x4x4_t: __ARM_mve_type_int32x4x4_t, \ + int64_t: __ARM_mve_type_int64_t, \ + int64_t *: __ARM_mve_type_int64_t_ptr, \ + int64_t const *: __ARM_mve_type_int64_t_const_ptr, \ + int64x2_t: __ARM_mve_type_int64x2_t, \ + int8_t: __ARM_mve_type_int8_t, \ + int8_t *: __ARM_mve_type_int8_t_ptr, \ + int8_t const *: __ARM_mve_type_int8_t_const_ptr, \ + int8x16_t: __ARM_mve_type_int8x16_t, \ + int8x16x2_t: __ARM_mve_type_int8x16x2_t, \ + int8x16x4_t: __ARM_mve_type_int8x16x4_t, \ + uint16_t: __ARM_mve_type_uint16_t, \ + uint16_t *: __ARM_mve_type_uint16_t_ptr, \ + uint16_t const *: __ARM_mve_type_uint16_t_const_ptr, \ + uint16x8_t: __ARM_mve_type_uint16x8_t, \ + uint16x8x2_t: __ARM_mve_type_uint16x8x2_t, \ + uint16x8x4_t: __ARM_mve_type_uint16x8x4_t, \ + uint32_t: __ARM_mve_type_uint32_t, \ + uint32_t *: __ARM_mve_type_uint32_t_ptr, \ + uint32_t const *: __ARM_mve_type_uint32_t_const_ptr, \ + uint32x4_t: __ARM_mve_type_uint32x4_t, \ + uint32x4x2_t: __ARM_mve_type_uint32x4x2_t, \ + uint32x4x4_t: __ARM_mve_type_uint32x4x4_t, \ + uint64_t: __ARM_mve_type_uint64_t, \ + uint64_t *: __ARM_mve_type_uint64_t_ptr, \ + uint64_t const *: __ARM_mve_type_uint64_t_const_ptr, \ + uint64x2_t: __ARM_mve_type_uint64x2_t, \ + uint8_t: __ARM_mve_type_uint8_t, \ + uint8_t *: __ARM_mve_type_uint8_t_ptr, \ + uint8_t const *: __ARM_mve_type_uint8_t_const_ptr, \ + uint8x16_t: __ARM_mve_type_uint8x16_t, \ + uint8x16x2_t: __ARM_mve_type_uint8x16x2_t, \ + uint8x16x4_t: __ARM_mve_type_uint8x16x4_t, \ + default: _Generic(x, \ + signed char: __ARM_mve_type_int8_t, \ + short: __ARM_mve_type_int16_t, \ + int: __ARM_mve_type_int32_t, \ + long: __ARM_mve_type_int32_t, \ + long long: __ARM_mve_type_int64_t, \ + unsigned char: __ARM_mve_type_uint8_t, \ + unsigned short: __ARM_mve_type_uint16_t, \ + unsigned int: __ARM_mve_type_uint32_t, \ + unsigned long: __ARM_mve_type_uint32_t, \ + unsigned long long: __ARM_mve_type_uint64_t, \ + default: __ARM_mve_unsupported_type)) +#else +#define __ARM_mve_typeid(x) _Generic(x, \ + int16_t: __ARM_mve_type_int16_t, \ + int16_t *: __ARM_mve_type_int16_t_ptr, \ + int16_t const *: __ARM_mve_type_int16_t_const_ptr, \ + int16x8_t: __ARM_mve_type_int16x8_t, \ + int16x8x2_t: __ARM_mve_type_int16x8x2_t, \ + int16x8x4_t: __ARM_mve_type_int16x8x4_t, \ + int32_t: __ARM_mve_type_int32_t, \ + int32_t *: __ARM_mve_type_int32_t_ptr, \ + int32_t const *: __ARM_mve_type_int32_t_const_ptr, \ + int32x4_t: __ARM_mve_type_int32x4_t, \ + int32x4x2_t: __ARM_mve_type_int32x4x2_t, \ + int32x4x4_t: __ARM_mve_type_int32x4x4_t, \ + int64_t: __ARM_mve_type_int64_t, \ + int64_t *: __ARM_mve_type_int64_t_ptr, \ + int64_t const *: __ARM_mve_type_int64_t_const_ptr, \ + int64x2_t: __ARM_mve_type_int64x2_t, \ + int8_t: __ARM_mve_type_int8_t, \ + int8_t *: __ARM_mve_type_int8_t_ptr, \ + int8_t const *: __ARM_mve_type_int8_t_const_ptr, \ + int8x16_t: __ARM_mve_type_int8x16_t, \ + int8x16x2_t: __ARM_mve_type_int8x16x2_t, \ + int8x16x4_t: __ARM_mve_type_int8x16x4_t, \ + uint16_t: __ARM_mve_type_uint16_t, \ + uint16_t *: __ARM_mve_type_uint16_t_ptr, \ + uint16_t const *: __ARM_mve_type_uint16_t_const_ptr, \ + uint16x8_t: __ARM_mve_type_uint16x8_t, \ + uint16x8x2_t: __ARM_mve_type_uint16x8x2_t, \ + uint16x8x4_t: __ARM_mve_type_uint16x8x4_t, \ + uint32_t: __ARM_mve_type_uint32_t, \ + uint32_t *: __ARM_mve_type_uint32_t_ptr, \ + uint32_t const *: __ARM_mve_type_uint32_t_const_ptr, \ + uint32x4_t: __ARM_mve_type_uint32x4_t, \ + uint32x4x2_t: __ARM_mve_type_uint32x4x2_t, \ + uint32x4x4_t: __ARM_mve_type_uint32x4x4_t, \ + uint64_t: __ARM_mve_type_uint64_t, \ + uint64_t *: __ARM_mve_type_uint64_t_ptr, \ + uint64_t const *: __ARM_mve_type_uint64_t_const_ptr, \ + uint64x2_t: __ARM_mve_type_uint64x2_t, \ + uint8_t: __ARM_mve_type_uint8_t, \ + uint8_t *: __ARM_mve_type_uint8_t_ptr, \ + uint8_t const *: __ARM_mve_type_uint8_t_const_ptr, \ + uint8x16_t: __ARM_mve_type_uint8x16_t, \ + uint8x16x2_t: __ARM_mve_type_uint8x16x2_t, \ + uint8x16x4_t: __ARM_mve_type_uint8x16x4_t, \ + default: _Generic(x, \ + signed char: __ARM_mve_type_int8_t, \ + short: __ARM_mve_type_int16_t, \ + int: __ARM_mve_type_int32_t, \ + long: __ARM_mve_type_int32_t, \ + long long: __ARM_mve_type_int64_t, \ + unsigned char: __ARM_mve_type_uint8_t, \ + unsigned short: __ARM_mve_type_uint16_t, \ + unsigned int: __ARM_mve_type_uint32_t, \ + unsigned long: __ARM_mve_type_uint32_t, \ + unsigned long long: __ARM_mve_type_uint64_t, \ + default: __ARM_mve_unsupported_type)) +#endif /* MVE Floating point. */ + +extern void *__ARM_undef; +#define __ARM_mve_coerce(param, type) \ + _Generic(param, type: param, default: *(type *)__ARM_undef) + +#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ + +#define vst4q(p0,p1) __arm_vst4q(p0,p1) +#define __arm_vst4q(p0,p1) ({ __typeof(p0) __p0 =3D (p0); \ + __typeof(p1) __p1 =3D (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x4_t]: __arm_vs= t4q_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x4_= t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x4_t]: __arm_v= st4q_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, int16x8= x4_t)), \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x4_t]: __arm_v= st4q_s32 (__ARM_mve_coerce(__p0, int32_t *), __ARM_mve_coerce(__p1, int32x4= x4_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x4_t]: __arm_= vst4q_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x1= 6x4_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]: __arm= _vst4q_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint= 16x8x4_t)), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]: __arm= _vst4q_u32 (__ARM_mve_coerce(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint= 32x4x4_t)), \ + int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x4_t]: __a= rm_vst4q_f16 (__ARM_mve_coerce(__p0, float16_t *), __ARM_mve_coerce(__p1, f= loat16x8x4_t)), \ + int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x4_t]: __a= rm_vst4q_f32 (__ARM_mve_coerce(__p0, float32_t *), __ARM_mve_coerce(__p1, f= loat32x4x4_t)));}) + +#else /* MVE Interger. */ + +#define vst4q(p0,p1) __arm_vst4q(p0,p1) +#define __arm_vst4q(p0,p1) ({ __typeof(p0) __p0 =3D (p0); \ + __typeof(p1) __p1 =3D (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8_t_ptr][__ARM_mve_type_int8x16x4_t]: __arm_vs= t4q_s8 (__ARM_mve_coerce(__p0, int8_t *), __ARM_mve_coerce(__p1, int8x16x4_= t)), \ + int (*)[__ARM_mve_type_int16_t_ptr][__ARM_mve_type_int16x8x4_t]: __arm_v= st4q_s16 (__ARM_mve_coerce(__p0, int16_t *), __ARM_mve_coerce(__p1, int16x8= x4_t)), \ + int (*)[__ARM_mve_type_int32_t_ptr][__ARM_mve_type_int32x4x4_t]: __arm_v= st4q_s32 (__ARM_mve_coerce(__p0, int32_t *), __ARM_mve_coerce(__p1, int32x4= x4_t)), \ + int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint8x16x4_t]: __arm_= vst4q_u8 (__ARM_mve_coerce(__p0, uint8_t *), __ARM_mve_coerce(__p1, uint8x1= 6x4_t)), \ + int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]: __arm= _vst4q_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint= 16x8x4_t)), \ + int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]: __arm= _vst4q_u32 (__ARM_mve_coerce(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint= 32x4x4_t)));}) + +#endif /* MVE Floating point. */ + #ifdef __cplusplus } #endif diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_b= uiltins.def new file mode 100644 index 0000000000000000000000000000000000000000..c7f3546c9cb0ec3ae794e181e53= 3a1cbed38121c --- /dev/null +++ b/gcc/config/arm/arm_mve_builtins.def @@ -0,0 +1,21 @@ +/* MVE builtin definitions for Arm. + Copyright (C) 2019 Free Software Foundation, Inc. + Contributed by Arm. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not see + . */ + +VAR5 (STORE1, vst4q, v16qi, v8hi, v4si, v8hf, v4sf) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 53334c6d329dedd482615b996232e85ded7a34f8..a2f5220eccb6d888b9b0b1bbd10= 54cc3a6be97f5 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -17,9 +17,12 @@ ;; along with GCC; see the file COPYING3. If not see ;; . =20 -(define_mode_iterator MVE_types [V16QI V8HI V4SI V2DI TI V8HF V4SF V2DF]) (define_mode_attr V_sz_elem2 [(V16QI "s8") (V8HI "u16") (V4SI "u32") (V2DI "u64")]) +(define_mode_iterator MVE_types [V16QI V8HI V4SI V2DI TI V8HF V4SF V2DF]) +(define_mode_iterator MVE_VLD_ST [V16QI V8HI V4SI V8HF V4SF]) + +(define_c_enum "unspec" [VST4Q]) =20 (define_insn "*mve_mov" [(set (match_operand:MVE_types 0 "s_register_operand" "=3Dw,w,r,w,w,r,w") @@ -76,3 +79,37 @@ "TARGET_HAVE_MVE" "vstrb. %q1, %E0" [(set_attr "type" "mve_store")]) + +;; +;; [vst4q]) +;; +(define_insn "mve_vst4q" + [(set (match_operand:XI 0 "neon_struct_operand" "=3DUm") + (unspec:XI [(match_operand:XI 1 "s_register_operand" "w") + (unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + VST4Q)) + ] + "TARGET_HAVE_MVE" +{ + rtx ops[6]; + int regno =3D REGNO (operands[1]); + ops[0] =3D gen_rtx_REG (TImode, regno); + ops[1] =3D gen_rtx_REG (TImode, regno+4); + ops[2] =3D gen_rtx_REG (TImode, regno+8); + ops[3] =3D gen_rtx_REG (TImode, regno+12); + rtx reg =3D operands[0]; + while (reg && !REG_P (reg)) + reg =3D XEXP (reg, 0); + gcc_assert (REG_P (reg)); + ops[4] =3D reg; + ops[5] =3D operands[0]; + /* Here in first three instructions data is stored to ops[4]'s location= but + in the fourth instruction data is stored to operands[0], this is to + support the writeback. */ + output_asm_insn ("vst40.\t{%q0, %q1, %q2, %q3}, [%4]\n\t" + "vst41.\t{%q0, %q1, %q2, %q3}, [%4]\n\t" + "vst42.\t{%q0, %q1, %q2, %q3}, [%4]\n\t" + "vst43.\t{%q0, %q1, %q2, %q3}, %5", ops); + return ""; +} + [(set_attr "length" "16")]) diff --git a/gcc/config/arm/t-arm b/gcc/config/arm/t-arm index fda5e84355b56a20eb9a22919ab1c786120cc8f1..fbd99197b31ee4b69b7a0659212= 3b6facd04f9af 100644 --- a/gcc/config/arm/t-arm +++ b/gcc/config/arm/t-arm @@ -135,7 +135,8 @@ arm.o: $(srcdir)/config/arm/arm.c $(CONFIG_H) $(SYSTEM_= H) coretypes.h $(TM_H) \ arm-cpu-data.h \ $(srcdir)/config/arm/arm-protos.h \ $(srcdir)/config/arm/arm_neon_builtins.def \ - $(srcdir)/config/arm/arm_vfp_builtins.def + $(srcdir)/config/arm/arm_vfp_builtins.def \ + $(srcdir)/config/arm/arm_mve_builtins.def =20 arm-builtins.o: $(srcdir)/config/arm/arm-builtins.c $(CONFIG_H) \ $(SYSTEM_H) coretypes.h $(TM_H) \ @@ -145,6 +146,7 @@ arm-builtins.o: $(srcdir)/config/arm/arm-builtins.c $(C= ONFIG_H) \ $(srcdir)/config/arm/arm_acle_builtins.def \ $(srcdir)/config/arm/arm_neon_builtins.def \ $(srcdir)/config/arm/arm_vfp_builtins.def \ + $(srcdir)/config/arm/arm_mve_builtins.def \ $(srcdir)/config/arm/arm-simd-builtin-types.def $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ $(srcdir)/config/arm/arm-builtins.c diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f16.c b/gcc/= testsuite/gcc.target/arm/mve/intrinsics/vst4q_f16.c new file mode 100644 index 0000000000000000000000000000000000000000..6f8ea17345b85983202613b0f48= 1b23e0532fd16 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f16.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve.fp -mfloat-abi=3Dh= ard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +void +foo (float16_t * addr, float16x8x4_t value) +{ + vst4q_f16 (addr, value); +} + +/* { dg-final { scan-assembler "vst40.16" } } */ +/* { dg-final { scan-assembler "vst41.16" } } */ +/* { dg-final { scan-assembler "vst42.16" } } */ +/* { dg-final { scan-assembler "vst43.16" } } */ + +void +foo1 (float16_t * addr, float16x8x4_t value) +{ + vst4q (addr, value); +} + +/* { dg-final { scan-assembler "vst40.16" } } */ +/* { dg-final { scan-assembler "vst41.16" } } */ +/* { dg-final { scan-assembler "vst42.16" } } */ +/* { dg-final { scan-assembler "vst43.16" } } */ + +void +foo2 (float16_t * addr, float16x8x4_t value) +{ + vst4q_f16 (addr, value); + addr +=3D 32; + vst4q_f16 (addr, value); +} + +/* { dg-final { scan-assembler {vst43.16\s\{.*\}, \[.*\]!} } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f32.c b/gcc/= testsuite/gcc.target/arm/mve/intrinsics/vst4q_f32.c new file mode 100644 index 0000000000000000000000000000000000000000..03b1dbb5b13e2c41013c772d944= f29da8c2468f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f32.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve.fp -mfloat-abi=3Dh= ard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +void +foo (float32_t * addr, float32x4x4_t value) +{ + vst4q_f32 (addr, value); +} + +/* { dg-final { scan-assembler "vst40.32" } } */ +/* { dg-final { scan-assembler "vst41.32" } } */ +/* { dg-final { scan-assembler "vst42.32" } } */ +/* { dg-final { scan-assembler "vst43.32" } } */ + +void +foo1 (float32_t * addr, float32x4x4_t value) +{ + vst4q (addr, value); +} + +/* { dg-final { scan-assembler "vst40.32" } } */ +/* { dg-final { scan-assembler "vst41.32" } } */ +/* { dg-final { scan-assembler "vst42.32" } } */ +/* { dg-final { scan-assembler "vst43.32" } } */ + +void +foo2 (float32_t * addr, float32x4x4_t value) +{ + vst4q_f32 (addr, value); + addr +=3D 16; + vst4q_f32 (addr, value); +} + +/* { dg-final { scan-assembler {vst43.32\s\{.*\}, \[.*\]!} } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s16.c b/gcc/= testsuite/gcc.target/arm/mve/intrinsics/vst4q_s16.c new file mode 100644 index 0000000000000000000000000000000000000000..05f53fc9175b41e4d16c7a6bc52= 5b57b626a632d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s16.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +void +foo (int16_t * addr, int16x8x4_t value) +{ + vst4q_s16 (addr, value); +} + +/* { dg-final { scan-assembler "vst40.16" } } */ +/* { dg-final { scan-assembler "vst41.16" } } */ +/* { dg-final { scan-assembler "vst42.16" } } */ +/* { dg-final { scan-assembler "vst43.16" } } */ + +void +foo1 (int16_t * addr, int16x8x4_t value) +{ + vst4q (addr, value); +} + +/* { dg-final { scan-assembler "vst40.16" } } */ +/* { dg-final { scan-assembler "vst41.16" } } */ +/* { dg-final { scan-assembler "vst42.16" } } */ +/* { dg-final { scan-assembler "vst43.16" } } */ + +void +foo2 (int16_t * addr, int16x8x4_t value) +{ + vst4q_s16 (addr, value); + addr +=3D 32; + vst4q_s16 (addr, value); +} + +/* { dg-final { scan-assembler {vst43.16\s\{.*\}, \[.*\]!} } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s32.c b/gcc/= testsuite/gcc.target/arm/mve/intrinsics/vst4q_s32.c new file mode 100644 index 0000000000000000000000000000000000000000..9da2addb8c3d9566722b640f66b= bee4f2b4b563d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s32.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +void +foo (int32_t * addr, int32x4x4_t value) +{ + vst4q_s32 (addr, value); +} + +/* { dg-final { scan-assembler "vst40.32" } } */ +/* { dg-final { scan-assembler "vst41.32" } } */ +/* { dg-final { scan-assembler "vst42.32" } } */ +/* { dg-final { scan-assembler "vst43.32" } } */ + +void +foo1 (int32_t * addr, int32x4x4_t value) +{ + vst4q (addr, value); +} + +/* { dg-final { scan-assembler "vst40.32" } } */ +/* { dg-final { scan-assembler "vst41.32" } } */ +/* { dg-final { scan-assembler "vst42.32" } } */ +/* { dg-final { scan-assembler "vst43.32" } } */ + +void +foo2 (int32_t * addr, int32x4x4_t value) +{ + vst4q_s32 (addr, value); + addr +=3D 16; + vst4q_s32 (addr, value);=20 +} + +/* { dg-final { scan-assembler {vst43.32\s\{.*\}, \[.*\]!} } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s8.c b/gcc/t= estsuite/gcc.target/arm/mve/intrinsics/vst4q_s8.c new file mode 100644 index 0000000000000000000000000000000000000000..1243d135e1628de14596a58f24a= 79f45299ce517 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s8.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +void +foo (int8_t * addr, int8x16x4_t value) +{ + vst4q_s8 (addr, value); +} + +/* { dg-final { scan-assembler "vst40.8" } } */ +/* { dg-final { scan-assembler "vst41.8" } } */ +/* { dg-final { scan-assembler "vst42.8" } } */ +/* { dg-final { scan-assembler "vst43.8" } } */ + +void +foo1 (int8_t * addr, int8x16x4_t value) +{ + vst4q (addr, value); +} + +/* { dg-final { scan-assembler "vst40.8" } } */ +/* { dg-final { scan-assembler "vst41.8" } } */ +/* { dg-final { scan-assembler "vst42.8" } } */ +/* { dg-final { scan-assembler "vst43.8" } } */ + +void +foo2 (int8_t * addr, int8x16x4_t value) +{ + vst4q_s8 (addr, value); + addr +=3D 16*4; + vst4q_s8 (addr, value); +} + +/* { dg-final { scan-assembler {vst43.8\s\{.*\}, \[.*\]!} } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u16.c b/gcc/= testsuite/gcc.target/arm/mve/intrinsics/vst4q_u16.c new file mode 100644 index 0000000000000000000000000000000000000000..09097e7914ed08dda5e7616bafe= 35cdb30486f21 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u16.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +void +foo (uint16_t * addr, uint16x8x4_t value) +{ + vst4q_u16 (addr, value); +} + +/* { dg-final { scan-assembler "vst40.16" } } */ +/* { dg-final { scan-assembler "vst41.16" } } */ +/* { dg-final { scan-assembler "vst42.16" } } */ +/* { dg-final { scan-assembler "vst43.16" } } */ + +void +foo1 (uint16_t * addr, uint16x8x4_t value) +{ + vst4q (addr, value); +} + +/* { dg-final { scan-assembler "vst40.16" } } */ +/* { dg-final { scan-assembler "vst41.16" } } */ +/* { dg-final { scan-assembler "vst42.16" } } */ +/* { dg-final { scan-assembler "vst43.16" } } */ + +void +foo2 (uint16_t * addr, uint16x8x4_t value) +{ + vst4q_u16 (addr, value); + addr +=3D 32; + vst4q_u16 (addr, value); +} + +/* { dg-final { scan-assembler {vst43.16\s\{.*\}, \[.*\]!} } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u32.c b/gcc/= testsuite/gcc.target/arm/mve/intrinsics/vst4q_u32.c new file mode 100644 index 0000000000000000000000000000000000000000..dcb0a10f9f21e4adb70d18b590f= cc7b663547f16 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u32.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +void +foo (uint32_t * addr, uint32x4x4_t value) +{ + vst4q_u32 (addr, value); +} + +/* { dg-final { scan-assembler "vst40.32" } } */ +/* { dg-final { scan-assembler "vst41.32" } } */ +/* { dg-final { scan-assembler "vst42.32" } } */ +/* { dg-final { scan-assembler "vst43.32" } } */ + +void +foo1 (uint32_t * addr, uint32x4x4_t value) +{ + vst4q (addr, value); +} + +/* { dg-final { scan-assembler "vst40.32" } } */ +/* { dg-final { scan-assembler "vst41.32" } } */ +/* { dg-final { scan-assembler "vst42.32" } } */ +/* { dg-final { scan-assembler "vst43.32" } } */ + +void +foo2 (uint32_t * addr, uint32x4x4_t value) +{ + vst4q_u32 (addr, value); + addr +=3D 16; + vst4q_u32 (addr, value);=20 +} + +/* { dg-final { scan-assembler {vst43.32\s\{.*\}, \[.*\]!} } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u8.c b/gcc/t= estsuite/gcc.target/arm/mve/intrinsics/vst4q_u8.c new file mode 100644 index 0000000000000000000000000000000000000000..b18f57dd6356c2fdf39cbf14ca8= 5373c98f1c62c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u8.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=3Darmv8.1-m.main+mve -mfloat-abi=3Dhard= -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=3D*"} {"-mfpu=3Dauto"} = } */ + +#include "arm_mve.h" + +void +foo (uint8_t * addr, uint8x16x4_t value) +{ + vst4q_u8 (addr, value); +} + +/* { dg-final { scan-assembler "vst40.8" } } */ +/* { dg-final { scan-assembler "vst41.8" } } */ +/* { dg-final { scan-assembler "vst42.8" } } */ +/* { dg-final { scan-assembler "vst43.8" } } */ + +void +foo1 (uint8_t * addr, uint8x16x4_t value) +{ + vst4q (addr, value); +} + +/* { dg-final { scan-assembler "vst40.8" } } */ +/* { dg-final { scan-assembler "vst41.8" } } */ +/* { dg-final { scan-assembler "vst42.8" } } */ +/* { dg-final { scan-assembler "vst43.8" } } */ + +void +foo2 (uint8_t * addr, uint8x16x4_t value) +{ + vst4q_u8 (addr, value); + addr +=3D 16*4; + vst4q_u8 (addr, value); +} + +/* { dg-final { scan-assembler {vst43.8\s\{.*\}, \[.*\]!} } } */ --_002_DBBPR08MB4775B9A53768600ABCC63EB79B710DBBPR08MB4775eurp_ Content-Type: text/plain; name="diff03.patch" Content-Description: diff03.patch Content-Disposition: attachment; filename="diff03.patch"; size=34616; creation-date="Thu, 14 Nov 2019 19:12:58 GMT"; modification-date="Thu, 14 Nov 2019 19:12:58 GMT" Content-ID: Content-Transfer-Encoding: base64 Content-length: 46926 ZGlmZiAtLWdpdCBhL2djYy9jb25maWcvYXJtL2FybS1idWlsdGlucy5jIGIv Z2NjL2NvbmZpZy9hcm0vYXJtLWJ1aWx0aW5zLmMKaW5kZXggZDRjYjBlYTNk ZWI0OWIxMDI2NmQxNjIwYzg1ZTI0M2VkMzRhZWU0ZC4uYTlmNzY5NzFlZjMx MDExOGJmN2VkZWE2YThkZDNkZTFkYTQ2YjQ2YiAxMDA2NDQKLS0tIGEvZ2Nj L2NvbmZpZy9hcm0vYXJtLWJ1aWx0aW5zLmMKKysrIGIvZ2NjL2NvbmZpZy9h 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