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From: "juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai>
To: "Robin Dapp" <rdapp.gcc@gmail.com>,
	 gcc-patches <gcc-patches@gcc.gnu.org>
Cc: "Robin Dapp" <rdapp.gcc@gmail.com>,
	 kito.cheng <kito.cheng@gmail.com>,
	 Kito.cheng <kito.cheng@sifive.com>,
	 jeffreyalaw <jeffreyalaw@gmail.com>
Subject: Re: Re: [PATCH] RISC-V: Enable SLP un-order reduction
Date: Tue, 18 Jul 2023 16:45:25 +0800	[thread overview]
Message-ID: <DC85179AE389297B+2023071816452364424068@rivai.ai> (raw)
In-Reply-To: <03b45c00-c10a-e238-429c-dd6f12467cc5@gmail.com>

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Address comment with V2:
https://gcc.gnu.org/pipermail/gcc-patches/2023-July/624754.html 
with moving the location of VSET_SHI_INSERT patterns.



juzhe.zhong@rivai.ai
 
From: Robin Dapp
Date: 2023-07-18 15:54
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Enable SLP un-order reduction
Hi Juzhe,
 
> +;; -------------------------------------------------------------------------
> +;; ---- [INT,FP] Initialize from individual elements
> +;; -------------------------------------------------------------------------
> +;; Includes:
> +;; - vslide1up.vx/vfslide1up.vf
> +;; -------------------------------------------------------------------------
> +
 
Wouldn't you want to add this to the already existing "section" with
the same name? (where vec_init is).
 
Apart from that LGTM, thanks.
 
> +;; Slide an RVV vector left and insert a scalar into element 0.
> +(define_expand "vec_shl_insert_<mode>"
> +  [(match_operand:VI 0 "register_operand")
> +   (match_operand:VI 1 "register_operand")
> +   (match_operand:<VEL> 2 "reg_or_0_operand")]
> +  "TARGET_VECTOR"
> +{
> +  insn_code icode = code_for_pred_slide (UNSPEC_VSLIDE1UP, <MODE>mode);
> +  rtx ops[] = {operands[0], RVV_VUNDEF (<MODE>mode), operands[1], operands[2]};
> +  riscv_vector::emit_vlmax_slide_insn (icode, ops);
> +  DONE;
> +})
> +
> +(define_expand "vec_shl_insert_<mode>"
> +  [(match_operand:VF 0 "register_operand")
> +   (match_operand:VF 1 "register_operand")
> +   (match_operand:<VEL> 2 "register_operand")]
> +  "TARGET_VECTOR"
> +{
> +  insn_code icode = code_for_pred_slide (UNSPEC_VFSLIDE1UP, <MODE>mode);
> +  rtx ops[] = {operands[0], RVV_VUNDEF (<MODE>mode), operands[1], operands[2]};
> +  riscv_vector::emit_vlmax_slide_insn (icode, ops);
> +  DONE;
> +})
 
It appears bit unfortunate here that we have two different insn patterns
for int and float when they are so similar but I guess that's the consequence
of the implicit sign extend.  We can still have emit_vlmax_slide_insn
(or some other function) differentiate between them and unify at the
expander site in the future, though.
 
Regards
Robin
 

      reply	other threads:[~2023-07-18  8:45 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-18  1:03 Juzhe-Zhong
2023-07-18  7:54 ` Robin Dapp
2023-07-18  8:45   ` juzhe.zhong [this message]

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