From: "Stepanyan, Victoria" <Victoria.Stepanyan@amd.com>
To: "'gcc-patches@gcc.gnu.org'" <gcc-patches@gcc.gnu.org>
Cc: "'gerald@pfeifer.com'" <gerald@pfeifer.com>,
"'ubizjak@gmail.com'" <ubizjak@gmail.com>,
"'rguenther@suse.de'" <rguenther@suse.de>,
"Kumar, Venkataramanan" <Venkataramanan.Kumar@amd.com>
Subject: Turnoff prefetching for -march=znver1
Date: Tue, 02 Feb 2016 20:28:00 -0000 [thread overview]
Message-ID: <DM2PR12MB0137C7D2468EE7E84186E27385DF0@DM2PR12MB0137.namprd12.prod.outlook.com> (raw)
[-- Attachment #1: Type: text/plain, Size: 294 bytes --]
Hi Maintainers,
This patch disables prefetching for -march=znver1 which is turned on by default.
gcc/ChangeLog:
2016-02-02 Victoria Stepanyan <victoria.stepanyan@amd.com>
* gcc/config/i386/x86-tune.def: Disable default prefetching for -march=znver1
Ok for trunk?
Victoria
[-- Attachment #2: turnoff_prefetch.patch.txt --]
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--- a/gcc/config/i386/x86-tune.def
+++ b/gcc/config/i386/x86-tune.def
@@ -218,7 +218,7 @@ DEF_TUNE (X86_TUNE_FOUR_JUMP_LIMIT, "four_jump_limit",
at -O3. For the moment, the prefetching seems badly tuned for Intel
chips. */
DEF_TUNE (X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL, "software_prefetching_beneficial",
- m_K6_GEODE | m_AMD_MULTIPLE)
+ m_K6_GEODE | m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
/* X86_TUNE_LCP_STALL: Avoid an expensive length-changing prefix stall
on 16-bit immediate moves into memory on Core2 and Corei7. */
next reply other threads:[~2016-02-02 20:28 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-02 20:28 Stepanyan, Victoria [this message]
2016-02-02 20:49 ` Uros Bizjak
2016-02-04 7:55 ` Kumar, Venkataramanan
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