From: "Kong, Lingling" <lingling.kong@intel.com>
To: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>
Cc: "Liu, Hongtao" <hongtao.liu@intel.com>,
Uros Bizjak <ubizjak@gmail.com>,
"Kong, Lingling" <lingling.kong@intel.com>
Subject: [PATCH 4/8] [APX NF] Support APX NF for right shift insns
Date: Wed, 15 May 2024 07:45:18 +0000 [thread overview]
Message-ID: <DM4PR11MB548747A96B976C325F5BD112ECEC2@DM4PR11MB5487.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20240515070226.3760873-4-lingling.kong@intel.com>
gcc/ChangeLog:
* config/i386/i386.md (*ashr<mode>3_1_nf): New.
(*lshr<mode>3_1_nf): Ditto.
(*lshrqi3_1_nf): Ditto.
(*lshrhi3_1_nf): Ditto.
---
gcc/config/i386/i386.md | 85 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 85 insertions(+)
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 9ffdb3fe71a..adcb09fcdd0 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -16569,6 +16569,21 @@
[(set_attr "type" "ishiftx")
(set_attr "mode" "<MODE>")])
+(define_insn "*ashr<mode>3_1_nf"
+ [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r,r")
+ (ashiftrt:SWI48
+ (match_operand:SWI48 1 "nonimmediate_operand" "0,rm,rm")
+ (match_operand:QI 2 "nonmemory_operand" "c<S>,r,c<S>")))]
+ "TARGET_APX_NF &&
+ ix86_binary_operator_ok (ASHIFTRT, <MODE>mode, operands, TARGET_APX_NDD)"
+ "@
+ %{nf%} sar{<imodesuffix>}\t{%2, %0|%0, %2}
+ #
+ %{nf%} sar{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "*,bmi2,apx_ndd")
+ (set_attr "type" "ishift,ishiftx,ishift")
+ (set_attr "mode" "<MODE>")])
+
(define_insn "*ashr<mode>3_1"
[(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r,r")
(ashiftrt:SWI48
@@ -16630,6 +16645,21 @@
}
[(set_attr "isa" "*,*,*,apx_ndd")])
+(define_insn "*lshr<mode>3_1_nf"
+ [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r,?k,r")
+ (lshiftrt:SWI48
+ (match_operand:SWI48 1 "nonimmediate_operand" "0,rm,k,rm")
+ (match_operand:QI 2 "nonmemory_operand" "c<S>,r,<KS>,c<S>")))]
+ "TARGET_APX_NF &&
+ ix86_binary_operator_ok (LSHIFTRT, <MODE>mode, operands, TARGET_APX_NDD)"
+ "@
+ %{nf%} shr{<imodesuffix>}\t{%2, %0|%0, %2}
+ #
+ #
+ %{nf%} shr{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "*,bmi2,avx512bw,apx_ndd")
+ (set_attr "type" "ishift,ishiftx,msklog,ishift")
+ (set_attr "mode" "<MODE>")])
(define_insn "*lshr<mode>3_1"
[(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r,?k,r") @@ -16669,6 +16699,17 @@
(set_attr "mode" "<MODE>")])
;; Convert shift to the shiftx pattern to avoid flags dependency.
+;; For NF/NDD doesn't support shift count as r, it just support c<S>,
+;; but it has no flag.
+(define_split
+ [(set (match_operand:SWI48 0 "register_operand")
+ (any_shiftrt:SWI48 (match_operand:SWI48 1 "nonimmediate_operand")
+ (match_operand:QI 2 "register_operand")))]
+ "TARGET_BMI2 && reload_completed"
+ [(set (match_dup 0)
+ (any_shiftrt:SWI48 (match_dup 1) (match_dup 2)))]
+ "operands[2] = gen_lowpart (<MODE>mode, operands[2]);")
+
(define_split
[(set (match_operand:SWI48 0 "register_operand")
(any_shiftrt:SWI48 (match_operand:SWI48 1 "nonimmediate_operand") @@ -16737,6 +16778,20 @@
(zero_extend:DI (any_shiftrt:SI (match_dup 1) (match_dup 2))))]
"operands[2] = gen_lowpart (SImode, operands[2]);")
+(define_insn "*ashr<mode>3_1_nf"
+ [(set (match_operand:SWI12 0 "nonimmediate_operand" "=<r>m, r")
+ (ashiftrt:SWI12
+ (match_operand:SWI12 1 "nonimmediate_operand" "0, rm")
+ (match_operand:QI 2 "nonmemory_operand" "c<S>, c<S>")))]
+ "TARGET_APX_NF &&
+ ix86_binary_operator_ok (ASHIFTRT, <MODE>mode, operands, TARGET_APX_NDD)"
+ "@
+ %{nf%} sar{<imodesuffix>}\t{%2, %0|%0, %2}
+ %{nf%} sar{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "*, apx_ndd")
+ (set_attr "type" "ishift")
+ (set_attr "mode" "<MODE>")])
+
(define_insn "*ashr<mode>3_1"
[(set (match_operand:SWI12 0 "nonimmediate_operand" "=<r>m, r")
(ashiftrt:SWI12
@@ -16765,6 +16820,21 @@
(const_string "*")))
(set_attr "mode" "<MODE>")])
+(define_insn "*lshrqi3_1_nf"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,?k,r")
+ (lshiftrt:QI
+ (match_operand:QI 1 "nonimmediate_operand" "0,k,rm")
+ (match_operand:QI 2 "nonmemory_operand" "cI,Wb,cI")))]
+ "TARGET_APX_NF &&
+ ix86_binary_operator_ok (LSHIFTRT, QImode, operands, TARGET_APX_NDD)"
+ "@
+ %{nf%} shr{b}\t{%2, %0|%0, %2}
+ #
+ %{nf%} shr{b}\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "*,avx512dq,apx_ndd")
+ (set_attr "type" "ishift,msklog,ishift")
+ (set_attr "mode" "QI")])
+
(define_insn "*lshrqi3_1"
[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,?k,r")
(lshiftrt:QI
@@ -16802,6 +16872,21 @@
(const_string "*")))
(set_attr "mode" "QI")])
+(define_insn "*lshrhi3_1_nf"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,?k,r")
+ (lshiftrt:HI
+ (match_operand:HI 1 "nonimmediate_operand" "0,k,rm")
+ (match_operand:QI 2 "nonmemory_operand" "cI,Ww,cI")))]
+ "TARGET_APX_NF &&
+ ix86_binary_operator_ok (LSHIFTRT, HImode, operands, TARGET_APX_NDD)"
+ "@
+ %{nf%} shr{w}\t{%2, %0|%0, %2}
+ #
+ %{nf%} shr{w}\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "*, avx512f, apx_ndd")
+ (set_attr "type" "ishift,msklog,ishift")
+ (set_attr "mode" "HI")])
+
(define_insn "*lshrhi3_1"
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm, ?k, r")
(lshiftrt:HI
--
2.31.1
next prev parent reply other threads:[~2024-05-15 7:45 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20240515070226.3760873-1-lingling.kong@intel.com>
2024-05-15 7:43 ` [PATCH 1/8] [APX NF]: Support APX NF add Kong, Lingling
2024-05-15 8:14 ` Uros Bizjak
2024-05-15 8:36 ` Kong, Lingling
2024-05-15 8:46 ` Uros Bizjak
2024-05-22 8:29 ` [PATCH v2 " Kong, Lingling
2024-05-22 8:35 ` Uros Bizjak
[not found] ` <20240515070226.3760873-2-lingling.kong@intel.com>
2024-05-15 7:44 ` [PATCH 2/8] [APX NF] Support APX NF for {sub/and/or/xor/neg} Kong, Lingling
[not found] ` <20240515070226.3760873-3-lingling.kong@intel.com>
2024-05-15 7:44 ` [PATCH 3/8] [APX NF] Support APX NF for left shift insns Kong, Lingling
[not found] ` <20240515070226.3760873-4-lingling.kong@intel.com>
2024-05-15 7:45 ` Kong, Lingling [this message]
[not found] ` <20240515070226.3760873-5-lingling.kong@intel.com>
2024-05-15 7:45 ` [PATCH 5/8] [APX NF] Support APX NF for rotate insns Kong, Lingling
[not found] ` <20240515070226.3760873-6-lingling.kong@intel.com>
2024-05-15 7:46 ` [PATCH 6/8] [APX NF] Support APX NF for shld/shrd Kong, Lingling
[not found] ` <20240515070226.3760873-7-lingling.kong@intel.com>
2024-05-15 7:46 ` [PATCH 7/8] [APX NF] Support APX NF for mul/div Kong, Lingling
[not found] ` <20240515070226.3760873-8-lingling.kong@intel.com>
2024-05-15 7:47 ` [PATCH 8/8] [APX NF] Support APX NF for lzcnt/tzcnt/popcnt Kong, Lingling
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