[PATCH 7/8] [APX NF] Support APX NF for mul/div

["Kong, Lingling" <lingling.kong@intel.com>]

gcc/ChangeLog:

	* config/i386/i386.md (*mul<mode>3_1_nf): New define_insn.
	(*mulqi3_1_nf): Ditto.
	(*<u>divmod<mode>4_noext_nf): Ditto.
	(<u>divmodhiqi3_nf): Ditto.
---
 gcc/config/i386/i386.md | 86 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 86 insertions(+)

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index f9a62fba0c4..55f65a31b16 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -9907,6 +9907,42 @@
 ;;
 ;; On BDVER1, all HI MULs use DoublePath
 
+(define_insn "*mul<mode>3_1_nf"
+  [(set (match_operand:SWIM248 0 "register_operand" "=r,r,r")
+	(mult:SWIM248
+	  (match_operand:SWIM248 1 "nonimmediate_operand" "%rm,rm,0")
+	  (match_operand:SWIM248 2 "<general_operand>" "K,<i>,<m>r")))]
+  "TARGET_APX_NF &&
+  !(MEM_P (operands[1]) && MEM_P (operands[2]))"
+  "@
+   %{nf%} imul{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}
+   %{nf%} imul{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}
+   %{nf%} imul{<imodesuffix>}\t{%2, %0|%0, %2}"
+  [(set_attr "type" "imul")
+   (set_attr "prefix_0f" "0,0,1")
+   (set (attr "athlon_decode")
+	(cond [(eq_attr "cpu" "athlon")
+		  (const_string "vector")
+	       (eq_attr "alternative" "1")
+		  (const_string "vector")
+	       (and (eq_attr "alternative" "2")
+	       	    (ior (match_test "<MODE>mode == HImode")
+		         (match_operand 1 "memory_operand")))
+		  (const_string "vector")]
+	      (const_string "direct")))
+   (set (attr "amdfam10_decode")
+	(cond [(and (eq_attr "alternative" "0,1")
+	      	    (ior (match_test "<MODE>mode == HImode")
+		         (match_operand 1 "memory_operand")))
+		  (const_string "vector")]
+	      (const_string "direct")))
+   (set (attr "bdver1_decode")
+   	(if_then_else
+	  (match_test "<MODE>mode == HImode")
+	    (const_string "double")
+	    (const_string "direct")))
+   (set_attr "mode" "<MODE>")])
+
 (define_insn "*mul<mode>3_1"
   [(set (match_operand:SWIM248 0 "register_operand" "=r,r,r")
 	(mult:SWIM248
@@ -9978,6 +10014,24 @@
 ;; MUL reg8 	Direct
 ;; MUL mem8 	Direct
 
+(define_insn "*mulqi3_1_nf"
+  [(set (match_operand:QI 0 "register_operand" "=a")
+	(mult:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
+		 (match_operand:QI 2 "nonimmediate_operand" "qm")))]
+  "TARGET_APX_NF &&
+  TARGET_QIMODE_MATH
+   && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
+  "%{nf%} mul{b}\t%2"
+  [(set_attr "type" "imul")
+   (set_attr "length_immediate" "0")
+   (set (attr "athlon_decode")
+     (if_then_else (eq_attr "cpu" "athlon")
+        (const_string "vector")
+        (const_string "direct")))
+   (set_attr "amdfam10_decode" "direct")
+   (set_attr "bdver1_decode" "direct")
+   (set_attr "mode" "QI")])
+
 (define_insn "*mulqi3_1"
   [(set (match_operand:QI 0 "register_operand" "=a")
 	(mult:QI (match_operand:QI 1 "nonimmediate_operand" "%0") @@ -11128,6 +11182,19 @@
   [(set_attr "type" "multi")
    (set_attr "mode" "SI")])
 
+(define_insn "*<u>divmod<mode>4_noext_nf"
+  [(set (match_operand:SWIM248 0 "register_operand" "=a")
+	(any_div:SWIM248
+	  (match_operand:SWIM248 2 "register_operand" "0")
+	  (match_operand:SWIM248 3 "nonimmediate_operand" "rm")))
+   (set (match_operand:SWIM248 1 "register_operand" "=d")
+	(<paired_mod>:SWIM248 (match_dup 2) (match_dup 3)))
+   (use (match_operand:SWIM248 4 "register_operand" "1"))]
+  "TARGET_APX_NF"
+  "%{nf%} <sgnprefix>div{<imodesuffix>}\t%3"
+  [(set_attr "type" "idiv")
+   (set_attr "mode" "<MODE>")])
+
 (define_insn "*<u>divmod<mode>4_noext"
   [(set (match_operand:SWIM248 0 "register_operand" "=a")
 	(any_div:SWIM248
@@ -11275,6 +11342,25 @@
 ;; Change div/mod to HImode and extend the second argument to HImode  ;; so that mode of div/mod matches with mode of arguments.  Otherwise  ;; combine may fail.
+(define_insn "<u>divmodhiqi3_nf"
+  [(set (match_operand:HI 0 "register_operand" "=a")
+	(ior:HI
+	  (ashift:HI
+	    (zero_extend:HI
+	      (truncate:QI
+		(mod:HI (match_operand:HI 1 "register_operand" "0")
+			(any_extend:HI
+			  (match_operand:QI 2 "nonimmediate_operand" "qm")))))
+	    (const_int 8))
+	  (zero_extend:HI
+	    (truncate:QI
+	      (div:HI (match_dup 1) (any_extend:HI (match_dup 2)))))))]
+  "TARGET_APX_NF
+  && TARGET_QIMODE_MATH"
+  "%{nf%} <sgnprefix>div{b}\t%2"
+  [(set_attr "type" "idiv")
+   (set_attr "mode" "QI")])
+
 (define_insn "<u>divmodhiqi3"
   [(set (match_operand:HI 0 "register_operand" "=a")
 	(ior:HI
--
2.31.1