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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM4PR11MB5487.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6e6c2009-af81-41b3-4c3e-08dc8f69f235 X-MS-Exchange-CrossTenant-originalarrivaltime: 18 Jun 2024 07:40:37.7228 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 71AJuesXJ4DO0/NUPFT675f4KlLOnWzYk5XHb4gkQW9cLK188t+jZWl46MShtJ6iDogUC6hb3yCxF4HzSmoALQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR11MB5133 X-OriginatorOrg: intel.com X-Spam-Status: No, score=-13.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: gcc/ChangeLog: * config/i386/i386-expand.cc (ix86_can_cfcmov_p): New function that test if the cfcmov can be generated. (ix86_expand_int_movcc): Expand to cfcmov pattern if ix86_can_cfcmov_p return ture. * config/i386/i386-opts.h (enum apx_features): Add apx_cfcmov. * config/i386/i386.cc (ix86_have_conditional_move_mem_notrap): New function to hook TARGET_HAVE_CONDITIONAL_MOVE_MEM_NOTRAP (TARGET_HAVE_CONDITIONAL_MOVE_MEM_NOTRAP): Target hook define. (ix86_rtx_costs): Add UNSPEC_APX_CFCMOV cost; * config/i386/i386.h (TARGET_APX_CFCMOV): Define. * config/i386/i386.md (cfmovcc): New define_insn to support cfcmov. (cfmovcc_2): Ditto. (UNSPEC_APX_CFCMOV): New unspec for cfcmov. * config/i386/i386.opt: Add enum value for cfcmov. * config/i386/predicates.md (register_or_cfc_mem_operand): New define_predicate. gcc/testsuite/ChangeLog: * gcc.target/i386/apx-cfcmov-1.c: New test. * gcc.target/i386/apx-cfcmov-2.c: Ditto. --- gcc/config/i386/i386-expand.cc | 63 +++++++++++++++++ gcc/config/i386/i386-opts.h | 4 +- gcc/config/i386/i386.cc | 16 +++-- gcc/config/i386/i386.h | 1 + gcc/config/i386/i386.md | 53 ++++++++++++-- gcc/config/i386/i386.opt | 3 + gcc/config/i386/predicates.md | 7 ++ gcc/testsuite/gcc.target/i386/apx-cfcmov-1.c | 73 ++++++++++++++++++++ gcc/testsuite/gcc.target/i386/apx-cfcmov-2.c | 40 +++++++++++ 9 files changed, 248 insertions(+), 12 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/apx-cfcmov-1.c create mode 100644 gcc/testsuite/gcc.target/i386/apx-cfcmov-2.c diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.c= c index 312329e550b..c02a4bcbec3 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -3336,6 +3336,30 @@ ix86_expand_int_addcc (rtx operands[]) return true; } =20 +/* Return TRUE if we could convert "if (test) x =3D a; else x =3D b;" to c= fcmov, + especially when load a or b or x store may cause memmory faults. */ +bool +ix86_can_cfcmov_p (rtx x, rtx a, rtx b) +{ + machine_mode mode =3D GET_MODE (x); + if (TARGET_APX_CFCMOV + && (mode =3D=3D DImode || mode =3D=3D SImode || mode =3D=3D HImode)) + { + /* C load (r m r), (r m C), (r r m). For r m m could use + two cfcmov. */ + if (register_operand (x, mode) + && ((MEM_P (a) && register_operand (b, mode)) + || (MEM_P (a) && b =3D=3D const0_rtx) + || (register_operand (a, mode) && MEM_P (b)) + || (MEM_P (a) && MEM_P (b)))) + return true; + /* C store (m r 0). */ + else if (MEM_P (x) && x =3D=3D b && register_operand (a, mode)) + return true; + } + return false; +} + bool ix86_expand_int_movcc (rtx operands[]) { @@ -3366,6 +3390,45 @@ ix86_expand_int_movcc (rtx operands[]) =20 compare_code =3D GET_CODE (compare_op); =20 + if (MEM_P (operands[0]) + && !ix86_can_cfcmov_p (operands[0], op2, op3)) + return false; + + if (may_trap_or_fault_p (op2) || may_trap_or_fault_p (op3)) + { + if (ix86_can_cfcmov_p (operands[0], op2, op3)) + { + if (may_trap_or_fault_p (op2)) + op2 =3D gen_rtx_UNSPEC (mode, gen_rtvec (1, operands[2]), + UNSPEC_APX_CFCMOV); + if (may_trap_or_fault_p (op3)) + op3 =3D gen_rtx_UNSPEC (mode, gen_rtvec (1, operands[3]), + UNSPEC_APX_CFCMOV); + emit_insn (compare_seq); + + if (may_trap_or_fault_p (op2) && may_trap_or_fault_p (op3)) + { + emit_insn (gen_rtx_SET (operands[0], + gen_rtx_IF_THEN_ELSE (mode, + compare_op, + op2, + operands[0]))); + emit_insn (gen_rtx_SET (operands[0], + gen_rtx_IF_THEN_ELSE (mode, + compare_op, + operands[0], + op3))); + } + else + emit_insn (gen_rtx_SET (operands[0], + gen_rtx_IF_THEN_ELSE (mode, + compare_op, + op2, op3))); + return true; + } + return false; + } + if ((op1 =3D=3D const0_rtx && (code =3D=3D GE || code =3D=3D LT)) || (op1 =3D=3D constm1_rtx && (code =3D=3D GT || code =3D=3D LE))) sign_bit_compare_p =3D true; diff --git a/gcc/config/i386/i386-opts.h b/gcc/config/i386/i386-opts.h index c7ec0d9fd39..711519ffb53 100644 --- a/gcc/config/i386/i386-opts.h +++ b/gcc/config/i386/i386-opts.h @@ -143,8 +143,10 @@ enum apx_features { apx_nf =3D 1 << 4, apx_ccmp =3D 1 << 5, apx_zu =3D 1 << 6, + apx_cfcmov =3D 1 << 7, apx_all =3D apx_egpr | apx_push2pop2 | apx_ndd - | apx_ppx | apx_nf | apx_ccmp | apx_zu, + | apx_ppx | apx_nf | apx_ccmp | apx_zu + | apx_cfcmov, }; =20 #endif diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index 173db213d14..4d9eb272e4a 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -22349,10 +22349,18 @@ ix86_rtx_costs (rtx x, machine_mode mode, int out= er_code_i, int opno, *total =3D COSTS_N_INSNS (1); if (!COMPARISON_P (XEXP (x, 0)) && !REG_P (XEXP (x, 0))) *total +=3D rtx_cost (XEXP (x, 0), mode, code, 0, speed); - if (!REG_P (XEXP (x, 1))) - *total +=3D rtx_cost (XEXP (x, 1), mode, code, 1, speed); - if (!REG_P (XEXP (x, 2))) - *total +=3D rtx_cost (XEXP (x, 2), mode, code, 2, speed); + rtx op1, op2; + op1 =3D XEXP (x, 1); + op2 =3D XEXP (x, 2); + /* Handle UNSPEC_APX_CFCMOV for cfcmov. */ + if (GET_CODE (op1) =3D=3D UNSPEC && XINT (op1, 1) =3D=3D UNSPEC_APX_CFC= MOV) + op1 =3D XVECEXP (op1, 0, 0); + if (GET_CODE (op2) =3D=3D UNSPEC && XINT (op2, 1) =3D=3D UNSPEC_APX_CFC= MOV) + op2 =3D XVECEXP (op2, 0, 0); + if (!REG_P (op1)) + *total +=3D rtx_cost (op1, mode, code, 1, speed); + if (!REG_P (op2)) + *total +=3D rtx_cost (op2, mode, code, 2, speed); return true; } return false; diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index dc1a1f44320..6a20fa678c8 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -58,6 +58,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. = If not, see #define TARGET_APX_NF (ix86_apx_features & apx_nf) #define TARGET_APX_CCMP (ix86_apx_features & apx_ccmp) #define TARGET_APX_ZU (ix86_apx_features & apx_zu) +#define TARGET_APX_CFCMOV (ix86_apx_features & apx_cfcmov) =20 #include "config/vxworks-dummy.h" =20 diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index fd48e764469..c20d85703ad 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -221,6 +221,9 @@ ;; For APX CCMP support ;; DFV =3D default flag value UNSPEC_APX_DFV + + ;; For APX CFCMOV support + UNSPEC_APX_CFCMOV ]) =20 (define_c_enum "unspecv" [ @@ -579,7 +582,7 @@ noavx512dq,fma_or_avx512vl,avx512vl,noavx512vl,avxvnni, avx512vnnivl,avx512fp16,avxifma,avx512ifmavl,avxneconvert, avx512bf16vl,vpclmulqdqvl,avx_noavx512f,avx_noavx512vl, - vaes_avx512vl,noapx_nf" + vaes_avx512vl,noapx_nf,apx_cfcmov" (const_string "base")) =20 ;; The (bounding maximum) length of an instruction immediate. @@ -986,6 +989,7 @@ (eq_attr "mmx_isa" "avx") (symbol_ref "TARGET_MMX_WITH_SSE && TARGET_AVX") (eq_attr "isa" "noapx_nf") (symbol_ref "!TARGET_APX_NF") + (eq_attr "isa" "apx_cfcmov") (symbol_ref "TARGET_APX_CFCMOV") ] (const_int 1))) =20 @@ -24995,7 +24999,7 @@ ;; Conditional move instructions. =20 (define_expand "movcc" - [(set (match_operand:SWIM 0 "register_operand") + [(set (match_operand:SWIM 0 "register_or_cfc_mem_operand") (if_then_else:SWIM (match_operand 1 "comparison_operator") (match_operand:SWIM 2 "") (match_operand:SWIM 3 "")))] @@ -25103,19 +25107,54 @@ (set (match_dup 0) (neg:SWI (ltu:SWI (reg:CCC FLAGS_REG) (const_int 0))))]) =20 +(define_insn "cfmovcc" + [(set (match_operand:SWI248 0 "register_operand" "=3Dr,r") + (if_then_else:SWI248 (match_operator 1 "ix86_comparison_operator" + [(reg FLAGS_REG) (const_int 0)]) + (unspec:SWI248 + [(match_operand:SWI248 2 "memory_operand" "m,m")] + UNSPEC_APX_CFCMOV) + (match_operand:SWI248 3 "reg_or_0_operand" "C,r")))] + "TARGET_CMOVE && TARGET_APX_CFCMOV" + "@ + cfcmov%O2%C1\t{%2, %0|%0, %2} + cfcmov%O2%C1\t{%2, %3, %0|%0, %3, %2}" + [(set_attr "isa" "*,apx_ndd") + (set_attr "type" "icmov") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_insn "cfmovcc_2" + [(set (match_operand:SWI248 0 "nonimmediate_operand" "=3Dr,m") + (if_then_else:SWI248 (match_operator 1 "ix86_comparison_operator" + [(reg FLAGS_REG) (const_int 0)]) + (match_operand:SWI248 2 "register_operand" "r,r") + (unspec:SWI248 + [(match_operand:SWI248 3 "memory_operand" "m,0")] + UNSPEC_APX_CFCMOV)))] + "TARGET_CMOVE && TARGET_APX_CFCMOV" + "@ + cfcmov%O2%c1\t{%3, %2, %0|%0, %2, %3} + cfcmov%O2%C1\t{%2, %0|%0, %2}" + [(set_attr "isa" "apx_ndd,*") + (set_attr "type" "icmov") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + (define_insn "*movcc_noc" - [(set (match_operand:SWI248 0 "register_operand" "=3Dr,r,r,r") + [(set (match_operand:SWI248 0 "register_operand" "=3Dr,r,r,r,r") (if_then_else:SWI248 (match_operator 1 "ix86_comparison_operator" [(reg FLAGS_REG) (const_int 0)]) - (match_operand:SWI248 2 "nonimmediate_operand" "rm,0,rm,r") - (match_operand:SWI248 3 "nonimmediate_operand" "0,rm,r,rm")))] + (match_operand:SWI248 2 "nonimmediate_operand" "rm,0,rm,r,r") + (match_operand:SWI248 3 "nonimm_or_0_operand" "0,rm,r,rm,C")))] "TARGET_CMOVE && !(MEM_P (operands[2]) && MEM_P (operands[3]))" "@ cmov%O2%C1\t{%2, %0|%0, %2} cmov%O2%c1\t{%3, %0|%0, %3} cmov%O2%C1\t{%2, %3, %0|%0, %3, %2} - cmov%O2%c1\t{%3, %2, %0|%0, %2, %3}" - [(set_attr "isa" "*,*,apx_ndd,apx_ndd") + cmov%O2%c1\t{%3, %2, %0|%0, %2, %3} + cfcmov%O2%C1\t{%2, %0|%0, %2}" + [(set_attr "isa" "*,*,apx_ndd,apx_ndd,apx_cfcmov") (set_attr "type" "icmov") (set_attr "mode" "")]) =20 diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index 353fffb2343..7d63d9abd95 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -1345,6 +1345,9 @@ Enum(apx_features) String(ccmp) Value(apx_ccmp) Set(7= ) EnumValue Enum(apx_features) String(zu) Value(apx_zu) Set(8) =20 +EnumValue +Enum(apx_features) String(cfcmov) Value(apx_cfcmov) Set(9) + EnumValue Enum(apx_features) String(all) Value(apx_all) Set(1) =20 diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index 7afe3100cb7..d562e10ab41 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -2322,3 +2322,10 @@ =20 return true; }) + +;; Return true if OP is a register operand or memory_operand is only +;; supported under TARGET_APX_CFCMOV. +(define_predicate "register_or_cfc_mem_operand" + (ior (match_operand 0 "register_operand") + (and (match_code "mem") + (match_test "TARGET_APX_CFCMOV")))) diff --git a/gcc/testsuite/gcc.target/i386/apx-cfcmov-1.c b/gcc/testsuite/g= cc.target/i386/apx-cfcmov-1.c new file mode 100644 index 00000000000..4a1fb91b24c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/apx-cfcmov-1.c @@ -0,0 +1,73 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O3 -mapxf" } */ + +/* { dg-final { scan-assembler-times "cfcmovne" 1 } } */ +/* { dg-final { scan-assembler-times "cfcmovg" 2} } */ +/* { dg-final { scan-assembler-times "cfcmove" 1 } } */ +/* { dg-final { scan-assembler-times "cfcmovl" 2 } } */ +/* { dg-final { scan-assembler-times "cfcmovle" 1 } } */ + +__attribute__((noinline, noclone, target("apxf"))) +int cfc_store (int a, int b, int c, int d, int *arr) +{ + if (a !=3D b) + *arr =3D c; + return d; + +} + +__attribute__((noinline, noclone, target("apxf"))) +int cfc_load_ndd (int a, int b, int c, int *p) +{ + if (a > b) + return *p; + return c; +} + +__attribute__((noinline, noclone, target("apxf"))) +int cfc_load_2_trap (int a, int b, int *c, int *p) +{ + if (a > b) + return *p; + return *c; +} + +__attribute__((noinline, noclone, target("apxf"))) +int cfc_load_zero (int a, int b, int c) +{ + int sum =3D 0; + if (a =3D=3D b) + return c; + return sum; +} + +__attribute__((noinline, noclone, target("apxf"))) +int cfc_load_mem (int a, int b, int *p) +{ + int sum =3D 0; + if (a < b ) + sum =3D *p; + return sum; +} + +__attribute__((noinline, noclone, target("apxf"))) +int cfc_load_arith_1 (int a, int b, int c, int *p) +{ + int sum =3D 0; + if (a > b) + sum =3D *p; + else + sum =3D a + c; + return sum + 1; +} + +__attribute__((noinline, noclone, target("apxf"))) +int cfc_load_arith_2 (int a, int b, int c, int *p) +{ + int sum =3D 0; + if (a > b) + sum =3D a + c; + else + sum =3D *p; + return sum + 1; +} diff --git a/gcc/testsuite/gcc.target/i386/apx-cfcmov-2.c b/gcc/testsuite/g= cc.target/i386/apx-cfcmov-2.c new file mode 100644 index 00000000000..2b1660f64fa --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/apx-cfcmov-2.c @@ -0,0 +1,40 @@ +/* { dg-do run { target { ! ia32 } } } */ +/* { dg-require-effective-target apxf } */ +/* { dg-options "-mapxf -march=3Dx86-64 -O3" } */ + +#include "apx-cfcmov-1.c" + +extern void abort (void); + +int main () +{ + if (!__builtin_cpu_supports ("apxf")) + return 0; + + int arr =3D 6; + int arr1 =3D 5; + int res =3D cfc_store (1, 2, 3, 4, &arr); + if (arr !=3D 3 && res !=3D 4) + abort (); + res =3D cfc_load_ndd (2, 1, 2, &arr); + if (res !=3D 3) + abort (); + res =3D cfc_load_2_trap (1, 2, &arr1, &arr); + if (res !=3D 5) + abort (); + res =3D cfc_load_zero (1, 2, 3); + res =3D cfc_load_zero (1, 2, 3); + if (res !=3D 0) + abort (); + res =3D cfc_load_mem (2, 1, &arr); + if (res !=3D 0) + abort (); + res =3D cfc_load_arith_1 (1, 2, 3, &arr); + if (res !=3D 5) + abort(); + res =3D cfc_load_arith_2 (2, 1, 3,&arr); + if (res !=3D 6) + abort(); + return 0; +} + --=20 2.31.1 =20