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charset="us-ascii" Content-ID: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Dell.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DS7PR19MB4501.namprd19.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7eba4f16-6a0e-483f-50c9-08daae0256b1 X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Oct 2022 16:37:09.3818 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 945c199a-83a2-4e80-9f8c-5a91be5752dd X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Up5xIYM3F9BwkT7lXU1hSO3+89rpBmLR7LPDQYuwszZeNAF6+YC5VDsyJPsJJqDkqRGsz3SNF975ttwOXr9tXA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR19MB5617 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-14_09,2022-10-14_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 spamscore=0 phishscore=0 priorityscore=1501 adultscore=0 mlxlogscore=999 lowpriorityscore=0 bulkscore=0 mlxscore=0 suspectscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2210140092 X-Proofpoint-GUID: _jS6HHgofiJlFakC5HjdoX7ptLF9Ik56 X-Proofpoint-ORIG-GUID: _jS6HHgofiJlFakC5HjdoX7ptLF9Ik56 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 malwarescore=0 phishscore=0 bulkscore=0 mlxlogscore=999 spamscore=0 suspectscore=0 mlxscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2210140092 X-Spam-Status: No, score=-2.9 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: > On Oct 14, 2022, at 10:38 AM, Jeff Law via Gcc-patches wrote: >=20 >=20 > On 10/14/22 06:37, Koning, Paul wrote: >>=20 >>> On Oct 13, 2022, at 9:07 PM, Jeff Law via Gcc-patches wrote: >>>=20 >>>=20 >>> On 10/13/22 17:56, Segher Boessenkool wrote: >>>> h8300 fails during GCC build: >>>> /home/segher/src/gcc/libgcc/unwind.inc: In function '_Unwind_SjLj_Rais= eException': >>>> /home/segher/src/gcc/libgcc/unwind.inc:141:1: error: could not split i= nsn >>>> 141 | } >>>> | ^ >>>> (insn 69 256 327 (set (mem/f:SI (pre_dec:SI (reg/f:SI 7 sp)) [12 S4 A= 32]) >>>> (reg/f:SI 7 sp)) "/home/segher/src/gcc/libgcc/unwind.inc":118:= 12 19 {*movsi} >>>> (expr_list:REG_ARGS_SIZE (const_int 4 [0x4]) >>>> (nil))) >>>> during RTL pass: final >>>> which looks like a backend bug, I don't see a pattern that could split >>>> this (without needing an extra clobber)? >>> I'm aware of this -- its invalid RTL: >>>=20 >>> Uses of the register outside of an address are not permitted within the >>> same insn as a use in an embedded side effect expression because such >>> insns behave differently on different machines and hence must be treate= d >>> as ambiguous and disallowed. >> I had a bit of a fight with this sort of thing in pdp11, where in fact s= uch operations are executed differently on different machine models. The s= olution I picked is to create two sets of machine-specific constraint codes= , one for "register N" and the other for "autoinc/dec of any register other= than N" and pairing those. (You can see this in pdp11.md, the mov d= efinition.) >=20 > I've long suspected the pdp11 was the inspiration for this restriction (I= have memories of noting it before I relocated to Utah, so circa 1992). Th= e key problem is the generic parts of the compiler don't know what the sema= ntics ought to be -- so it's not obvious when they do a substitution whethe= r or not the substitution of one reg for another is actually valid. It's i= mportant to remember that sometimes when we substitute one register for ano= ther, we don't have any contextual information about source vs dest -- it's= a long standing wart that causes problems in other cases as well. >=20 > That punts the problem to the backends and the H8 actually tries to deal = with this restriction. Basically in the movxx pattern conditions, when the= destination uses an autoinc addressing mode, the pattern's condition will = check that the source register is different. I would expect other ports li= kely to do something similar. >=20 > But that approach falls down with reload/lra doing substitutions without = validating the result. I guess it might be possible to cobble together som= ething with secondary reloads, but it's way way way down on my todo list. Aren't the constraints enforced? My experience is that I was getting these= bad addressing modes in some test programs, and that the constraints I cre= ated to make the requirement explicit cured that. Maybe I'm expecting too = much from constraints, but my (admittedly inexperienced) understanding of t= hem is that they inform reload what sort of things it can construct, and wh= at it cannot. If reload obeys the constraints in the patterns then the back end machine d= efinition can be written to avoid the problematic cases, and it is no longe= r necessary to have a general (and as I pointed out, overly broad) rule in = generic code. paul