Re: [PATCH 2/3] RISC-V: Part-2: Save/Restore vector registers which need to be preversed

["Lehua Ding" <lehua.ding@rivai.ai>]

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Hi Kito,

> > +machine_mode m1_mode = TARGET_VECTOR_ELEN_64
> > +? (TARGET_MIN_VLEN >= 128 ? VNx2DImode : VNx1DImode) 
> > +: VNx1SImode;

> This should update since JuZhe has update the mode system :P

Yes, thanks reminder.

> > @@ -5907,7 +6057,7 @@ riscv_expand_epilogue (int style) 
> > Start off by assuming that no registers need to be restored.*/ 
> >struct riscv_frame_info *frame = &cfun->machine->frame; 
> >unsigned mask = frame->mask; 
> > -HOST_WIDE_INT step2 = 0; 
> > +poly_int64 step2 = 0; 

> I saw we check `step2.to_constant () 
> 0` later, does it mean step2 is 
> always a scalar rather than a poly number? 
> If so, I would suggest keeping HOST_WIDE_INT if possible.
step2 will be reduced by `riscv_for_each_saved_v_reg (step2, riscv_restore_reg, false);`
before `step2.to_constant () > 0`. After `riscv_for_each_saved_v_reg`,
the step2 must be a constant. So step2 may be a poly number if there are any
length agnostic vector registers that need to be saved.

Best,
Lehua