From: "juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai>
To: 丁乐华 <lehua.ding@rivai.ai>, gcc-patches <gcc-patches@gcc.gnu.org>
Cc: "kito.cheng" <kito.cheng@gmail.com>,
"Robin Dapp" <rdapp.gcc@gmail.com>, palmer <palmer@rivosinc.com>,
jeffreyalaw <jeffreyalaw@gmail.com>, 丁乐华 <lehua.ding@rivai.ai>
Subject: Re: [PATCH V2 04/14] RISC-V: P4: move method from pass_vsetvl to pre_vsetvl
Date: Wed, 18 Oct 2023 12:02:24 +0800 [thread overview]
Message-ID: <ED834EBAA2A1CD38+2023101812022378862558@rivai.ai> (raw)
In-Reply-To: <20231017113500.1160997-5-lehua.ding@rivai.ai>
[-- Attachment #1: Type: text/plain, Size: 8930 bytes --]
LGMT this patch.
juzhe.zhong@rivai.ai
From: Lehua Ding
Date: 2023-10-17 19:34
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH V2 04/14] RISC-V: P4: move method from pass_vsetvl to pre_vsetvl
This sub-patch remove the method about optimize vsetvl infos into
class pre_vsetvl.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (pass_vsetvl::get_vector_info): Removed.
(pass_vsetvl::get_block_info): Removed.
(pass_vsetvl::update_vector_info): Removed.
(pass_vsetvl::update_block_info): Removed.
(pass_vsetvl::simple_vsetvl): Removed.
(pass_vsetvl::lazy_vsetvl): Removed.
(pass_vsetvl::execute): Removed.
(make_pass_vsetvl): Removed.
---
gcc/config/riscv/riscv-vsetvl.cc | 228 ++++++++++++-------------------
1 file changed, 87 insertions(+), 141 deletions(-)
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index c219ad178bb..3f07fde782f 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -2684,54 +2684,8 @@ const pass_data pass_data_vsetvl = {
class pass_vsetvl : public rtl_opt_pass
{
private:
- vector_infos_manager *m_vector_manager;
-
- const vector_insn_info &get_vector_info (const rtx_insn *) const;
- const vector_insn_info &get_vector_info (const insn_info *) const;
- const vector_block_info &get_block_info (const basic_block) const;
- const vector_block_info &get_block_info (const bb_info *) const;
- vector_block_info &get_block_info (const basic_block);
- vector_block_info &get_block_info (const bb_info *);
- void update_vector_info (const insn_info *, const vector_insn_info &);
- void update_block_info (int, profile_probability, const vector_insn_info &);
-
- void simple_vsetvl (void) const;
- void lazy_vsetvl (void);
-
- /* Phase 1. */
- void compute_local_backward_infos (const bb_info *);
-
- /* Phase 2. */
- bool need_vsetvl (const vector_insn_info &, const vector_insn_info &) const;
- void transfer_before (vector_insn_info &, insn_info *) const;
- void transfer_after (vector_insn_info &, insn_info *) const;
- void emit_local_forward_vsetvls (const bb_info *);
-
- /* Phase 3. */
- bool earliest_fusion (void);
- void vsetvl_fusion (void);
-
- /* Phase 4. */
- void prune_expressions (void);
- void compute_local_properties (void);
- bool can_refine_vsetvl_p (const basic_block, const vector_insn_info &) const;
- void refine_vsetvls (void) const;
- void cleanup_vsetvls (void);
- bool commit_vsetvls (void);
- void pre_vsetvl (void);
-
- /* Phase 5. */
- rtx_insn *get_vsetvl_at_end (const bb_info *, vector_insn_info *) const;
- void local_eliminate_vsetvl_insn (const bb_info *) const;
- bool global_eliminate_vsetvl_insn (const bb_info *) const;
- void ssa_post_optimization (void) const;
-
- /* Phase 6. */
- void df_post_optimization (void) const;
-
- void init (void);
- void done (void);
- void compute_probabilities (void);
+ void simple_vsetvl ();
+ void lazy_vsetvl ();
public:
pass_vsetvl (gcc::context *ctxt) : rtl_opt_pass (pass_data_vsetvl, ctxt) {}
@@ -2741,69 +2695,11 @@ public:
virtual unsigned int execute (function *) final override;
}; // class pass_vsetvl
-const vector_insn_info &
-pass_vsetvl::get_vector_info (const rtx_insn *i) const
-{
- return m_vector_manager->vector_insn_infos[INSN_UID (i)];
-}
-
-const vector_insn_info &
-pass_vsetvl::get_vector_info (const insn_info *i) const
-{
- return m_vector_manager->vector_insn_infos[i->uid ()];
-}
-
-const vector_block_info &
-pass_vsetvl::get_block_info (const basic_block bb) const
-{
- return m_vector_manager->vector_block_infos[bb->index];
-}
-
-const vector_block_info &
-pass_vsetvl::get_block_info (const bb_info *bb) const
-{
- return m_vector_manager->vector_block_infos[bb->index ()];
-}
-
-vector_block_info &
-pass_vsetvl::get_block_info (const basic_block bb)
-{
- return m_vector_manager->vector_block_infos[bb->index];
-}
-
-vector_block_info &
-pass_vsetvl::get_block_info (const bb_info *bb)
-{
- return m_vector_manager->vector_block_infos[bb->index ()];
-}
-
-void
-pass_vsetvl::update_vector_info (const insn_info *i,
- const vector_insn_info &new_info)
-{
- m_vector_manager->vector_insn_infos[i->uid ()] = new_info;
-}
-
void
-pass_vsetvl::update_block_info (int index, profile_probability prob,
- const vector_insn_info &new_info)
-{
- m_vector_manager->vector_block_infos[index].probability = prob;
- if (m_vector_manager->vector_block_infos[index].local_dem
- == m_vector_manager->vector_block_infos[index].reaching_out)
- m_vector_manager->vector_block_infos[index].local_dem = new_info;
- m_vector_manager->vector_block_infos[index].reaching_out = new_info;
-}
-
-/* Simple m_vsetvl_insert vsetvl for optimize == 0. */
-void
-pass_vsetvl::simple_vsetvl (void) const
+pass_vsetvl::simple_vsetvl ()
{
if (dump_file)
- fprintf (dump_file,
- "\nEntering Simple VSETVL PASS and Handling %d basic blocks for "
- "function:%s\n",
- n_basic_blocks_for_fn (cfun), function_name (cfun));
+ fprintf (dump_file, "\nEntering Simple VSETVL PASS\n");
basic_block cfg_bb;
rtx_insn *rinsn;
@@ -2815,7 +2711,7 @@ pass_vsetvl::simple_vsetvl (void) const
continue;
if (has_vtype_op (rinsn))
{
- const auto info = get_vector_info (rinsn);
+ const auto info = vsetvl_info (rinsn);
emit_vsetvl_insn (VSETVL_DISCARD_RESULT, EMIT_BEFORE, info,
NULL_RTX, rinsn);
}
@@ -2823,6 +2719,88 @@ pass_vsetvl::simple_vsetvl (void) const
}
}
+/* Lazy vsetvl insertion for optimize > 0. */
+void
+pass_vsetvl::lazy_vsetvl ()
+{
+ if (dump_file)
+ fprintf (dump_file, "\nEntering Lazy VSETVL PASS\n\n");
+
+ pre_vsetvl pre = pre_vsetvl ();
+
+ if (dump_file)
+ fprintf (dump_file, "\nPhase 1: Fuse local vsetvl infos.\n\n");
+ pre.fuse_local_vsetvl_info ();
+ if (dump_file && (dump_flags & TDF_DETAILS))
+ pre.dump (dump_file, "phase 1");
+
+ /* Phase 2: Fuse header and footer vsetvl infos between basic blocks. */
+ if (dump_file)
+ fprintf (dump_file, "\nPhase 2: Lift up vsetvl info.\n\n");
+ bool changed;
+ int fused_count = 0;
+ do
+ {
+ if (dump_file)
+ fprintf (dump_file, " Try lift up %d.\n\n", fused_count);
+ changed = pre.earliest_fuse_vsetvl_info ();
+ fused_count += 1;
+ } while (changed);
+
+ if (dump_file && (dump_flags & TDF_DETAILS))
+ pre.dump (dump_file, "phase 2");
+
+ /* Phase 3: Reducing redundant vsetvl infos using LCM. */
+ if (dump_file)
+ fprintf (dump_file, "\nPhase 3: Reduce global vsetvl infos.\n\n");
+ pre.pre_global_vsetvl_info ();
+ if (dump_file && (dump_flags & TDF_DETAILS))
+ pre.dump (dump_file, "phase 3");
+
+ /* Phase 4: Insert, modify and remove vsetvl insns. */
+ if (dump_file)
+ fprintf (dump_file,
+ "\nPhase 4: Insert, modify and remove vsetvl insns.\n\n");
+ pre.emit_vsetvl ();
+
+ /* Phase 5: Cleaup */
+ if (dump_file)
+ fprintf (dump_file, "\nPhase 5: Cleaup\n\n");
+ pre.cleaup ();
+
+ pre.finish ();
+}
+
+/* Main entry point for this pass. */
+unsigned int
+pass_vsetvl::execute (function *)
+{
+ if (n_basic_blocks_for_fn (cfun) <= 0)
+ return 0;
+
+ /* The RVV instruction may change after split which is not a stable
+ instruction. We need to split it here to avoid potential issue
+ since the VSETVL PASS is insert before split PASS. */
+ split_all_insns ();
+
+ /* Early return for there is no vector instructions. */
+ if (!has_vector_insn (cfun))
+ return 0;
+
+ if (!optimize)
+ simple_vsetvl ();
+ else
+ lazy_vsetvl ();
+
+ return 0;
+}
+
+rtl_opt_pass *
+make_pass_vsetvl (gcc::context *ctxt)
+{
+ return new pass_vsetvl (ctxt);
+}
+
/* Compute demanded information by backward data-flow analysis. */
void
pass_vsetvl::compute_local_backward_infos (const bb_info *bb)
@@ -4253,35 +4231,3 @@ pass_vsetvl::lazy_vsetvl (void)
df_post_optimization ();
}
-/* Main entry point for this pass. */
-unsigned int
-pass_vsetvl::execute (function *)
-{
- if (n_basic_blocks_for_fn (cfun) <= 0)
- return 0;
-
- /* The RVV instruction may change after split which is not a stable
- instruction. We need to split it here to avoid potential issue
- since the VSETVL PASS is insert before split PASS. */
- split_all_insns ();
-
- /* Early return for there is no vector instructions. */
- if (!has_vector_insn (cfun))
- return 0;
-
- init ();
-
- if (!optimize)
- simple_vsetvl ();
- else
- lazy_vsetvl ();
-
- done ();
- return 0;
-}
-
-rtl_opt_pass *
-make_pass_vsetvl (gcc::context *ctxt)
-{
- return new pass_vsetvl (ctxt);
-}
--
2.36.3
next prev parent reply other threads:[~2023-10-18 4:02 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-17 11:34 [PATCH V2 00/14] Refactor and cleanup vsetvl pass Lehua Ding
2023-10-17 11:34 ` [PATCH V2 01/14] RISC-V: P1: Refactor avl_info/vl_vtype_info/vector_insn_info Lehua Ding
2023-10-17 12:32 ` juzhe.zhong
2023-10-17 15:23 ` 钟居哲
2023-10-18 2:30 ` juzhe.zhong
2023-10-17 11:34 ` [PATCH V2 02/14] RISC-V: P2: Refactor and cleanup demand system Lehua Ding
2023-10-18 3:43 ` juzhe.zhong
2023-10-17 11:34 ` [PATCH V2 03/14] RISC-V: P3: Refactor vector_infos_manager Lehua Ding
2023-10-18 3:58 ` juzhe.zhong
2023-10-17 11:34 ` [PATCH V2 04/14] RISC-V: P4: move method from pass_vsetvl to pre_vsetvl Lehua Ding
2023-10-18 4:02 ` juzhe.zhong [this message]
2023-10-17 11:34 ` [PATCH V2 05/14] RISC-V: P5: combine phase 1 and 2 Lehua Ding
2023-10-18 4:07 ` juzhe.zhong
2023-10-17 11:34 ` [PATCH V2 06/14] RISC-V: P6: Add computing reaching definition data flow Lehua Ding
2023-10-18 4:12 ` juzhe.zhong
2023-10-18 4:13 ` juzhe.zhong
2023-10-17 11:34 ` [PATCH V2 07/14] RISC-V: P7: Move earliest fuse and lcm code to pre_vsetvl class Lehua Ding
2023-10-18 4:14 ` juzhe.zhong
2023-10-17 11:34 ` [PATCH V2 08/14] RISC-V: P8: Unified insert and delete of vsetvl insn into Phase 4 Lehua Ding
2023-10-18 4:15 ` juzhe.zhong
2023-10-17 11:34 ` [PATCH V2 09/14] RISC-V: P9: Cleanup post optimize phase Lehua Ding
2023-10-18 4:15 ` juzhe.zhong
2023-10-17 11:34 ` [PATCH V2 10/14] RISC-V: P10: Cleanup helper functions Lehua Ding
2023-10-18 4:16 ` juzhe.zhong
2023-10-17 11:34 ` [PATCH V2 11/14] RISC-V: P11: Adjust vector_block_info to vsetvl_block_info class Lehua Ding
2023-10-18 4:06 ` juzhe.zhong
2023-10-17 11:34 ` [PATCH V2 12/14] RISC-V: P12: Delete riscv-vsetvl.h Lehua Ding
2023-10-18 4:16 ` juzhe.zhong
2023-10-17 11:34 ` [PATCH V2 13/14] RISC-V: P13: Reorganize functions used to modify RTL Lehua Ding
2023-10-18 4:17 ` juzhe.zhong
2023-10-17 11:35 ` [PATCH V2 14/14] RISC-V: P14: Adjust and add testcases Lehua Ding
2023-10-18 4:17 ` juzhe.zhong
2023-10-17 20:25 ` [PATCH V2 00/14] Refactor and cleanup vsetvl pass Patrick O'Neill
2023-10-18 2:20 ` Lehua Ding
2023-10-18 9:14 ` Lehua Ding
2023-10-18 17:17 ` Patrick O'Neill
2023-10-19 8:41 ` Lehua Ding
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