From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbgsg1.qq.com (smtpbgsg1.qq.com [54.254.200.92]) by sourceware.org (Postfix) with ESMTPS id A28833858C53 for ; Thu, 24 Aug 2023 10:16:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A28833858C53 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp90t1692872167tvu1jz5q Received: from [10.101.11.9] ( [119.123.199.188]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 24 Aug 2023 18:16:06 +0800 (CST) X-QQ-SSF: 01400000000000C0F000000A0000000 X-QQ-FEAT: +ynUkgUhZJmO7KZyIjawD7D6HlUFwkEUaNSRRx7en6Kwfj+iyC11t+jAAoSUJ R5e2T3bQCEioKwC7dgBdD8M1QQ1xzCEmJNxDXX5UzNvj5kU5hmqaN+cy7Xb+dFoe7UzyIfC gcIN8T0wgCPyDujNGXFRbHhXOUP/4OJ7sUezW1edTNmQwXHstdx9zTsA6rPOa/v9I6nwP1R gWza+ePhp4XVLXnTElxi3jBUrzcDKGyuhsPof3FbzkYh9EBVAILGKXl2SR5AtNUSi69IlH1 dlQZjHd1dsZ6mgUZklExgLS/ERR+ocg+2xb1EZ4TRp55Xyl8cerzAkT/yhBcjeMoCwXv3ZN +u8wjWWgcZBQyOZP/qYkhCpYEKxKaHhHBttcmmK0LR03n+vAIBaBmlWS0jbAA== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 15789786647644271244 Message-ID: Date: Thu, 24 Aug 2023 18:16:06 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] RISC-V: Add conditional sign/zero extension and truncation autovec patterns Content-Language: en-US To: Robin Dapp , gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, palmer@rivosinc.com, jeffreyalaw@gmail.com References: <20230823110317.4053846-1-lehua.ding@rivai.ai> From: Lehua Ding In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz6a-0 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,FORGED_MUA_MOZILLA,KAM_DMARC_STATUS,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Robin, On 2023/8/24 17:59, Robin Dapp wrote: > Hi Lehua, > > thanks, just tiny non-functional nits. > >> - rtx ops[] = {operands[0], quarter}; >> - icode = code_for_pred_trunc (mode); >> - riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, ops); >> + rtx half = gen_reg_rtx (mode); > > Not really a half anymore now? :) Yes, it's better to call it one_quad. > >> +#include >> + >> +#define DEF_LOOP(OLD_TYPE, NEW_TYPE) \ >> + void __attribute__ ((noipa)) \ >> + test_##OLD_TYPE##_2_##NEW_TYPE (NEW_TYPE *__restrict r, \ >> + OLD_TYPE *__restrict a, \ >> + NEW_TYPE *__restrict b, \ >> + OLD_TYPE *__restrict pred, int n) \ >> + { \ >> + for (int i = 0; i < n; ++i) \ >> + { \ >> + NEW_TYPE bi = b[i]; \ > > Is this necessary for recognizing a different pattern? Are you saying that the testcases xxx-1 and xxx-2 are duplicated? If so, I have no problem removing it and just keeping xxx-1 testcase since it is still possible to cover my code. > >> +/* wider-width Integer Type => Integer Type */ > > Isn't it the other way around or am I just confused? Yes, I changed it to the following which might be better understood: /* INT -> wider-INT */ > >> +/* narrower-width Integer Type => Integer Type */ >> +#define TEST_ALL_X2X_NARROWER(T) \ >> + T (uint16_t, uint8_t) \ > > Same here. > > Regards > Robin > > -- Best, Lehua