From: "juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai>
To: pan2.li <pan2.li@intel.com>, gcc-patches <gcc-patches@gcc.gnu.org>
Cc: kito.cheng <kito.cheng@gmail.com>,
jeffreyalaw <jeffreyalaw@gmail.com>,
"Robin Dapp" <rdapp.gcc@gmail.com>, pan2.li <pan2.li@intel.com>
Subject: Re: [PATCH v1 3/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 5
Date: Fri, 14 Jun 2024 10:24:29 +0800 [thread overview]
Message-ID: <F254EC13B43025A1+202406141024282680782@rivai.ai> (raw)
In-Reply-To: <20240614021328.3032144-3-pan2.li@intel.com>
[-- Attachment #1: Type: text/plain, Size: 10941 bytes --]
LGTM
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2024-06-14 10:13
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 3/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 5
From: Pan Li <pan2.li@intel.com>
After the middle-end support the form 5 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 5 of unsigned .SAT_SUB.
Form 5:
#define SAT_SUB_U_5(T) \
T sat_sub_u_5_##T (T x, T y) \
{ \
return x < y ? 0 : x - y; \
}
Passed the rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-17.c: New test.
* gcc.target/riscv/sat_u_sub-18.c: New test.
* gcc.target/riscv/sat_u_sub-19.c: New test.
* gcc.target/riscv/sat_u_sub-20.c: New test.
* gcc.target/riscv/sat_u_sub-run-17.c: New test.
* gcc.target/riscv/sat_u_sub-run-18.c: New test.
* gcc.target/riscv/sat_u_sub-run-19.c: New test.
* gcc.target/riscv/sat_u_sub-run-20.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 8 ++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-17.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-18.c | 19 ++++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-19.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-20.c | 17 +++++++++++++
.../gcc.target/riscv/sat_u_sub-run-17.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-18.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-19.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-20.c | 25 +++++++++++++++++++
9 files changed, 180 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-17.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-18.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-19.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-20.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-17.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-18.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-19.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-20.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index b2f8478d36b..d08755dd861 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -106,10 +106,18 @@ sat_u_sub_##T##_fmt_4 (T x, T y) \
return x >= y ? x - y : 0; \
}
+#define DEF_SAT_U_SUB_FMT_5(T) \
+T __attribute__((noinline)) \
+sat_u_sub_##T##_fmt_5 (T x, T y) \
+{ \
+ return x < y ? 0 : x - y; \
+}
+
#define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
#define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
#define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
#define RUN_SAT_U_SUB_FMT_4(T, x, y) sat_u_sub_##T##_fmt_4(x, y)
+#define RUN_SAT_U_SUB_FMT_5(T, x, y) sat_u_sub_##T##_fmt_5(x, y)
#define DEF_VEC_SAT_U_SUB_FMT_1(T) \
void __attribute__((noinline)) \
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-17.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-17.c
new file mode 100644
index 00000000000..853ddcfd285
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-17.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint8_t_fmt_5:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_SUB_FMT_5(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-18.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-18.c
new file mode 100644
index 00000000000..423a6f82170
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-18.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint16_t_fmt_5:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_SUB_FMT_5(uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-19.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-19.c
new file mode 100644
index 00000000000..29b9c235d97
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-19.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint32_t_fmt_5:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_SUB_FMT_5(uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-20.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-20.c
new file mode 100644
index 00000000000..89e84d60f94
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-20.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint64_t_fmt_5:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+a0,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_SUB_FMT_5(uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-17.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-17.c
new file mode 100644
index 00000000000..b2823112b62
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-17.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint8_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_5
+
+DEF_SAT_U_SUB_FMT_5(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 255, 254, 1, },
+ { 255, 255, 0, },
+ { 254, 255, 0, },
+ { 253, 254, 0, },
+ { 0, 255, 0, },
+ { 1, 255, 0, },
+ { 32, 5, 27, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-18.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-18.c
new file mode 100644
index 00000000000..9f575a47bfe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-18.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint16_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_5
+
+DEF_SAT_U_SUB_FMT_5(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 65535, 65534, 1, },
+ { 65535, 65535, 0, },
+ { 65534, 65535, 0, },
+ { 65533, 65534, 0, },
+ { 0, 65535, 0, },
+ { 1, 65535, 0, },
+ { 35, 5, 30, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-19.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-19.c
new file mode 100644
index 00000000000..c370455c3d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-19.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint32_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_5
+
+DEF_SAT_U_SUB_FMT_5(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 4294967295, 4294967294, 1, },
+ { 4294967295, 4294967295, 0, },
+ { 4294967294, 4294967295, 0, },
+ { 4294967293, 4294967294, 0, },
+ { 1, 4294967295, 0, },
+ { 2, 4294967295, 0, },
+ { 5, 1, 4, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-20.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-20.c
new file mode 100644
index 00000000000..22d82f973d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-20.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint64_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_5
+
+DEF_SAT_U_SUB_FMT_5(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 18446744073709551615u, 18446744073709551614u, 1, },
+ { 18446744073709551615u, 18446744073709551615u, 0, },
+ { 18446744073709551614u, 18446744073709551615u, 0, },
+ { 18446744073709551613u, 18446744073709551614u, 0, },
+ { 0, 18446744073709551615u, 0, },
+ { 1, 18446744073709551615u, 0, },
+ { 43, 11, 32, },
+};
+
+#include "scalar_sat_binary.h"
--
2.34.1
next prev parent reply other threads:[~2024-06-14 2:24 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-14 2:13 [PATCH v1 1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3 pan2.li
2024-06-14 2:13 ` [PATCH v1 2/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 4 pan2.li
2024-06-14 2:24 ` juzhe.zhong
2024-06-14 2:13 ` [PATCH v1 3/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 5 pan2.li
2024-06-14 2:24 ` juzhe.zhong [this message]
2024-06-14 2:13 ` [PATCH v1 4/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 6 pan2.li
2024-06-14 2:24 ` juzhe.zhong
2024-06-14 2:13 ` [PATCH v1 5/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 7 pan2.li
2024-06-14 2:24 ` juzhe.zhong
2024-06-14 2:13 ` [PATCH v1 6/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 8 pan2.li
2024-06-14 2:24 ` juzhe.zhong
2024-06-14 2:13 ` [PATCH v1 7/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 9 pan2.li
2024-06-14 2:24 ` juzhe.zhong
2024-06-14 2:13 ` [PATCH v1 8/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 10 pan2.li
2024-06-14 2:24 ` juzhe.zhong
2024-06-14 2:24 ` [PATCH v1 1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3 juzhe.zhong
2024-06-14 2:29 ` Li, Pan2
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