* [PATCH v1 1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3
@ 2024-06-14 2:13 pan2.li
2024-06-14 2:13 ` [PATCH v1 2/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 4 pan2.li
` (7 more replies)
0 siblings, 8 replies; 17+ messages in thread
From: pan2.li @ 2024-06-14 2:13 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, jeffreyalaw, rdapp.gcc, Pan Li
From: Pan Li <pan2.li@intel.com>
After the middle-end support the form 3 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 3 of unsigned .SAT_SUB.
Form 3:
#define SAT_SUB_U_3(T) \
T sat_sub_u_3_##T (T x, T y) \
{ \
return x > y ? x - y : 0; \
}
Passed the rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-10.c: New test.
* gcc.target/riscv/sat_u_sub-11.c: New test.
* gcc.target/riscv/sat_u_sub-12.c: New test.
* gcc.target/riscv/sat_u_sub-9.c: New test.
* gcc.target/riscv/sat_u_sub-run-10.c: New test.
* gcc.target/riscv/sat_u_sub-run-11.c: New test.
* gcc.target/riscv/sat_u_sub-run-12.c: New test.
* gcc.target/riscv/sat_u_sub-run-9.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 8 ++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c | 19 ++++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c | 17 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-9.c | 18 +++++++++++++
.../gcc.target/riscv/sat_u_sub-run-10.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-11.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-12.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-9.c | 25 +++++++++++++++++++
9 files changed, 180 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-9.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-11.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-12.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-9.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index bc9a372b6df..50c65cdea49 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -92,8 +92,16 @@ sat_u_sub_##T##_fmt_2 (T x, T y) \
return (x - y) & (-(T)(x > y)); \
}
+#define DEF_SAT_U_SUB_FMT_3(T) \
+T __attribute__((noinline)) \
+sat_u_sub_##T##_fmt_3 (T x, T y) \
+{ \
+ return x > y ? x - y : 0; \
+}
+
#define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
#define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
+#define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
#define DEF_VEC_SAT_U_SUB_FMT_1(T) \
void __attribute__((noinline)) \
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c
new file mode 100644
index 00000000000..6e78164865f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint16_t_fmt_3:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_SUB_FMT_3(uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c
new file mode 100644
index 00000000000..84e34657f55
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint32_t_fmt_3:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_SUB_FMT_3(uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c
new file mode 100644
index 00000000000..eea282b21ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint64_t_fmt_3:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+a0,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_SUB_FMT_3(uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-9.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-9.c
new file mode 100644
index 00000000000..b24bf3eb549
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-9.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint8_t_fmt_3:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_SUB_FMT_3(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-10.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-10.c
new file mode 100644
index 00000000000..ea52ff4573e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-10.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint16_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_3
+
+DEF_SAT_U_SUB_FMT_3(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 65535, 65534, 1, },
+ { 65535, 65535, 0, },
+ { 65534, 65535, 0, },
+ { 65533, 65534, 0, },
+ { 0, 65535, 0, },
+ { 1, 65535, 0, },
+ { 35, 5, 30, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-11.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-11.c
new file mode 100644
index 00000000000..fdea8916ab3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-11.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint32_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_3
+
+DEF_SAT_U_SUB_FMT_3(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 4294967295, 4294967294, 1, },
+ { 4294967295, 4294967295, 0, },
+ { 4294967294, 4294967295, 0, },
+ { 4294967293, 4294967294, 0, },
+ { 1, 4294967295, 0, },
+ { 2, 4294967295, 0, },
+ { 5, 1, 4, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-12.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-12.c
new file mode 100644
index 00000000000..164ee77fb76
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-12.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint64_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_3
+
+DEF_SAT_U_SUB_FMT_3(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 18446744073709551615u, 18446744073709551614u, 1, },
+ { 18446744073709551615u, 18446744073709551615u, 0, },
+ { 18446744073709551614u, 18446744073709551615u, 0, },
+ { 18446744073709551613u, 18446744073709551614u, 0, },
+ { 0, 18446744073709551615u, 0, },
+ { 1, 18446744073709551615u, 0, },
+ { 43, 11, 32, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-9.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-9.c
new file mode 100644
index 00000000000..724adf92d3e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-9.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint8_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_3
+
+DEF_SAT_U_SUB_FMT_3(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 255, 254, 1, },
+ { 255, 255, 0, },
+ { 254, 255, 0, },
+ { 253, 254, 0, },
+ { 0, 255, 0, },
+ { 1, 255, 0, },
+ { 32, 5, 27, },
+};
+
+#include "scalar_sat_binary.h"
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v1 2/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 4
2024-06-14 2:13 [PATCH v1 1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3 pan2.li
@ 2024-06-14 2:13 ` pan2.li
2024-06-14 2:24 ` juzhe.zhong
2024-06-14 2:13 ` [PATCH v1 3/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 5 pan2.li
` (6 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: pan2.li @ 2024-06-14 2:13 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, jeffreyalaw, rdapp.gcc, Pan Li
From: Pan Li <pan2.li@intel.com>
After the middle-end support the form 4 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 4 of unsigned .SAT_SUB.
Form 4:
#define SAT_SUB_U_4(T) \
T sat_sub_u_4_##T (T x, T y) \
{ \
return x >= y ? x - y : 0; \
}
Passed the rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-13.c: New test.
* gcc.target/riscv/sat_u_sub-14.c: New test.
* gcc.target/riscv/sat_u_sub-15.c: New test.
* gcc.target/riscv/sat_u_sub-16.c: New test.
* gcc.target/riscv/sat_u_sub-run-13.c: New test.
* gcc.target/riscv/sat_u_sub-run-14.c: New test.
* gcc.target/riscv/sat_u_sub-run-15.c: New test.
* gcc.target/riscv/sat_u_sub-run-16.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 8 ++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-13.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-14.c | 19 ++++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-15.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-16.c | 17 +++++++++++++
.../gcc.target/riscv/sat_u_sub-run-13.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-14.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-15.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-16.c | 25 +++++++++++++++++++
9 files changed, 180 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-13.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-14.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-15.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-16.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-13.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-14.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-15.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-16.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index 50c65cdea49..b2f8478d36b 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -99,9 +99,17 @@ sat_u_sub_##T##_fmt_3 (T x, T y) \
return x > y ? x - y : 0; \
}
+#define DEF_SAT_U_SUB_FMT_4(T) \
+T __attribute__((noinline)) \
+sat_u_sub_##T##_fmt_4 (T x, T y) \
+{ \
+ return x >= y ? x - y : 0; \
+}
+
#define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
#define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
#define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
+#define RUN_SAT_U_SUB_FMT_4(T, x, y) sat_u_sub_##T##_fmt_4(x, y)
#define DEF_VEC_SAT_U_SUB_FMT_1(T) \
void __attribute__((noinline)) \
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-13.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-13.c
new file mode 100644
index 00000000000..edb7017f9b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-13.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint8_t_fmt_4:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_SUB_FMT_4(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-14.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-14.c
new file mode 100644
index 00000000000..2aab9f65586
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-14.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint16_t_fmt_4:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_SUB_FMT_4(uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-15.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-15.c
new file mode 100644
index 00000000000..25ad702bf04
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-15.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint32_t_fmt_4:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_SUB_FMT_4(uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-16.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-16.c
new file mode 100644
index 00000000000..72c1931608f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-16.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint64_t_fmt_4:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+a0,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_SUB_FMT_4(uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-13.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-13.c
new file mode 100644
index 00000000000..c8ae7a6680d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-13.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint8_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_4
+
+DEF_SAT_U_SUB_FMT_4(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 255, 254, 1, },
+ { 255, 255, 0, },
+ { 254, 255, 0, },
+ { 253, 254, 0, },
+ { 0, 255, 0, },
+ { 1, 255, 0, },
+ { 32, 5, 27, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-14.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-14.c
new file mode 100644
index 00000000000..9b57861b578
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-14.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint16_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_4
+
+DEF_SAT_U_SUB_FMT_4(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 65535, 65534, 1, },
+ { 65535, 65535, 0, },
+ { 65534, 65535, 0, },
+ { 65533, 65534, 0, },
+ { 0, 65535, 0, },
+ { 1, 65535, 0, },
+ { 35, 5, 30, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-15.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-15.c
new file mode 100644
index 00000000000..df2eecef6fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-15.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint32_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_4
+
+DEF_SAT_U_SUB_FMT_4(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 4294967295, 4294967294, 1, },
+ { 4294967295, 4294967295, 0, },
+ { 4294967294, 4294967295, 0, },
+ { 4294967293, 4294967294, 0, },
+ { 1, 4294967295, 0, },
+ { 2, 4294967295, 0, },
+ { 5, 1, 4, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-16.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-16.c
new file mode 100644
index 00000000000..09e9ac38a83
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-16.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint64_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_4
+
+DEF_SAT_U_SUB_FMT_4(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 18446744073709551615u, 18446744073709551614u, 1, },
+ { 18446744073709551615u, 18446744073709551615u, 0, },
+ { 18446744073709551614u, 18446744073709551615u, 0, },
+ { 18446744073709551613u, 18446744073709551614u, 0, },
+ { 0, 18446744073709551615u, 0, },
+ { 1, 18446744073709551615u, 0, },
+ { 43, 11, 32, },
+};
+
+#include "scalar_sat_binary.h"
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v1 3/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 5
2024-06-14 2:13 [PATCH v1 1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3 pan2.li
2024-06-14 2:13 ` [PATCH v1 2/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 4 pan2.li
@ 2024-06-14 2:13 ` pan2.li
2024-06-14 2:24 ` juzhe.zhong
2024-06-14 2:13 ` [PATCH v1 4/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 6 pan2.li
` (5 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: pan2.li @ 2024-06-14 2:13 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, jeffreyalaw, rdapp.gcc, Pan Li
From: Pan Li <pan2.li@intel.com>
After the middle-end support the form 5 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 5 of unsigned .SAT_SUB.
Form 5:
#define SAT_SUB_U_5(T) \
T sat_sub_u_5_##T (T x, T y) \
{ \
return x < y ? 0 : x - y; \
}
Passed the rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-17.c: New test.
* gcc.target/riscv/sat_u_sub-18.c: New test.
* gcc.target/riscv/sat_u_sub-19.c: New test.
* gcc.target/riscv/sat_u_sub-20.c: New test.
* gcc.target/riscv/sat_u_sub-run-17.c: New test.
* gcc.target/riscv/sat_u_sub-run-18.c: New test.
* gcc.target/riscv/sat_u_sub-run-19.c: New test.
* gcc.target/riscv/sat_u_sub-run-20.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 8 ++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-17.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-18.c | 19 ++++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-19.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-20.c | 17 +++++++++++++
.../gcc.target/riscv/sat_u_sub-run-17.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-18.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-19.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-20.c | 25 +++++++++++++++++++
9 files changed, 180 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-17.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-18.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-19.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-20.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-17.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-18.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-19.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-20.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index b2f8478d36b..d08755dd861 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -106,10 +106,18 @@ sat_u_sub_##T##_fmt_4 (T x, T y) \
return x >= y ? x - y : 0; \
}
+#define DEF_SAT_U_SUB_FMT_5(T) \
+T __attribute__((noinline)) \
+sat_u_sub_##T##_fmt_5 (T x, T y) \
+{ \
+ return x < y ? 0 : x - y; \
+}
+
#define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
#define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
#define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
#define RUN_SAT_U_SUB_FMT_4(T, x, y) sat_u_sub_##T##_fmt_4(x, y)
+#define RUN_SAT_U_SUB_FMT_5(T, x, y) sat_u_sub_##T##_fmt_5(x, y)
#define DEF_VEC_SAT_U_SUB_FMT_1(T) \
void __attribute__((noinline)) \
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-17.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-17.c
new file mode 100644
index 00000000000..853ddcfd285
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-17.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint8_t_fmt_5:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_SUB_FMT_5(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-18.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-18.c
new file mode 100644
index 00000000000..423a6f82170
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-18.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint16_t_fmt_5:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_SUB_FMT_5(uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-19.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-19.c
new file mode 100644
index 00000000000..29b9c235d97
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-19.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint32_t_fmt_5:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_SUB_FMT_5(uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-20.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-20.c
new file mode 100644
index 00000000000..89e84d60f94
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-20.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint64_t_fmt_5:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+a0,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_SUB_FMT_5(uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-17.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-17.c
new file mode 100644
index 00000000000..b2823112b62
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-17.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint8_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_5
+
+DEF_SAT_U_SUB_FMT_5(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 255, 254, 1, },
+ { 255, 255, 0, },
+ { 254, 255, 0, },
+ { 253, 254, 0, },
+ { 0, 255, 0, },
+ { 1, 255, 0, },
+ { 32, 5, 27, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-18.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-18.c
new file mode 100644
index 00000000000..9f575a47bfe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-18.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint16_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_5
+
+DEF_SAT_U_SUB_FMT_5(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 65535, 65534, 1, },
+ { 65535, 65535, 0, },
+ { 65534, 65535, 0, },
+ { 65533, 65534, 0, },
+ { 0, 65535, 0, },
+ { 1, 65535, 0, },
+ { 35, 5, 30, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-19.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-19.c
new file mode 100644
index 00000000000..c370455c3d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-19.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint32_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_5
+
+DEF_SAT_U_SUB_FMT_5(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 4294967295, 4294967294, 1, },
+ { 4294967295, 4294967295, 0, },
+ { 4294967294, 4294967295, 0, },
+ { 4294967293, 4294967294, 0, },
+ { 1, 4294967295, 0, },
+ { 2, 4294967295, 0, },
+ { 5, 1, 4, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-20.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-20.c
new file mode 100644
index 00000000000..22d82f973d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-20.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint64_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_5
+
+DEF_SAT_U_SUB_FMT_5(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 18446744073709551615u, 18446744073709551614u, 1, },
+ { 18446744073709551615u, 18446744073709551615u, 0, },
+ { 18446744073709551614u, 18446744073709551615u, 0, },
+ { 18446744073709551613u, 18446744073709551614u, 0, },
+ { 0, 18446744073709551615u, 0, },
+ { 1, 18446744073709551615u, 0, },
+ { 43, 11, 32, },
+};
+
+#include "scalar_sat_binary.h"
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v1 4/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 6
2024-06-14 2:13 [PATCH v1 1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3 pan2.li
2024-06-14 2:13 ` [PATCH v1 2/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 4 pan2.li
2024-06-14 2:13 ` [PATCH v1 3/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 5 pan2.li
@ 2024-06-14 2:13 ` pan2.li
2024-06-14 2:24 ` juzhe.zhong
2024-06-14 2:13 ` [PATCH v1 5/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 7 pan2.li
` (4 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: pan2.li @ 2024-06-14 2:13 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, jeffreyalaw, rdapp.gcc, Pan Li
From: Pan Li <pan2.li@intel.com>
After the middle-end support the form 6 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 6 of unsigned .SAT_SUB.
Form 6:
#define SAT_SUB_U_6(T) \
T sat_sub_u_6_##T (T x, T y) \
{ \
return x <= y ? 0 : x - y; \
}
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-21.c: New test.
* gcc.target/riscv/sat_u_sub-22.c: New test.
* gcc.target/riscv/sat_u_sub-23.c: New test.
* gcc.target/riscv/sat_u_sub-24.c: New test.
* gcc.target/riscv/sat_u_sub-run-21.c: New test.
* gcc.target/riscv/sat_u_sub-run-22.c: New test.
* gcc.target/riscv/sat_u_sub-run-23.c: New test.
* gcc.target/riscv/sat_u_sub-run-24.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 8 ++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-21.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-22.c | 19 ++++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-23.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-24.c | 17 +++++++++++++
.../gcc.target/riscv/sat_u_sub-run-21.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-22.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-23.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-24.c | 25 +++++++++++++++++++
9 files changed, 180 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-21.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-22.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-23.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-24.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-21.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-22.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-23.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-24.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index d08755dd861..4296235cf62 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -113,11 +113,19 @@ sat_u_sub_##T##_fmt_5 (T x, T y) \
return x < y ? 0 : x - y; \
}
+#define DEF_SAT_U_SUB_FMT_6(T) \
+T __attribute__((noinline)) \
+sat_u_sub_##T##_fmt_6 (T x, T y) \
+{ \
+ return x <= y ? 0 : x - y; \
+}
+
#define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
#define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
#define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
#define RUN_SAT_U_SUB_FMT_4(T, x, y) sat_u_sub_##T##_fmt_4(x, y)
#define RUN_SAT_U_SUB_FMT_5(T, x, y) sat_u_sub_##T##_fmt_5(x, y)
+#define RUN_SAT_U_SUB_FMT_6(T, x, y) sat_u_sub_##T##_fmt_6(x, y)
#define DEF_VEC_SAT_U_SUB_FMT_1(T) \
void __attribute__((noinline)) \
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-21.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-21.c
new file mode 100644
index 00000000000..9a8fb7f1c91
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-21.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint8_t_fmt_6:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_SUB_FMT_6(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-22.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-22.c
new file mode 100644
index 00000000000..6182169edc5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-22.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint16_t_fmt_6:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_SUB_FMT_6(uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-23.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-23.c
new file mode 100644
index 00000000000..820110cdbb0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-23.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint32_t_fmt_6:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_SUB_FMT_6(uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-24.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-24.c
new file mode 100644
index 00000000000..48e6296e315
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-24.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint64_t_fmt_6:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+a0,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_SUB_FMT_6(uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-21.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-21.c
new file mode 100644
index 00000000000..0b4cbdbf599
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-21.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint8_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_6
+
+DEF_SAT_U_SUB_FMT_6(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 255, 254, 1, },
+ { 255, 255, 0, },
+ { 254, 255, 0, },
+ { 253, 254, 0, },
+ { 0, 255, 0, },
+ { 1, 255, 0, },
+ { 32, 5, 27, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-22.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-22.c
new file mode 100644
index 00000000000..e0dda451775
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-22.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint16_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_6
+
+DEF_SAT_U_SUB_FMT_6(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 65535, 65534, 1, },
+ { 65535, 65535, 0, },
+ { 65534, 65535, 0, },
+ { 65533, 65534, 0, },
+ { 0, 65535, 0, },
+ { 1, 65535, 0, },
+ { 35, 5, 30, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-23.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-23.c
new file mode 100644
index 00000000000..dfd95ef58c3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-23.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint32_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_6
+
+DEF_SAT_U_SUB_FMT_6(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 4294967295, 4294967294, 1, },
+ { 4294967295, 4294967295, 0, },
+ { 4294967294, 4294967295, 0, },
+ { 4294967293, 4294967294, 0, },
+ { 1, 4294967295, 0, },
+ { 2, 4294967295, 0, },
+ { 5, 1, 4, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-24.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-24.c
new file mode 100644
index 00000000000..7cac446aa33
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-24.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint64_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_6
+
+DEF_SAT_U_SUB_FMT_6(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 18446744073709551615u, 18446744073709551614u, 1, },
+ { 18446744073709551615u, 18446744073709551615u, 0, },
+ { 18446744073709551614u, 18446744073709551615u, 0, },
+ { 18446744073709551613u, 18446744073709551614u, 0, },
+ { 0, 18446744073709551615u, 0, },
+ { 1, 18446744073709551615u, 0, },
+ { 43, 11, 32, },
+};
+
+#include "scalar_sat_binary.h"
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v1 5/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 7
2024-06-14 2:13 [PATCH v1 1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3 pan2.li
` (2 preceding siblings ...)
2024-06-14 2:13 ` [PATCH v1 4/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 6 pan2.li
@ 2024-06-14 2:13 ` pan2.li
2024-06-14 2:24 ` juzhe.zhong
2024-06-14 2:13 ` [PATCH v1 6/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 8 pan2.li
` (3 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: pan2.li @ 2024-06-14 2:13 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, jeffreyalaw, rdapp.gcc, Pan Li
From: Pan Li <pan2.li@intel.com>
After the middle-end support the form 7 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 7 of unsigned .SAT_SUB.
Form 7:
#define SAT_SUB_U_7(T) \
T sat_sub_u_7_##T (T x, T y) \
{ \
T ret; \
T overflow = __builtin_sub_overflow (x, y, &ret); \
return ret & (T)(overflow - 1); \
}
Passed the rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-25.c: New test.
* gcc.target/riscv/sat_u_sub-26.c: New test.
* gcc.target/riscv/sat_u_sub-27.c: New test.
* gcc.target/riscv/sat_u_sub-28.c: New test.
* gcc.target/riscv/sat_u_sub-run-25.c: New test.
* gcc.target/riscv/sat_u_sub-run-26.c: New test.
* gcc.target/riscv/sat_u_sub-run-27.c: New test.
* gcc.target/riscv/sat_u_sub-run-28.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 10 ++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-25.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-26.c | 19 ++++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-27.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-28.c | 17 +++++++++++++
.../gcc.target/riscv/sat_u_sub-run-25.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-26.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-27.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-28.c | 25 +++++++++++++++++++
9 files changed, 182 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-25.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-26.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-27.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-28.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-25.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-26.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-27.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-28.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index 4296235cf62..bde054d5c9d 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -120,12 +120,22 @@ sat_u_sub_##T##_fmt_6 (T x, T y) \
return x <= y ? 0 : x - y; \
}
+#define DEF_SAT_U_SUB_FMT_7(T) \
+T __attribute__((noinline)) \
+sat_u_sub_##T##_fmt_7 (T x, T y) \
+{ \
+ T ret; \
+ T overflow = __builtin_sub_overflow (x, y, &ret); \
+ return ret & (T)(overflow - 1); \
+}
+
#define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
#define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
#define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
#define RUN_SAT_U_SUB_FMT_4(T, x, y) sat_u_sub_##T##_fmt_4(x, y)
#define RUN_SAT_U_SUB_FMT_5(T, x, y) sat_u_sub_##T##_fmt_5(x, y)
#define RUN_SAT_U_SUB_FMT_6(T, x, y) sat_u_sub_##T##_fmt_6(x, y)
+#define RUN_SAT_U_SUB_FMT_7(T, x, y) sat_u_sub_##T##_fmt_7(x, y)
#define DEF_VEC_SAT_U_SUB_FMT_1(T) \
void __attribute__((noinline)) \
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-25.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-25.c
new file mode 100644
index 00000000000..8780ef0c8f1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-25.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint8_t_fmt_7:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_SUB_FMT_7(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-26.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-26.c
new file mode 100644
index 00000000000..f720f619d09
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-26.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint16_t_fmt_7:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_SUB_FMT_7(uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-27.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-27.c
new file mode 100644
index 00000000000..779c9247e02
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-27.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint32_t_fmt_7:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_SUB_FMT_7(uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-28.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-28.c
new file mode 100644
index 00000000000..86b80dbccd5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-28.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint64_t_fmt_7:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+a0,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_SUB_FMT_7(uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-25.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-25.c
new file mode 100644
index 00000000000..d101d2897c9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-25.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint8_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_7
+
+DEF_SAT_U_SUB_FMT_7(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 255, 254, 1, },
+ { 255, 255, 0, },
+ { 254, 255, 0, },
+ { 253, 254, 0, },
+ { 0, 255, 0, },
+ { 1, 255, 0, },
+ { 32, 5, 27, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-26.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-26.c
new file mode 100644
index 00000000000..10c65fec97d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-26.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint16_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_7
+
+DEF_SAT_U_SUB_FMT_7(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 65535, 65534, 1, },
+ { 65535, 65535, 0, },
+ { 65534, 65535, 0, },
+ { 65533, 65534, 0, },
+ { 0, 65535, 0, },
+ { 1, 65535, 0, },
+ { 35, 5, 30, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-27.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-27.c
new file mode 100644
index 00000000000..e3b4dde683d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-27.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint32_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_7
+
+DEF_SAT_U_SUB_FMT_7(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 4294967295, 4294967294, 1, },
+ { 4294967295, 4294967295, 0, },
+ { 4294967294, 4294967295, 0, },
+ { 4294967293, 4294967294, 0, },
+ { 1, 4294967295, 0, },
+ { 2, 4294967295, 0, },
+ { 5, 1, 4, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-28.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-28.c
new file mode 100644
index 00000000000..6e93fcff032
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-28.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint64_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_7
+
+DEF_SAT_U_SUB_FMT_7(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 18446744073709551615u, 18446744073709551614u, 1, },
+ { 18446744073709551615u, 18446744073709551615u, 0, },
+ { 18446744073709551614u, 18446744073709551615u, 0, },
+ { 18446744073709551613u, 18446744073709551614u, 0, },
+ { 0, 18446744073709551615u, 0, },
+ { 1, 18446744073709551615u, 0, },
+ { 43, 11, 32, },
+};
+
+#include "scalar_sat_binary.h"
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v1 6/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 8
2024-06-14 2:13 [PATCH v1 1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3 pan2.li
` (3 preceding siblings ...)
2024-06-14 2:13 ` [PATCH v1 5/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 7 pan2.li
@ 2024-06-14 2:13 ` pan2.li
2024-06-14 2:24 ` juzhe.zhong
2024-06-14 2:13 ` [PATCH v1 7/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 9 pan2.li
` (2 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: pan2.li @ 2024-06-14 2:13 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, jeffreyalaw, rdapp.gcc, Pan Li
From: Pan Li <pan2.li@intel.com>
After the middle-end support the form 8 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 8 of unsigned .SAT_SUB.
Form 8:
#define SAT_SUB_U_8(T) \
T sat_sub_u_8_##T (T x, T y) \
{ \
T ret; \
T overflow = __builtin_sub_overflow (x, y, &ret); \
return ret & (T)-(!overflow); \
}
Passed the rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-29.c: New test.
* gcc.target/riscv/sat_u_sub-30.c: New test.
* gcc.target/riscv/sat_u_sub-31.c: New test.
* gcc.target/riscv/sat_u_sub-32.c: New test.
* gcc.target/riscv/sat_u_sub-run-29.c: New test.
* gcc.target/riscv/sat_u_sub-run-30.c: New test.
* gcc.target/riscv/sat_u_sub-run-31.c: New test.
* gcc.target/riscv/sat_u_sub-run-32.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 10 ++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-29.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-30.c | 19 ++++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-31.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-32.c | 17 +++++++++++++
.../gcc.target/riscv/sat_u_sub-run-29.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-30.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-31.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-32.c | 25 +++++++++++++++++++
9 files changed, 182 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-29.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-30.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-31.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-29.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-30.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-31.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-32.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index bde054d5c9d..9f901de5cdf 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -129,6 +129,15 @@ sat_u_sub_##T##_fmt_7 (T x, T y) \
return ret & (T)(overflow - 1); \
}
+#define DEF_SAT_U_SUB_FMT_8(T) \
+T __attribute__((noinline)) \
+sat_u_sub_##T##_fmt_8 (T x, T y) \
+{ \
+ T ret; \
+ T overflow = __builtin_sub_overflow (x, y, &ret); \
+ return ret & (T)-(!overflow); \
+}
+
#define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
#define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
#define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
@@ -136,6 +145,7 @@ sat_u_sub_##T##_fmt_7 (T x, T y) \
#define RUN_SAT_U_SUB_FMT_5(T, x, y) sat_u_sub_##T##_fmt_5(x, y)
#define RUN_SAT_U_SUB_FMT_6(T, x, y) sat_u_sub_##T##_fmt_6(x, y)
#define RUN_SAT_U_SUB_FMT_7(T, x, y) sat_u_sub_##T##_fmt_7(x, y)
+#define RUN_SAT_U_SUB_FMT_8(T, x, y) sat_u_sub_##T##_fmt_8(x, y)
#define DEF_VEC_SAT_U_SUB_FMT_1(T) \
void __attribute__((noinline)) \
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-29.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-29.c
new file mode 100644
index 00000000000..1a2da50256e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-29.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint8_t_fmt_8:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_SUB_FMT_8(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-30.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-30.c
new file mode 100644
index 00000000000..75aa7506369
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-30.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint16_t_fmt_8:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_SUB_FMT_8(uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-31.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-31.c
new file mode 100644
index 00000000000..bc935ea0f3d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-31.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint32_t_fmt_8:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_SUB_FMT_8(uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-32.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-32.c
new file mode 100644
index 00000000000..f0f2254182c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-32.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint64_t_fmt_8:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+a0,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_SUB_FMT_8(uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-29.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-29.c
new file mode 100644
index 00000000000..1f74562125b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-29.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint8_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_8
+
+DEF_SAT_U_SUB_FMT_8(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 255, 254, 1, },
+ { 255, 255, 0, },
+ { 254, 255, 0, },
+ { 253, 254, 0, },
+ { 0, 255, 0, },
+ { 1, 255, 0, },
+ { 32, 5, 27, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-30.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-30.c
new file mode 100644
index 00000000000..4e50e3f804e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-30.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint16_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_8
+
+DEF_SAT_U_SUB_FMT_8(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 65535, 65534, 1, },
+ { 65535, 65535, 0, },
+ { 65534, 65535, 0, },
+ { 65533, 65534, 0, },
+ { 0, 65535, 0, },
+ { 1, 65535, 0, },
+ { 35, 5, 30, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-31.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-31.c
new file mode 100644
index 00000000000..3c8f78d7ed3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-31.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint32_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_8
+
+DEF_SAT_U_SUB_FMT_8(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 4294967295, 4294967294, 1, },
+ { 4294967295, 4294967295, 0, },
+ { 4294967294, 4294967295, 0, },
+ { 4294967293, 4294967294, 0, },
+ { 1, 4294967295, 0, },
+ { 2, 4294967295, 0, },
+ { 5, 1, 4, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-32.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-32.c
new file mode 100644
index 00000000000..932596a28e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-32.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint64_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_8
+
+DEF_SAT_U_SUB_FMT_8(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 18446744073709551615u, 18446744073709551614u, 1, },
+ { 18446744073709551615u, 18446744073709551615u, 0, },
+ { 18446744073709551614u, 18446744073709551615u, 0, },
+ { 18446744073709551613u, 18446744073709551614u, 0, },
+ { 0, 18446744073709551615u, 0, },
+ { 1, 18446744073709551615u, 0, },
+ { 43, 11, 32, },
+};
+
+#include "scalar_sat_binary.h"
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v1 7/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 9
2024-06-14 2:13 [PATCH v1 1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3 pan2.li
` (4 preceding siblings ...)
2024-06-14 2:13 ` [PATCH v1 6/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 8 pan2.li
@ 2024-06-14 2:13 ` pan2.li
2024-06-14 2:24 ` juzhe.zhong
2024-06-14 2:13 ` [PATCH v1 8/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 10 pan2.li
2024-06-14 2:24 ` [PATCH v1 1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3 juzhe.zhong
7 siblings, 1 reply; 17+ messages in thread
From: pan2.li @ 2024-06-14 2:13 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, jeffreyalaw, rdapp.gcc, Pan Li
From: Pan Li <pan2.li@intel.com>
After the middle-end support the form 9 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 9 of unsigned .SAT_SUB.
Form 9:
#define SAT_SUB_U_9(T) \
T sat_sub_u_9_##T (T x, T y) \
{ \
T ret; \
T overflow = __builtin_sub_overflow (x, y, &ret); \
return overflow ? 0 : ret; \
}
Passed the rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-33.c: New test.
* gcc.target/riscv/sat_u_sub-34.c: New test.
* gcc.target/riscv/sat_u_sub-35.c: New test.
* gcc.target/riscv/sat_u_sub-36.c: New test.
* gcc.target/riscv/sat_u_sub-run-33.c: New test.
* gcc.target/riscv/sat_u_sub-run-34.c: New test.
* gcc.target/riscv/sat_u_sub-run-35.c: New test.
* gcc.target/riscv/sat_u_sub-run-36.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 10 ++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-33.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-34.c | 19 ++++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-35.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-36.c | 17 +++++++++++++
.../gcc.target/riscv/sat_u_sub-run-33.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-34.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-35.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-36.c | 25 +++++++++++++++++++
9 files changed, 182 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-33.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-34.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-35.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-36.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-33.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-34.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-35.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-36.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index 9f901de5cdf..ecb74e56e9c 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -138,6 +138,15 @@ sat_u_sub_##T##_fmt_8 (T x, T y) \
return ret & (T)-(!overflow); \
}
+#define DEF_SAT_U_SUB_FMT_9(T) \
+T __attribute__((noinline)) \
+sat_u_sub_##T##_fmt_9 (T x, T y) \
+{ \
+ T ret; \
+ T overflow = __builtin_sub_overflow (x, y, &ret); \
+ return overflow ? 0 : ret; \
+}
+
#define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
#define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
#define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
@@ -146,6 +155,7 @@ sat_u_sub_##T##_fmt_8 (T x, T y) \
#define RUN_SAT_U_SUB_FMT_6(T, x, y) sat_u_sub_##T##_fmt_6(x, y)
#define RUN_SAT_U_SUB_FMT_7(T, x, y) sat_u_sub_##T##_fmt_7(x, y)
#define RUN_SAT_U_SUB_FMT_8(T, x, y) sat_u_sub_##T##_fmt_8(x, y)
+#define RUN_SAT_U_SUB_FMT_9(T, x, y) sat_u_sub_##T##_fmt_9(x, y)
#define DEF_VEC_SAT_U_SUB_FMT_1(T) \
void __attribute__((noinline)) \
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-33.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-33.c
new file mode 100644
index 00000000000..aca4bd28b5d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-33.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint8_t_fmt_9:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_SUB_FMT_9(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-34.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-34.c
new file mode 100644
index 00000000000..f87a51a504b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-34.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint16_t_fmt_9:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_SUB_FMT_9(uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-35.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-35.c
new file mode 100644
index 00000000000..13c3e922f14
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-35.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint32_t_fmt_9:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_SUB_FMT_9(uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-36.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-36.c
new file mode 100644
index 00000000000..0254f539e09
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-36.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint64_t_fmt_9:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+a0,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_SUB_FMT_9(uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-33.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-33.c
new file mode 100644
index 00000000000..ab8b4750d01
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-33.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint8_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_9
+
+DEF_SAT_U_SUB_FMT_9(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 255, 254, 1, },
+ { 255, 255, 0, },
+ { 254, 255, 0, },
+ { 253, 254, 0, },
+ { 0, 255, 0, },
+ { 1, 255, 0, },
+ { 32, 5, 27, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-34.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-34.c
new file mode 100644
index 00000000000..66a82f20ca5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-34.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint16_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_9
+
+DEF_SAT_U_SUB_FMT_9(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 65535, 65534, 1, },
+ { 65535, 65535, 0, },
+ { 65534, 65535, 0, },
+ { 65533, 65534, 0, },
+ { 0, 65535, 0, },
+ { 1, 65535, 0, },
+ { 35, 5, 30, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-35.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-35.c
new file mode 100644
index 00000000000..a54b5c33bc1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-35.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint32_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_9
+
+DEF_SAT_U_SUB_FMT_9(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 4294967295, 4294967294, 1, },
+ { 4294967295, 4294967295, 0, },
+ { 4294967294, 4294967295, 0, },
+ { 4294967293, 4294967294, 0, },
+ { 1, 4294967295, 0, },
+ { 2, 4294967295, 0, },
+ { 5, 1, 4, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-36.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-36.c
new file mode 100644
index 00000000000..97943b3e3b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-36.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint64_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_9
+
+DEF_SAT_U_SUB_FMT_9(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 18446744073709551615u, 18446744073709551614u, 1, },
+ { 18446744073709551615u, 18446744073709551615u, 0, },
+ { 18446744073709551614u, 18446744073709551615u, 0, },
+ { 18446744073709551613u, 18446744073709551614u, 0, },
+ { 0, 18446744073709551615u, 0, },
+ { 1, 18446744073709551615u, 0, },
+ { 43, 11, 32, },
+};
+
+#include "scalar_sat_binary.h"
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v1 8/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 10
2024-06-14 2:13 [PATCH v1 1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3 pan2.li
` (5 preceding siblings ...)
2024-06-14 2:13 ` [PATCH v1 7/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 9 pan2.li
@ 2024-06-14 2:13 ` pan2.li
2024-06-14 2:24 ` juzhe.zhong
2024-06-14 2:24 ` [PATCH v1 1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3 juzhe.zhong
7 siblings, 1 reply; 17+ messages in thread
From: pan2.li @ 2024-06-14 2:13 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, jeffreyalaw, rdapp.gcc, Pan Li
From: Pan Li <pan2.li@intel.com>
After the middle-end support the form 10 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 10 of unsigned .SAT_SUB.
Form 10:
#define SAT_SUB_U_10(T) \
T sat_sub_u_10_##T (T x, T y) \
{ \
T ret; \
T overflow = __builtin_sub_overflow (x, y, &ret); \
return !overflow ? ret : 0; \
}
Passed the rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-37.c: New test.
* gcc.target/riscv/sat_u_sub-38.c: New test.
* gcc.target/riscv/sat_u_sub-39.c: New test.
* gcc.target/riscv/sat_u_sub-40.c: New test.
* gcc.target/riscv/sat_u_sub-run-37.c: New test.
* gcc.target/riscv/sat_u_sub-run-38.c: New test.
* gcc.target/riscv/sat_u_sub-run-39.c: New test.
* gcc.target/riscv/sat_u_sub-run-40.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 10 ++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-37.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-38.c | 19 ++++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-39.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-40.c | 17 +++++++++++++
.../gcc.target/riscv/sat_u_sub-run-37.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-38.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-39.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-40.c | 25 +++++++++++++++++++
9 files changed, 182 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-37.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-38.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-39.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-40.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-37.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-38.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-39.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-40.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index ecb74e56e9c..4c02783e845 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -147,6 +147,15 @@ sat_u_sub_##T##_fmt_9 (T x, T y) \
return overflow ? 0 : ret; \
}
+#define DEF_SAT_U_SUB_FMT_10(T) \
+T __attribute__((noinline)) \
+sat_u_sub_##T##_fmt_10 (T x, T y) \
+{ \
+ T ret; \
+ T overflow = __builtin_sub_overflow (x, y, &ret); \
+ return !overflow ? ret : 0; \
+}
+
#define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
#define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
#define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
@@ -156,6 +165,7 @@ sat_u_sub_##T##_fmt_9 (T x, T y) \
#define RUN_SAT_U_SUB_FMT_7(T, x, y) sat_u_sub_##T##_fmt_7(x, y)
#define RUN_SAT_U_SUB_FMT_8(T, x, y) sat_u_sub_##T##_fmt_8(x, y)
#define RUN_SAT_U_SUB_FMT_9(T, x, y) sat_u_sub_##T##_fmt_9(x, y)
+#define RUN_SAT_U_SUB_FMT_10(T, x, y) sat_u_sub_##T##_fmt_10(x, y)
#define DEF_VEC_SAT_U_SUB_FMT_1(T) \
void __attribute__((noinline)) \
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-37.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-37.c
new file mode 100644
index 00000000000..8c97a518d2c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-37.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint8_t_fmt_10:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_SUB_FMT_10(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-38.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-38.c
new file mode 100644
index 00000000000..7e3cec2a9a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-38.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint16_t_fmt_10:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_SUB_FMT_10(uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-39.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-39.c
new file mode 100644
index 00000000000..cd37f526abd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-39.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint32_t_fmt_10:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_SUB_FMT_10(uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-40.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-40.c
new file mode 100644
index 00000000000..165be897313
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-40.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint64_t_fmt_10:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+a0,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_SUB_FMT_10(uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-37.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-37.c
new file mode 100644
index 00000000000..2a157f027da
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-37.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint8_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_10
+
+DEF_SAT_U_SUB_FMT_10(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 255, 254, 1, },
+ { 255, 255, 0, },
+ { 254, 255, 0, },
+ { 253, 254, 0, },
+ { 0, 255, 0, },
+ { 1, 255, 0, },
+ { 32, 5, 27, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-38.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-38.c
new file mode 100644
index 00000000000..ae87544c9c4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-38.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint16_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_10
+
+DEF_SAT_U_SUB_FMT_10(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 65535, 65534, 1, },
+ { 65535, 65535, 0, },
+ { 65534, 65535, 0, },
+ { 65533, 65534, 0, },
+ { 0, 65535, 0, },
+ { 1, 65535, 0, },
+ { 35, 5, 30, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-39.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-39.c
new file mode 100644
index 00000000000..43414ae2d84
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-39.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint32_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_10
+
+DEF_SAT_U_SUB_FMT_10(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 4294967295, 4294967294, 1, },
+ { 4294967295, 4294967295, 0, },
+ { 4294967294, 4294967295, 0, },
+ { 4294967293, 4294967294, 0, },
+ { 1, 4294967295, 0, },
+ { 2, 4294967295, 0, },
+ { 5, 1, 4, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-40.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-40.c
new file mode 100644
index 00000000000..3ef70a19c58
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-40.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint64_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_10
+
+DEF_SAT_U_SUB_FMT_10(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 18446744073709551615u, 18446744073709551614u, 1, },
+ { 18446744073709551615u, 18446744073709551615u, 0, },
+ { 18446744073709551614u, 18446744073709551615u, 0, },
+ { 18446744073709551613u, 18446744073709551614u, 0, },
+ { 0, 18446744073709551615u, 0, },
+ { 1, 18446744073709551615u, 0, },
+ { 43, 11, 32, },
+};
+
+#include "scalar_sat_binary.h"
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v1 1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3
2024-06-14 2:13 [PATCH v1 1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3 pan2.li
` (6 preceding siblings ...)
2024-06-14 2:13 ` [PATCH v1 8/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 10 pan2.li
@ 2024-06-14 2:24 ` juzhe.zhong
2024-06-14 2:29 ` Li, Pan2
7 siblings, 1 reply; 17+ messages in thread
From: juzhe.zhong @ 2024-06-14 2:24 UTC (permalink / raw)
To: pan2.li, gcc-patches; +Cc: kito.cheng, jeffreyalaw, Robin Dapp, pan2.li
[-- Attachment #1: Type: text/plain, Size: 10803 bytes --]
LGTM
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2024-06-14 10:13
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3
From: Pan Li <pan2.li@intel.com>
After the middle-end support the form 3 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 3 of unsigned .SAT_SUB.
Form 3:
#define SAT_SUB_U_3(T) \
T sat_sub_u_3_##T (T x, T y) \
{ \
return x > y ? x - y : 0; \
}
Passed the rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-10.c: New test.
* gcc.target/riscv/sat_u_sub-11.c: New test.
* gcc.target/riscv/sat_u_sub-12.c: New test.
* gcc.target/riscv/sat_u_sub-9.c: New test.
* gcc.target/riscv/sat_u_sub-run-10.c: New test.
* gcc.target/riscv/sat_u_sub-run-11.c: New test.
* gcc.target/riscv/sat_u_sub-run-12.c: New test.
* gcc.target/riscv/sat_u_sub-run-9.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 8 ++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c | 19 ++++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c | 17 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-9.c | 18 +++++++++++++
.../gcc.target/riscv/sat_u_sub-run-10.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-11.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-12.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-9.c | 25 +++++++++++++++++++
9 files changed, 180 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-9.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-11.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-12.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-9.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index bc9a372b6df..50c65cdea49 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -92,8 +92,16 @@ sat_u_sub_##T##_fmt_2 (T x, T y) \
return (x - y) & (-(T)(x > y)); \
}
+#define DEF_SAT_U_SUB_FMT_3(T) \
+T __attribute__((noinline)) \
+sat_u_sub_##T##_fmt_3 (T x, T y) \
+{ \
+ return x > y ? x - y : 0; \
+}
+
#define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
#define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
+#define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
#define DEF_VEC_SAT_U_SUB_FMT_1(T) \
void __attribute__((noinline)) \
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c
new file mode 100644
index 00000000000..6e78164865f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint16_t_fmt_3:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_SUB_FMT_3(uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c
new file mode 100644
index 00000000000..84e34657f55
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint32_t_fmt_3:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_SUB_FMT_3(uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c
new file mode 100644
index 00000000000..eea282b21ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint64_t_fmt_3:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+a0,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_SUB_FMT_3(uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-9.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-9.c
new file mode 100644
index 00000000000..b24bf3eb549
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-9.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint8_t_fmt_3:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_SUB_FMT_3(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-10.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-10.c
new file mode 100644
index 00000000000..ea52ff4573e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-10.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint16_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_3
+
+DEF_SAT_U_SUB_FMT_3(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 65535, 65534, 1, },
+ { 65535, 65535, 0, },
+ { 65534, 65535, 0, },
+ { 65533, 65534, 0, },
+ { 0, 65535, 0, },
+ { 1, 65535, 0, },
+ { 35, 5, 30, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-11.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-11.c
new file mode 100644
index 00000000000..fdea8916ab3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-11.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint32_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_3
+
+DEF_SAT_U_SUB_FMT_3(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 4294967295, 4294967294, 1, },
+ { 4294967295, 4294967295, 0, },
+ { 4294967294, 4294967295, 0, },
+ { 4294967293, 4294967294, 0, },
+ { 1, 4294967295, 0, },
+ { 2, 4294967295, 0, },
+ { 5, 1, 4, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-12.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-12.c
new file mode 100644
index 00000000000..164ee77fb76
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-12.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint64_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_3
+
+DEF_SAT_U_SUB_FMT_3(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 18446744073709551615u, 18446744073709551614u, 1, },
+ { 18446744073709551615u, 18446744073709551615u, 0, },
+ { 18446744073709551614u, 18446744073709551615u, 0, },
+ { 18446744073709551613u, 18446744073709551614u, 0, },
+ { 0, 18446744073709551615u, 0, },
+ { 1, 18446744073709551615u, 0, },
+ { 43, 11, 32, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-9.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-9.c
new file mode 100644
index 00000000000..724adf92d3e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-9.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint8_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_3
+
+DEF_SAT_U_SUB_FMT_3(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 255, 254, 1, },
+ { 255, 255, 0, },
+ { 254, 255, 0, },
+ { 253, 254, 0, },
+ { 0, 255, 0, },
+ { 1, 255, 0, },
+ { 32, 5, 27, },
+};
+
+#include "scalar_sat_binary.h"
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v1 2/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 4
2024-06-14 2:13 ` [PATCH v1 2/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 4 pan2.li
@ 2024-06-14 2:24 ` juzhe.zhong
0 siblings, 0 replies; 17+ messages in thread
From: juzhe.zhong @ 2024-06-14 2:24 UTC (permalink / raw)
To: pan2.li, gcc-patches; +Cc: kito.cheng, jeffreyalaw, Robin Dapp, pan2.li
[-- Attachment #1: Type: text/plain, Size: 10875 bytes --]
LGTM
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2024-06-14 10:13
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 2/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 4
From: Pan Li <pan2.li@intel.com>
After the middle-end support the form 4 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 4 of unsigned .SAT_SUB.
Form 4:
#define SAT_SUB_U_4(T) \
T sat_sub_u_4_##T (T x, T y) \
{ \
return x >= y ? x - y : 0; \
}
Passed the rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-13.c: New test.
* gcc.target/riscv/sat_u_sub-14.c: New test.
* gcc.target/riscv/sat_u_sub-15.c: New test.
* gcc.target/riscv/sat_u_sub-16.c: New test.
* gcc.target/riscv/sat_u_sub-run-13.c: New test.
* gcc.target/riscv/sat_u_sub-run-14.c: New test.
* gcc.target/riscv/sat_u_sub-run-15.c: New test.
* gcc.target/riscv/sat_u_sub-run-16.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 8 ++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-13.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-14.c | 19 ++++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-15.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-16.c | 17 +++++++++++++
.../gcc.target/riscv/sat_u_sub-run-13.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-14.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-15.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-16.c | 25 +++++++++++++++++++
9 files changed, 180 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-13.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-14.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-15.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-16.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-13.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-14.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-15.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-16.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index 50c65cdea49..b2f8478d36b 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -99,9 +99,17 @@ sat_u_sub_##T##_fmt_3 (T x, T y) \
return x > y ? x - y : 0; \
}
+#define DEF_SAT_U_SUB_FMT_4(T) \
+T __attribute__((noinline)) \
+sat_u_sub_##T##_fmt_4 (T x, T y) \
+{ \
+ return x >= y ? x - y : 0; \
+}
+
#define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
#define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
#define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
+#define RUN_SAT_U_SUB_FMT_4(T, x, y) sat_u_sub_##T##_fmt_4(x, y)
#define DEF_VEC_SAT_U_SUB_FMT_1(T) \
void __attribute__((noinline)) \
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-13.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-13.c
new file mode 100644
index 00000000000..edb7017f9b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-13.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint8_t_fmt_4:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_SUB_FMT_4(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-14.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-14.c
new file mode 100644
index 00000000000..2aab9f65586
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-14.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint16_t_fmt_4:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_SUB_FMT_4(uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-15.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-15.c
new file mode 100644
index 00000000000..25ad702bf04
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-15.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint32_t_fmt_4:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_SUB_FMT_4(uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-16.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-16.c
new file mode 100644
index 00000000000..72c1931608f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-16.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint64_t_fmt_4:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+a0,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_SUB_FMT_4(uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-13.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-13.c
new file mode 100644
index 00000000000..c8ae7a6680d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-13.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint8_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_4
+
+DEF_SAT_U_SUB_FMT_4(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 255, 254, 1, },
+ { 255, 255, 0, },
+ { 254, 255, 0, },
+ { 253, 254, 0, },
+ { 0, 255, 0, },
+ { 1, 255, 0, },
+ { 32, 5, 27, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-14.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-14.c
new file mode 100644
index 00000000000..9b57861b578
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-14.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint16_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_4
+
+DEF_SAT_U_SUB_FMT_4(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 65535, 65534, 1, },
+ { 65535, 65535, 0, },
+ { 65534, 65535, 0, },
+ { 65533, 65534, 0, },
+ { 0, 65535, 0, },
+ { 1, 65535, 0, },
+ { 35, 5, 30, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-15.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-15.c
new file mode 100644
index 00000000000..df2eecef6fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-15.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint32_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_4
+
+DEF_SAT_U_SUB_FMT_4(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 4294967295, 4294967294, 1, },
+ { 4294967295, 4294967295, 0, },
+ { 4294967294, 4294967295, 0, },
+ { 4294967293, 4294967294, 0, },
+ { 1, 4294967295, 0, },
+ { 2, 4294967295, 0, },
+ { 5, 1, 4, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-16.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-16.c
new file mode 100644
index 00000000000..09e9ac38a83
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-16.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint64_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_4
+
+DEF_SAT_U_SUB_FMT_4(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 18446744073709551615u, 18446744073709551614u, 1, },
+ { 18446744073709551615u, 18446744073709551615u, 0, },
+ { 18446744073709551614u, 18446744073709551615u, 0, },
+ { 18446744073709551613u, 18446744073709551614u, 0, },
+ { 0, 18446744073709551615u, 0, },
+ { 1, 18446744073709551615u, 0, },
+ { 43, 11, 32, },
+};
+
+#include "scalar_sat_binary.h"
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v1 3/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 5
2024-06-14 2:13 ` [PATCH v1 3/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 5 pan2.li
@ 2024-06-14 2:24 ` juzhe.zhong
0 siblings, 0 replies; 17+ messages in thread
From: juzhe.zhong @ 2024-06-14 2:24 UTC (permalink / raw)
To: pan2.li, gcc-patches; +Cc: kito.cheng, jeffreyalaw, Robin Dapp, pan2.li
[-- Attachment #1: Type: text/plain, Size: 10941 bytes --]
LGTM
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2024-06-14 10:13
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 3/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 5
From: Pan Li <pan2.li@intel.com>
After the middle-end support the form 5 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 5 of unsigned .SAT_SUB.
Form 5:
#define SAT_SUB_U_5(T) \
T sat_sub_u_5_##T (T x, T y) \
{ \
return x < y ? 0 : x - y; \
}
Passed the rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-17.c: New test.
* gcc.target/riscv/sat_u_sub-18.c: New test.
* gcc.target/riscv/sat_u_sub-19.c: New test.
* gcc.target/riscv/sat_u_sub-20.c: New test.
* gcc.target/riscv/sat_u_sub-run-17.c: New test.
* gcc.target/riscv/sat_u_sub-run-18.c: New test.
* gcc.target/riscv/sat_u_sub-run-19.c: New test.
* gcc.target/riscv/sat_u_sub-run-20.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 8 ++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-17.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-18.c | 19 ++++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-19.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-20.c | 17 +++++++++++++
.../gcc.target/riscv/sat_u_sub-run-17.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-18.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-19.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-20.c | 25 +++++++++++++++++++
9 files changed, 180 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-17.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-18.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-19.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-20.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-17.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-18.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-19.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-20.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index b2f8478d36b..d08755dd861 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -106,10 +106,18 @@ sat_u_sub_##T##_fmt_4 (T x, T y) \
return x >= y ? x - y : 0; \
}
+#define DEF_SAT_U_SUB_FMT_5(T) \
+T __attribute__((noinline)) \
+sat_u_sub_##T##_fmt_5 (T x, T y) \
+{ \
+ return x < y ? 0 : x - y; \
+}
+
#define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
#define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
#define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
#define RUN_SAT_U_SUB_FMT_4(T, x, y) sat_u_sub_##T##_fmt_4(x, y)
+#define RUN_SAT_U_SUB_FMT_5(T, x, y) sat_u_sub_##T##_fmt_5(x, y)
#define DEF_VEC_SAT_U_SUB_FMT_1(T) \
void __attribute__((noinline)) \
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-17.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-17.c
new file mode 100644
index 00000000000..853ddcfd285
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-17.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint8_t_fmt_5:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_SUB_FMT_5(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-18.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-18.c
new file mode 100644
index 00000000000..423a6f82170
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-18.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint16_t_fmt_5:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_SUB_FMT_5(uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-19.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-19.c
new file mode 100644
index 00000000000..29b9c235d97
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-19.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint32_t_fmt_5:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_SUB_FMT_5(uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-20.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-20.c
new file mode 100644
index 00000000000..89e84d60f94
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-20.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint64_t_fmt_5:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+a0,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_SUB_FMT_5(uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-17.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-17.c
new file mode 100644
index 00000000000..b2823112b62
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-17.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint8_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_5
+
+DEF_SAT_U_SUB_FMT_5(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 255, 254, 1, },
+ { 255, 255, 0, },
+ { 254, 255, 0, },
+ { 253, 254, 0, },
+ { 0, 255, 0, },
+ { 1, 255, 0, },
+ { 32, 5, 27, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-18.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-18.c
new file mode 100644
index 00000000000..9f575a47bfe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-18.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint16_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_5
+
+DEF_SAT_U_SUB_FMT_5(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 65535, 65534, 1, },
+ { 65535, 65535, 0, },
+ { 65534, 65535, 0, },
+ { 65533, 65534, 0, },
+ { 0, 65535, 0, },
+ { 1, 65535, 0, },
+ { 35, 5, 30, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-19.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-19.c
new file mode 100644
index 00000000000..c370455c3d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-19.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint32_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_5
+
+DEF_SAT_U_SUB_FMT_5(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 4294967295, 4294967294, 1, },
+ { 4294967295, 4294967295, 0, },
+ { 4294967294, 4294967295, 0, },
+ { 4294967293, 4294967294, 0, },
+ { 1, 4294967295, 0, },
+ { 2, 4294967295, 0, },
+ { 5, 1, 4, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-20.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-20.c
new file mode 100644
index 00000000000..22d82f973d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-20.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint64_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_5
+
+DEF_SAT_U_SUB_FMT_5(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 18446744073709551615u, 18446744073709551614u, 1, },
+ { 18446744073709551615u, 18446744073709551615u, 0, },
+ { 18446744073709551614u, 18446744073709551615u, 0, },
+ { 18446744073709551613u, 18446744073709551614u, 0, },
+ { 0, 18446744073709551615u, 0, },
+ { 1, 18446744073709551615u, 0, },
+ { 43, 11, 32, },
+};
+
+#include "scalar_sat_binary.h"
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v1 4/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 6
2024-06-14 2:13 ` [PATCH v1 4/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 6 pan2.li
@ 2024-06-14 2:24 ` juzhe.zhong
0 siblings, 0 replies; 17+ messages in thread
From: juzhe.zhong @ 2024-06-14 2:24 UTC (permalink / raw)
To: pan2.li, gcc-patches; +Cc: kito.cheng, jeffreyalaw, Robin Dapp, pan2.li
[-- Attachment #1: Type: text/plain, Size: 10962 bytes --]
LGTM
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2024-06-14 10:13
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 4/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 6
From: Pan Li <pan2.li@intel.com>
After the middle-end support the form 6 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 6 of unsigned .SAT_SUB.
Form 6:
#define SAT_SUB_U_6(T) \
T sat_sub_u_6_##T (T x, T y) \
{ \
return x <= y ? 0 : x - y; \
}
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-21.c: New test.
* gcc.target/riscv/sat_u_sub-22.c: New test.
* gcc.target/riscv/sat_u_sub-23.c: New test.
* gcc.target/riscv/sat_u_sub-24.c: New test.
* gcc.target/riscv/sat_u_sub-run-21.c: New test.
* gcc.target/riscv/sat_u_sub-run-22.c: New test.
* gcc.target/riscv/sat_u_sub-run-23.c: New test.
* gcc.target/riscv/sat_u_sub-run-24.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 8 ++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-21.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-22.c | 19 ++++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-23.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-24.c | 17 +++++++++++++
.../gcc.target/riscv/sat_u_sub-run-21.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-22.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-23.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-24.c | 25 +++++++++++++++++++
9 files changed, 180 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-21.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-22.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-23.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-24.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-21.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-22.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-23.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-24.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index d08755dd861..4296235cf62 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -113,11 +113,19 @@ sat_u_sub_##T##_fmt_5 (T x, T y) \
return x < y ? 0 : x - y; \
}
+#define DEF_SAT_U_SUB_FMT_6(T) \
+T __attribute__((noinline)) \
+sat_u_sub_##T##_fmt_6 (T x, T y) \
+{ \
+ return x <= y ? 0 : x - y; \
+}
+
#define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
#define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
#define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
#define RUN_SAT_U_SUB_FMT_4(T, x, y) sat_u_sub_##T##_fmt_4(x, y)
#define RUN_SAT_U_SUB_FMT_5(T, x, y) sat_u_sub_##T##_fmt_5(x, y)
+#define RUN_SAT_U_SUB_FMT_6(T, x, y) sat_u_sub_##T##_fmt_6(x, y)
#define DEF_VEC_SAT_U_SUB_FMT_1(T) \
void __attribute__((noinline)) \
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-21.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-21.c
new file mode 100644
index 00000000000..9a8fb7f1c91
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-21.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint8_t_fmt_6:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_SUB_FMT_6(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-22.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-22.c
new file mode 100644
index 00000000000..6182169edc5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-22.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint16_t_fmt_6:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_SUB_FMT_6(uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-23.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-23.c
new file mode 100644
index 00000000000..820110cdbb0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-23.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint32_t_fmt_6:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_SUB_FMT_6(uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-24.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-24.c
new file mode 100644
index 00000000000..48e6296e315
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-24.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint64_t_fmt_6:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+a0,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_SUB_FMT_6(uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-21.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-21.c
new file mode 100644
index 00000000000..0b4cbdbf599
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-21.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint8_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_6
+
+DEF_SAT_U_SUB_FMT_6(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 255, 254, 1, },
+ { 255, 255, 0, },
+ { 254, 255, 0, },
+ { 253, 254, 0, },
+ { 0, 255, 0, },
+ { 1, 255, 0, },
+ { 32, 5, 27, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-22.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-22.c
new file mode 100644
index 00000000000..e0dda451775
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-22.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint16_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_6
+
+DEF_SAT_U_SUB_FMT_6(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 65535, 65534, 1, },
+ { 65535, 65535, 0, },
+ { 65534, 65535, 0, },
+ { 65533, 65534, 0, },
+ { 0, 65535, 0, },
+ { 1, 65535, 0, },
+ { 35, 5, 30, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-23.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-23.c
new file mode 100644
index 00000000000..dfd95ef58c3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-23.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint32_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_6
+
+DEF_SAT_U_SUB_FMT_6(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 4294967295, 4294967294, 1, },
+ { 4294967295, 4294967295, 0, },
+ { 4294967294, 4294967295, 0, },
+ { 4294967293, 4294967294, 0, },
+ { 1, 4294967295, 0, },
+ { 2, 4294967295, 0, },
+ { 5, 1, 4, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-24.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-24.c
new file mode 100644
index 00000000000..7cac446aa33
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-24.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint64_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_6
+
+DEF_SAT_U_SUB_FMT_6(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 18446744073709551615u, 18446744073709551614u, 1, },
+ { 18446744073709551615u, 18446744073709551615u, 0, },
+ { 18446744073709551614u, 18446744073709551615u, 0, },
+ { 18446744073709551613u, 18446744073709551614u, 0, },
+ { 0, 18446744073709551615u, 0, },
+ { 1, 18446744073709551615u, 0, },
+ { 43, 11, 32, },
+};
+
+#include "scalar_sat_binary.h"
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v1 5/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 7
2024-06-14 2:13 ` [PATCH v1 5/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 7 pan2.li
@ 2024-06-14 2:24 ` juzhe.zhong
0 siblings, 0 replies; 17+ messages in thread
From: juzhe.zhong @ 2024-06-14 2:24 UTC (permalink / raw)
To: pan2.li, gcc-patches; +Cc: kito.cheng, jeffreyalaw, Robin Dapp, pan2.li
[-- Attachment #1: Type: text/plain, Size: 11359 bytes --]
LGTM
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2024-06-14 10:13
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 5/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 7
From: Pan Li <pan2.li@intel.com>
After the middle-end support the form 7 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 7 of unsigned .SAT_SUB.
Form 7:
#define SAT_SUB_U_7(T) \
T sat_sub_u_7_##T (T x, T y) \
{ \
T ret; \
T overflow = __builtin_sub_overflow (x, y, &ret); \
return ret & (T)(overflow - 1); \
}
Passed the rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-25.c: New test.
* gcc.target/riscv/sat_u_sub-26.c: New test.
* gcc.target/riscv/sat_u_sub-27.c: New test.
* gcc.target/riscv/sat_u_sub-28.c: New test.
* gcc.target/riscv/sat_u_sub-run-25.c: New test.
* gcc.target/riscv/sat_u_sub-run-26.c: New test.
* gcc.target/riscv/sat_u_sub-run-27.c: New test.
* gcc.target/riscv/sat_u_sub-run-28.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 10 ++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-25.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-26.c | 19 ++++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-27.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-28.c | 17 +++++++++++++
.../gcc.target/riscv/sat_u_sub-run-25.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-26.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-27.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-28.c | 25 +++++++++++++++++++
9 files changed, 182 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-25.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-26.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-27.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-28.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-25.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-26.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-27.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-28.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index 4296235cf62..bde054d5c9d 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -120,12 +120,22 @@ sat_u_sub_##T##_fmt_6 (T x, T y) \
return x <= y ? 0 : x - y; \
}
+#define DEF_SAT_U_SUB_FMT_7(T) \
+T __attribute__((noinline)) \
+sat_u_sub_##T##_fmt_7 (T x, T y) \
+{ \
+ T ret; \
+ T overflow = __builtin_sub_overflow (x, y, &ret); \
+ return ret & (T)(overflow - 1); \
+}
+
#define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
#define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
#define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
#define RUN_SAT_U_SUB_FMT_4(T, x, y) sat_u_sub_##T##_fmt_4(x, y)
#define RUN_SAT_U_SUB_FMT_5(T, x, y) sat_u_sub_##T##_fmt_5(x, y)
#define RUN_SAT_U_SUB_FMT_6(T, x, y) sat_u_sub_##T##_fmt_6(x, y)
+#define RUN_SAT_U_SUB_FMT_7(T, x, y) sat_u_sub_##T##_fmt_7(x, y)
#define DEF_VEC_SAT_U_SUB_FMT_1(T) \
void __attribute__((noinline)) \
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-25.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-25.c
new file mode 100644
index 00000000000..8780ef0c8f1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-25.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint8_t_fmt_7:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_SUB_FMT_7(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-26.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-26.c
new file mode 100644
index 00000000000..f720f619d09
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-26.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint16_t_fmt_7:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_SUB_FMT_7(uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-27.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-27.c
new file mode 100644
index 00000000000..779c9247e02
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-27.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint32_t_fmt_7:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_SUB_FMT_7(uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-28.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-28.c
new file mode 100644
index 00000000000..86b80dbccd5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-28.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint64_t_fmt_7:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+a0,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_SUB_FMT_7(uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-25.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-25.c
new file mode 100644
index 00000000000..d101d2897c9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-25.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint8_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_7
+
+DEF_SAT_U_SUB_FMT_7(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 255, 254, 1, },
+ { 255, 255, 0, },
+ { 254, 255, 0, },
+ { 253, 254, 0, },
+ { 0, 255, 0, },
+ { 1, 255, 0, },
+ { 32, 5, 27, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-26.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-26.c
new file mode 100644
index 00000000000..10c65fec97d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-26.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint16_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_7
+
+DEF_SAT_U_SUB_FMT_7(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 65535, 65534, 1, },
+ { 65535, 65535, 0, },
+ { 65534, 65535, 0, },
+ { 65533, 65534, 0, },
+ { 0, 65535, 0, },
+ { 1, 65535, 0, },
+ { 35, 5, 30, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-27.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-27.c
new file mode 100644
index 00000000000..e3b4dde683d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-27.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint32_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_7
+
+DEF_SAT_U_SUB_FMT_7(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 4294967295, 4294967294, 1, },
+ { 4294967295, 4294967295, 0, },
+ { 4294967294, 4294967295, 0, },
+ { 4294967293, 4294967294, 0, },
+ { 1, 4294967295, 0, },
+ { 2, 4294967295, 0, },
+ { 5, 1, 4, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-28.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-28.c
new file mode 100644
index 00000000000..6e93fcff032
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-28.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint64_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_7
+
+DEF_SAT_U_SUB_FMT_7(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 18446744073709551615u, 18446744073709551614u, 1, },
+ { 18446744073709551615u, 18446744073709551615u, 0, },
+ { 18446744073709551614u, 18446744073709551615u, 0, },
+ { 18446744073709551613u, 18446744073709551614u, 0, },
+ { 0, 18446744073709551615u, 0, },
+ { 1, 18446744073709551615u, 0, },
+ { 43, 11, 32, },
+};
+
+#include "scalar_sat_binary.h"
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v1 6/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 8
2024-06-14 2:13 ` [PATCH v1 6/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 8 pan2.li
@ 2024-06-14 2:24 ` juzhe.zhong
0 siblings, 0 replies; 17+ messages in thread
From: juzhe.zhong @ 2024-06-14 2:24 UTC (permalink / raw)
To: pan2.li, gcc-patches; +Cc: kito.cheng, jeffreyalaw, Robin Dapp, pan2.li
[-- Attachment #1: Type: text/plain, Size: 11469 bytes --]
LGTM
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2024-06-14 10:13
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 6/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 8
From: Pan Li <pan2.li@intel.com>
After the middle-end support the form 8 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 8 of unsigned .SAT_SUB.
Form 8:
#define SAT_SUB_U_8(T) \
T sat_sub_u_8_##T (T x, T y) \
{ \
T ret; \
T overflow = __builtin_sub_overflow (x, y, &ret); \
return ret & (T)-(!overflow); \
}
Passed the rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-29.c: New test.
* gcc.target/riscv/sat_u_sub-30.c: New test.
* gcc.target/riscv/sat_u_sub-31.c: New test.
* gcc.target/riscv/sat_u_sub-32.c: New test.
* gcc.target/riscv/sat_u_sub-run-29.c: New test.
* gcc.target/riscv/sat_u_sub-run-30.c: New test.
* gcc.target/riscv/sat_u_sub-run-31.c: New test.
* gcc.target/riscv/sat_u_sub-run-32.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 10 ++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-29.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-30.c | 19 ++++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-31.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-32.c | 17 +++++++++++++
.../gcc.target/riscv/sat_u_sub-run-29.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-30.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-31.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-32.c | 25 +++++++++++++++++++
9 files changed, 182 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-29.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-30.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-31.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-29.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-30.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-31.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-32.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index bde054d5c9d..9f901de5cdf 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -129,6 +129,15 @@ sat_u_sub_##T##_fmt_7 (T x, T y) \
return ret & (T)(overflow - 1); \
}
+#define DEF_SAT_U_SUB_FMT_8(T) \
+T __attribute__((noinline)) \
+sat_u_sub_##T##_fmt_8 (T x, T y) \
+{ \
+ T ret; \
+ T overflow = __builtin_sub_overflow (x, y, &ret); \
+ return ret & (T)-(!overflow); \
+}
+
#define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
#define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
#define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
@@ -136,6 +145,7 @@ sat_u_sub_##T##_fmt_7 (T x, T y) \
#define RUN_SAT_U_SUB_FMT_5(T, x, y) sat_u_sub_##T##_fmt_5(x, y)
#define RUN_SAT_U_SUB_FMT_6(T, x, y) sat_u_sub_##T##_fmt_6(x, y)
#define RUN_SAT_U_SUB_FMT_7(T, x, y) sat_u_sub_##T##_fmt_7(x, y)
+#define RUN_SAT_U_SUB_FMT_8(T, x, y) sat_u_sub_##T##_fmt_8(x, y)
#define DEF_VEC_SAT_U_SUB_FMT_1(T) \
void __attribute__((noinline)) \
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-29.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-29.c
new file mode 100644
index 00000000000..1a2da50256e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-29.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint8_t_fmt_8:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_SUB_FMT_8(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-30.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-30.c
new file mode 100644
index 00000000000..75aa7506369
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-30.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint16_t_fmt_8:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_SUB_FMT_8(uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-31.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-31.c
new file mode 100644
index 00000000000..bc935ea0f3d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-31.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint32_t_fmt_8:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_SUB_FMT_8(uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-32.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-32.c
new file mode 100644
index 00000000000..f0f2254182c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-32.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint64_t_fmt_8:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+a0,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_SUB_FMT_8(uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-29.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-29.c
new file mode 100644
index 00000000000..1f74562125b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-29.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint8_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_8
+
+DEF_SAT_U_SUB_FMT_8(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 255, 254, 1, },
+ { 255, 255, 0, },
+ { 254, 255, 0, },
+ { 253, 254, 0, },
+ { 0, 255, 0, },
+ { 1, 255, 0, },
+ { 32, 5, 27, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-30.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-30.c
new file mode 100644
index 00000000000..4e50e3f804e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-30.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint16_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_8
+
+DEF_SAT_U_SUB_FMT_8(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 65535, 65534, 1, },
+ { 65535, 65535, 0, },
+ { 65534, 65535, 0, },
+ { 65533, 65534, 0, },
+ { 0, 65535, 0, },
+ { 1, 65535, 0, },
+ { 35, 5, 30, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-31.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-31.c
new file mode 100644
index 00000000000..3c8f78d7ed3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-31.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint32_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_8
+
+DEF_SAT_U_SUB_FMT_8(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 4294967295, 4294967294, 1, },
+ { 4294967295, 4294967295, 0, },
+ { 4294967294, 4294967295, 0, },
+ { 4294967293, 4294967294, 0, },
+ { 1, 4294967295, 0, },
+ { 2, 4294967295, 0, },
+ { 5, 1, 4, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-32.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-32.c
new file mode 100644
index 00000000000..932596a28e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-32.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint64_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_8
+
+DEF_SAT_U_SUB_FMT_8(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 18446744073709551615u, 18446744073709551614u, 1, },
+ { 18446744073709551615u, 18446744073709551615u, 0, },
+ { 18446744073709551614u, 18446744073709551615u, 0, },
+ { 18446744073709551613u, 18446744073709551614u, 0, },
+ { 0, 18446744073709551615u, 0, },
+ { 1, 18446744073709551615u, 0, },
+ { 43, 11, 32, },
+};
+
+#include "scalar_sat_binary.h"
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v1 7/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 9
2024-06-14 2:13 ` [PATCH v1 7/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 9 pan2.li
@ 2024-06-14 2:24 ` juzhe.zhong
0 siblings, 0 replies; 17+ messages in thread
From: juzhe.zhong @ 2024-06-14 2:24 UTC (permalink / raw)
To: pan2.li, gcc-patches; +Cc: kito.cheng, jeffreyalaw, Robin Dapp, pan2.li
[-- Attachment #1: Type: text/plain, Size: 11466 bytes --]
LGTM
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2024-06-14 10:13
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 7/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 9
From: Pan Li <pan2.li@intel.com>
After the middle-end support the form 9 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 9 of unsigned .SAT_SUB.
Form 9:
#define SAT_SUB_U_9(T) \
T sat_sub_u_9_##T (T x, T y) \
{ \
T ret; \
T overflow = __builtin_sub_overflow (x, y, &ret); \
return overflow ? 0 : ret; \
}
Passed the rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-33.c: New test.
* gcc.target/riscv/sat_u_sub-34.c: New test.
* gcc.target/riscv/sat_u_sub-35.c: New test.
* gcc.target/riscv/sat_u_sub-36.c: New test.
* gcc.target/riscv/sat_u_sub-run-33.c: New test.
* gcc.target/riscv/sat_u_sub-run-34.c: New test.
* gcc.target/riscv/sat_u_sub-run-35.c: New test.
* gcc.target/riscv/sat_u_sub-run-36.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 10 ++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-33.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-34.c | 19 ++++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-35.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-36.c | 17 +++++++++++++
.../gcc.target/riscv/sat_u_sub-run-33.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-34.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-35.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-36.c | 25 +++++++++++++++++++
9 files changed, 182 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-33.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-34.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-35.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-36.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-33.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-34.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-35.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-36.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index 9f901de5cdf..ecb74e56e9c 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -138,6 +138,15 @@ sat_u_sub_##T##_fmt_8 (T x, T y) \
return ret & (T)-(!overflow); \
}
+#define DEF_SAT_U_SUB_FMT_9(T) \
+T __attribute__((noinline)) \
+sat_u_sub_##T##_fmt_9 (T x, T y) \
+{ \
+ T ret; \
+ T overflow = __builtin_sub_overflow (x, y, &ret); \
+ return overflow ? 0 : ret; \
+}
+
#define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
#define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
#define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
@@ -146,6 +155,7 @@ sat_u_sub_##T##_fmt_8 (T x, T y) \
#define RUN_SAT_U_SUB_FMT_6(T, x, y) sat_u_sub_##T##_fmt_6(x, y)
#define RUN_SAT_U_SUB_FMT_7(T, x, y) sat_u_sub_##T##_fmt_7(x, y)
#define RUN_SAT_U_SUB_FMT_8(T, x, y) sat_u_sub_##T##_fmt_8(x, y)
+#define RUN_SAT_U_SUB_FMT_9(T, x, y) sat_u_sub_##T##_fmt_9(x, y)
#define DEF_VEC_SAT_U_SUB_FMT_1(T) \
void __attribute__((noinline)) \
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-33.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-33.c
new file mode 100644
index 00000000000..aca4bd28b5d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-33.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint8_t_fmt_9:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_SUB_FMT_9(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-34.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-34.c
new file mode 100644
index 00000000000..f87a51a504b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-34.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint16_t_fmt_9:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_SUB_FMT_9(uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-35.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-35.c
new file mode 100644
index 00000000000..13c3e922f14
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-35.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint32_t_fmt_9:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_SUB_FMT_9(uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-36.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-36.c
new file mode 100644
index 00000000000..0254f539e09
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-36.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint64_t_fmt_9:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+a0,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_SUB_FMT_9(uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-33.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-33.c
new file mode 100644
index 00000000000..ab8b4750d01
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-33.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint8_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_9
+
+DEF_SAT_U_SUB_FMT_9(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 255, 254, 1, },
+ { 255, 255, 0, },
+ { 254, 255, 0, },
+ { 253, 254, 0, },
+ { 0, 255, 0, },
+ { 1, 255, 0, },
+ { 32, 5, 27, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-34.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-34.c
new file mode 100644
index 00000000000..66a82f20ca5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-34.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint16_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_9
+
+DEF_SAT_U_SUB_FMT_9(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 65535, 65534, 1, },
+ { 65535, 65535, 0, },
+ { 65534, 65535, 0, },
+ { 65533, 65534, 0, },
+ { 0, 65535, 0, },
+ { 1, 65535, 0, },
+ { 35, 5, 30, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-35.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-35.c
new file mode 100644
index 00000000000..a54b5c33bc1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-35.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint32_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_9
+
+DEF_SAT_U_SUB_FMT_9(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 4294967295, 4294967294, 1, },
+ { 4294967295, 4294967295, 0, },
+ { 4294967294, 4294967295, 0, },
+ { 4294967293, 4294967294, 0, },
+ { 1, 4294967295, 0, },
+ { 2, 4294967295, 0, },
+ { 5, 1, 4, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-36.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-36.c
new file mode 100644
index 00000000000..97943b3e3b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-36.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint64_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_9
+
+DEF_SAT_U_SUB_FMT_9(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 18446744073709551615u, 18446744073709551614u, 1, },
+ { 18446744073709551615u, 18446744073709551615u, 0, },
+ { 18446744073709551614u, 18446744073709551615u, 0, },
+ { 18446744073709551613u, 18446744073709551614u, 0, },
+ { 0, 18446744073709551615u, 0, },
+ { 1, 18446744073709551615u, 0, },
+ { 43, 11, 32, },
+};
+
+#include "scalar_sat_binary.h"
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v1 8/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 10
2024-06-14 2:13 ` [PATCH v1 8/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 10 pan2.li
@ 2024-06-14 2:24 ` juzhe.zhong
0 siblings, 0 replies; 17+ messages in thread
From: juzhe.zhong @ 2024-06-14 2:24 UTC (permalink / raw)
To: pan2.li, gcc-patches; +Cc: kito.cheng, jeffreyalaw, Robin Dapp, pan2.li
[-- Attachment #1: Type: text/plain, Size: 11491 bytes --]
LGTM
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2024-06-14 10:13
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 8/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 10
From: Pan Li <pan2.li@intel.com>
After the middle-end support the form 10 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 10 of unsigned .SAT_SUB.
Form 10:
#define SAT_SUB_U_10(T) \
T sat_sub_u_10_##T (T x, T y) \
{ \
T ret; \
T overflow = __builtin_sub_overflow (x, y, &ret); \
return !overflow ? ret : 0; \
}
Passed the rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-37.c: New test.
* gcc.target/riscv/sat_u_sub-38.c: New test.
* gcc.target/riscv/sat_u_sub-39.c: New test.
* gcc.target/riscv/sat_u_sub-40.c: New test.
* gcc.target/riscv/sat_u_sub-run-37.c: New test.
* gcc.target/riscv/sat_u_sub-run-38.c: New test.
* gcc.target/riscv/sat_u_sub-run-39.c: New test.
* gcc.target/riscv/sat_u_sub-run-40.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 10 ++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-37.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-38.c | 19 ++++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-39.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-40.c | 17 +++++++++++++
.../gcc.target/riscv/sat_u_sub-run-37.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-38.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-39.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-40.c | 25 +++++++++++++++++++
9 files changed, 182 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-37.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-38.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-39.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-40.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-37.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-38.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-39.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-40.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index ecb74e56e9c..4c02783e845 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -147,6 +147,15 @@ sat_u_sub_##T##_fmt_9 (T x, T y) \
return overflow ? 0 : ret; \
}
+#define DEF_SAT_U_SUB_FMT_10(T) \
+T __attribute__((noinline)) \
+sat_u_sub_##T##_fmt_10 (T x, T y) \
+{ \
+ T ret; \
+ T overflow = __builtin_sub_overflow (x, y, &ret); \
+ return !overflow ? ret : 0; \
+}
+
#define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
#define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
#define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
@@ -156,6 +165,7 @@ sat_u_sub_##T##_fmt_9 (T x, T y) \
#define RUN_SAT_U_SUB_FMT_7(T, x, y) sat_u_sub_##T##_fmt_7(x, y)
#define RUN_SAT_U_SUB_FMT_8(T, x, y) sat_u_sub_##T##_fmt_8(x, y)
#define RUN_SAT_U_SUB_FMT_9(T, x, y) sat_u_sub_##T##_fmt_9(x, y)
+#define RUN_SAT_U_SUB_FMT_10(T, x, y) sat_u_sub_##T##_fmt_10(x, y)
#define DEF_VEC_SAT_U_SUB_FMT_1(T) \
void __attribute__((noinline)) \
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-37.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-37.c
new file mode 100644
index 00000000000..8c97a518d2c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-37.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint8_t_fmt_10:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_SUB_FMT_10(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-38.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-38.c
new file mode 100644
index 00000000000..7e3cec2a9a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-38.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint16_t_fmt_10:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_SUB_FMT_10(uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-39.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-39.c
new file mode 100644
index 00000000000..cd37f526abd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-39.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint32_t_fmt_10:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_SUB_FMT_10(uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-40.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-40.c
new file mode 100644
index 00000000000..165be897313
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-40.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint64_t_fmt_10:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+a0,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_SUB_FMT_10(uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-37.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-37.c
new file mode 100644
index 00000000000..2a157f027da
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-37.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint8_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_10
+
+DEF_SAT_U_SUB_FMT_10(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 255, 254, 1, },
+ { 255, 255, 0, },
+ { 254, 255, 0, },
+ { 253, 254, 0, },
+ { 0, 255, 0, },
+ { 1, 255, 0, },
+ { 32, 5, 27, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-38.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-38.c
new file mode 100644
index 00000000000..ae87544c9c4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-38.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint16_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_10
+
+DEF_SAT_U_SUB_FMT_10(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 65535, 65534, 1, },
+ { 65535, 65535, 0, },
+ { 65534, 65535, 0, },
+ { 65533, 65534, 0, },
+ { 0, 65535, 0, },
+ { 1, 65535, 0, },
+ { 35, 5, 30, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-39.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-39.c
new file mode 100644
index 00000000000..43414ae2d84
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-39.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint32_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_10
+
+DEF_SAT_U_SUB_FMT_10(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 4294967295, 4294967294, 1, },
+ { 4294967295, 4294967295, 0, },
+ { 4294967294, 4294967295, 0, },
+ { 4294967293, 4294967294, 0, },
+ { 1, 4294967295, 0, },
+ { 2, 4294967295, 0, },
+ { 5, 1, 4, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-40.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-40.c
new file mode 100644
index 00000000000..3ef70a19c58
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-40.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint64_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_10
+
+DEF_SAT_U_SUB_FMT_10(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 18446744073709551615u, 18446744073709551614u, 1, },
+ { 18446744073709551615u, 18446744073709551615u, 0, },
+ { 18446744073709551614u, 18446744073709551615u, 0, },
+ { 18446744073709551613u, 18446744073709551614u, 0, },
+ { 0, 18446744073709551615u, 0, },
+ { 1, 18446744073709551615u, 0, },
+ { 43, 11, 32, },
+};
+
+#include "scalar_sat_binary.h"
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* RE: [PATCH v1 1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3
2024-06-14 2:24 ` [PATCH v1 1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3 juzhe.zhong
@ 2024-06-14 2:29 ` Li, Pan2
0 siblings, 0 replies; 17+ messages in thread
From: Li, Pan2 @ 2024-06-14 2:29 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches; +Cc: kito.cheng, jeffreyalaw, Robin Dapp
[-- Attachment #1: Type: text/plain, Size: 11568 bytes --]
Thanks Juzhe, will commit the series after the middle-end patch.
Pan
From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Friday, June 14, 2024 10:24 AM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: kito.cheng <kito.cheng@gmail.com>; jeffreyalaw <jeffreyalaw@gmail.com>; Robin Dapp <rdapp.gcc@gmail.com>; Li, Pan2 <pan2.li@intel.com>
Subject: Re: [PATCH v1 1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3
LGTM
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: pan2.li<mailto:pan2.li@intel.com>
Date: 2024-06-14 10:13
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; kito.cheng<mailto:kito.cheng@gmail.com>; jeffreyalaw<mailto:jeffreyalaw@gmail.com>; rdapp.gcc<mailto:rdapp.gcc@gmail.com>; Pan Li<mailto:pan2.li@intel.com>
Subject: [PATCH v1 1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
After the middle-end support the form 3 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 3 of unsigned .SAT_SUB.
Form 3:
#define SAT_SUB_U_3(T) \
T sat_sub_u_3_##T (T x, T y) \
{ \
return x > y ? x - y : 0; \
}
Passed the rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-10.c: New test.
* gcc.target/riscv/sat_u_sub-11.c: New test.
* gcc.target/riscv/sat_u_sub-12.c: New test.
* gcc.target/riscv/sat_u_sub-9.c: New test.
* gcc.target/riscv/sat_u_sub-run-10.c: New test.
* gcc.target/riscv/sat_u_sub-run-11.c: New test.
* gcc.target/riscv/sat_u_sub-run-12.c: New test.
* gcc.target/riscv/sat_u_sub-run-9.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 8 ++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c | 19 ++++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c | 17 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-9.c | 18 +++++++++++++
.../gcc.target/riscv/sat_u_sub-run-10.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-11.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-12.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-9.c | 25 +++++++++++++++++++
9 files changed, 180 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-9.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-11.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-12.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-9.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index bc9a372b6df..50c65cdea49 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -92,8 +92,16 @@ sat_u_sub_##T##_fmt_2 (T x, T y) \
return (x - y) & (-(T)(x > y)); \
}
+#define DEF_SAT_U_SUB_FMT_3(T) \
+T __attribute__((noinline)) \
+sat_u_sub_##T##_fmt_3 (T x, T y) \
+{ \
+ return x > y ? x - y : 0; \
+}
+
#define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
#define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
+#define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
#define DEF_VEC_SAT_U_SUB_FMT_1(T) \
void __attribute__((noinline)) \
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c
new file mode 100644
index 00000000000..6e78164865f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint16_t_fmt_3:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_SUB_FMT_3(uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c
new file mode 100644
index 00000000000..84e34657f55
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint32_t_fmt_3:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_SUB_FMT_3(uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c
new file mode 100644
index 00000000000..eea282b21ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint64_t_fmt_3:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+a0,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_SUB_FMT_3(uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-9.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-9.c
new file mode 100644
index 00000000000..b24bf3eb549
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-9.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint8_t_fmt_3:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_SUB_FMT_3(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-10.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-10.c
new file mode 100644
index 00000000000..ea52ff4573e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-10.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint16_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_3
+
+DEF_SAT_U_SUB_FMT_3(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 65535, 65534, 1, },
+ { 65535, 65535, 0, },
+ { 65534, 65535, 0, },
+ { 65533, 65534, 0, },
+ { 0, 65535, 0, },
+ { 1, 65535, 0, },
+ { 35, 5, 30, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-11.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-11.c
new file mode 100644
index 00000000000..fdea8916ab3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-11.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint32_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_3
+
+DEF_SAT_U_SUB_FMT_3(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 4294967295, 4294967294, 1, },
+ { 4294967295, 4294967295, 0, },
+ { 4294967294, 4294967295, 0, },
+ { 4294967293, 4294967294, 0, },
+ { 1, 4294967295, 0, },
+ { 2, 4294967295, 0, },
+ { 5, 1, 4, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-12.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-12.c
new file mode 100644
index 00000000000..164ee77fb76
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-12.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint64_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_3
+
+DEF_SAT_U_SUB_FMT_3(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 18446744073709551615u, 18446744073709551614u, 1, },
+ { 18446744073709551615u, 18446744073709551615u, 0, },
+ { 18446744073709551614u, 18446744073709551615u, 0, },
+ { 18446744073709551613u, 18446744073709551614u, 0, },
+ { 0, 18446744073709551615u, 0, },
+ { 1, 18446744073709551615u, 0, },
+ { 43, 11, 32, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-9.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-9.c
new file mode 100644
index 00000000000..724adf92d3e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-9.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint8_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_3
+
+DEF_SAT_U_SUB_FMT_3(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 255, 254, 1, },
+ { 255, 255, 0, },
+ { 254, 255, 0, },
+ { 253, 254, 0, },
+ { 0, 255, 0, },
+ { 1, 255, 0, },
+ { 32, 5, 27, },
+};
+
+#include "scalar_sat_binary.h"
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread
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2024-06-14 2:13 [PATCH v1 1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3 pan2.li
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2024-06-14 2:24 ` juzhe.zhong
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2024-06-14 2:24 ` juzhe.zhong
2024-06-14 2:13 ` [PATCH v1 7/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 9 pan2.li
2024-06-14 2:24 ` juzhe.zhong
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2024-06-14 2:29 ` Li, Pan2
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