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Cc: David Edelsohn <dje.gcc@gmail.com>, GCC Patches <gcc-patches@gcc.gnu.org>,        Pat Haugen <pthaugen@us.ibm.com>, Peter Bergner <bergner@vnet.ibm.com>
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From: Segher Boessenkool <segher@kernel.crashing.org>
Subject: Re: [PATCH, rs6000] power8 patches, patch #4, new power8 builtins
Date: Fri, 31 May 2013 09:14:00 -0000
To: Michael Meissner <meissner@linux.vnet.ibm.com>
X-SW-Source: 2013-05/txt/msg01845.txt.bz2

> Ok, I tracked down what the problem is.  We never implemented the  
> EQV, ORC, or
> NAND insns in the GPRs.  When I added the power8 vector versions,  
> the split
> wide types pass tried to do its thing in the GPRs, it creates a bad  
> insn. I
> originally saw it in the atomic ops, because I was testing all of the
> combinations provided, but I can reproduce it just by using  
> __int128_t.

The boolc<mode>3_internal1 pattern uses non-canonical RTL for
eqv: (xor (not x) y) instead of (not (xor x y)).  You'll need
to add a correct pattern, or wait for my patch series (which
I'll start sending later today) to get in.

(There are problems with the dot forms of xor, nand, nor, and
eqv as well, but I don't think you will hit that?)


Segher