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From: 钟居哲 <juzhe.zhong@rivai.ai>
To: rdapp.gcc <rdapp.gcc@gmail.com>,  gcc-patches <gcc-patches@gcc.gnu.org>
Cc: rdapp.gcc <rdapp.gcc@gmail.com>,
	 kito.cheng <kito.cheng@gmail.com>,
	 kito.cheng <kito.cheng@sifive.com>,
	 "Jeff Law" <jeffreyalaw@gmail.com>
Subject: Re: Re: [PATCH] RISC-V: Support VLS basic operation auto-vectorization
Date: Tue, 8 Aug 2023 05:14:44 +0800	[thread overview]
Message-ID: <F64607F9547DE09B+202308080514435254412@rivai.ai> (raw)
In-Reply-To: <e67514ae-c6ca-edc8-d8e5-997ed5c01f52@gmail.com>

[-- Attachment #1: Type: text/plain, Size: 720 bytes --]

Thanks Robin.

Yes, we should not allow vsetvli rd,rs1 which is generated by SELECT_VL for partial vector auto-vectorzation.
But I believe scan-assembler-not csrr is enough.



juzhe.zhong@rivai.ai
 
From: Robin Dapp
Date: 2023-08-08 03:46
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Support VLS basic operation auto-vectorization
Hi Juzhe,
 
thanks, looks good from my side.
 
> +/* { dg-final { scan-assembler-times {vand\.vi\s+v[0-9]+,\s*v[0-9]+,\s*-16} 42 } } */
> +/* { dg-final { scan-assembler-not {csrr} } } */
 
I was actually looking for a scan-assembler-not vsetvli... but the
csrr will do as well.
 
Regards
Robin
 

  reply	other threads:[~2023-08-07 21:14 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-07  9:27 Juzhe-Zhong
2023-08-07 19:46 ` Robin Dapp
2023-08-07 21:14   ` 钟居哲 [this message]
2023-08-07 23:07     ` Li, Pan2

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