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From: Richard Biener <richard.guenther@gmail.com>
To: David Edelsohn <dje.gcc@gmail.com>,Segher Boessenkool
	<segher@kernel.crashing.org>,"William J. Schmidt"
	<wschmidt@linux.vnet.ibm.com>
Cc: GCC Patches <gcc-patches@gcc.gnu.org>
Subject: Re: [PATCH] lround for PowerPC
Date: Sun, 22 Nov 2015 08:51:00 -0000	[thread overview]
Message-ID: <F75D0D75-95E8-4A66-8A17-1976282B462E@gmail.com> (raw)
In-Reply-To: <CAGWvnynJ8bDp-NF6YsZKF1ENRY-tGquqCmMHaEz4ZiMvR7r4kw@mail.gmail.com>

On November 22, 2015 2:52:53 AM GMT+01:00, David Edelsohn <dje.gcc@gmail.com> wrote:
>PowerPC was missing a definition of the lroundMN pattern, which can be
>implemented with  VSX instructions available in Power7.  Below is a
>first draft.
>
>- David
>
>* config/rs6000/rs6000.md (*xsrdpidf2): New define_insn.
>(lrounddfdi2): New define_expand.
>
>diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
>index 8c53c40..eadbe1d 100644
>--- a/gcc/config/rs6000/rs6000.md
>+++ b/gcc/config/rs6000/rs6000.md
>@@ -77,6 +77,7 @@
>    UNSPEC_FRIN
>    UNSPEC_FRIP
>    UNSPEC_FRIZ
>+   UNSPEC_XSRDPI
>    UNSPEC_LD_MPIC              ; load_macho_picbase
>    UNSPEC_RELD_MPIC            ; re-load_macho_picbase
>    UNSPEC_MPIC_CORRECT         ; macho_correct_pic
>@@ -5245,6 +5246,27 @@
>   [(set_attr "type" "fp")
>    (set_attr "fp_type" "fp_addsub_<Fs>")])
>
>+(define_insn "*xsrdpidf2"
>+  [(set (match_operand:DF 0 "gpc_reg_operand" "=<Fv>")
>+       (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "<Fv>")]
>+                  UNSPEC_XSRDPI))]
>+  "TARGET_DF_FPR && TARGET_POPCNTD"
>+  "xsrdpi %0,%1"
>+  [(set_attr "type" "fp")])
>+
>+(define_expand "lrounddfdi2"
>+  [(set (match_dup 2)
>+       (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "<Fv>")]
>+                  UNSPEC_XSRDPI))
>+   (set (match_operand:DI 0 "gpc_reg_operand" "=d")
>+       (unspec:DI [(match_dup 2)]
>+                  UNSPEC_FCTID))]
>+  "TARGET_DF_FPR && TARGET_POPCNTD
>+   && flag_unsafe_math_optimizations && !flag_trapping_math"

Why unsafe-math?

Richard.

>+{
>+  operands[2] = gen_reg_rtx (DFmode);
>+})
>+
>; An UNSPEC is used so we don't have to support SImode in FP registers.
> (define_insn "stfiwx"
>   [(set (match_operand:SI 0 "memory_operand" "=Z")


  reply	other threads:[~2015-11-22  7:34 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-11-22  3:21 David Edelsohn
2015-11-22  8:51 ` Richard Biener [this message]
2015-11-22 14:39   ` David Edelsohn
2015-11-22 20:58   ` David Edelsohn
2015-11-23 22:15     ` Michael Meissner
2015-11-24  0:06       ` David Edelsohn
2015-11-24 18:51         ` Michael Meissner
2015-11-24 19:00           ` Michael Meissner
2015-11-24 19:29             ` David Edelsohn
2015-11-24 23:01         ` Michael Meissner
2015-11-24  0:16       ` Michael Meissner

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