From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by sourceware.org (Postfix) with ESMTPS id C78373858D32 for ; Mon, 17 Oct 2022 15:27:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org C78373858D32 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ej1-x631.google.com with SMTP id d26so25721870eje.10 for ; Mon, 17 Oct 2022 08:27:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:references :in-reply-to:subject:cc:to:from:date:from:to:cc:subject:date :message-id:reply-to; bh=tXkE/bLgnpMVv7xlCCzNSSSvWvn4C1NzHdjvDTKQ+lo=; b=VfCb/QYPeIA9alQNmacOI7ulicyjS6/h5zf/Qgn4INvl0sA/uQ715rL4LO26v+ldQb tOGRWOcyhhNR0fDXa/e37mgQZiv1TDRmwjfMgVi1eQTpGMSFSainqmb5nignWz7WqJTk L5nFZqqLSL05HN1qV7ZR9LdwcjpL7weQg66fw3L05c/FIqNV08e4cVzS/ccKqNIP81nx Mb/Tk5WnjS8xfv4lc+c9myGHfmdt48ZSPifcMzaQR/EhHgV0ee9BFw/fHastL9Ll3rug Gw+oorUsj6UPZbdcyifbNcSL+hHYrvrz12y246saeJLvnKjGeuYupToiuyA3CYMyALIi swnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:references :in-reply-to:subject:cc:to:from:date:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tXkE/bLgnpMVv7xlCCzNSSSvWvn4C1NzHdjvDTKQ+lo=; b=c6bbMfLOdA2G/dUjPVDf5w/F1qeNGlKsxpKeCLoxKf3siEiQALLpybgFDLTM8XtWv2 I3xrRtpLnChNntS0dAfZ+UF0xSnAiVfW6PHHh4pKU0/8le7R2OfhezKQsv3fxBx/v8lY W+XJVfuRuXPF73SkDxQBABkfHSf3n0F8LoPHVysZVvQd/szOPysgetoAN4R2w4wCEyWl ODxS/SuvMP4O2N4CF49CZkCZE1o4yFsjyp/WYDfC6yHZHBmUGEtGRnl0wncz2oEXCcJV PIeiE9Gf58hOPAvKhUW2MX6WQ4WpwJTbtP/clHhvsdQ1xi9r6Rc5wH/kPojEWxFabOAG e/9Q== X-Gm-Message-State: ACrzQf1X+anxqi8Y+l7MC+cVwFCCj85OKdVboQR44QZxaLUnVL68JQ6V vjO75ENd8HegIluoUdnwWu4= X-Google-Smtp-Source: AMsMyM6Eb4PIzZ1OigM8/6vr/cJOLA/HefIfNTYl2mxoQgmUOdYAp4rlZ/RrtbpJgIWCuaN4+y/F0A== X-Received: by 2002:a17:906:974f:b0:78e:1031:6b26 with SMTP id o15-20020a170906974f00b0078e10316b26mr9040582ejy.280.1666020438878; Mon, 17 Oct 2022 08:27:18 -0700 (PDT) Received: from [127.0.0.1] (80-110-214-113.static.upcbusiness.at. [80.110.214.113]) by smtp.gmail.com with ESMTPSA id f6-20020a170906c08600b007813968e154sm6308228ejz.86.2022.10.17.08.27.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 17 Oct 2022 08:27:18 -0700 (PDT) Date: Mon, 17 Oct 2022 17:25:34 +0200 From: Bernhard Reutner-Fischer To: Christophe Lyon , Christophe Lyon via Gcc-patches , Srinath Parvathaneni , gcc-patches@gcc.gnu.org CC: richard.earnshaw@arm.com Subject: Re: [GCC][PATCH] arm: Add cde feature support for Cortex-M55 CPU. In-Reply-To: <6bc253d0-a642-e89e-0897-e8cb2fc8ce2c@arm.com> References: <6bc253d0-a642-e89e-0897-e8cb2fc8ce2c@arm.com> Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-9.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_LOTSOFHASH,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 17 October 2022 15:29:33 CEST, Christophe Lyon via Gcc-patches wrote: >Hi Srinath, > > >On 10/10/22 10:20, Srinath Parvathaneni via Gcc-patches wrote: >> Hi, >>=20 >> This patch adds cde feature (optional) support for Cortex-M55 CPU, plea= se refer >> [1] for more details=2E To use this feature we need to specify +cdecpN >> (e=2Eg=2E -mcpu=3Dcortex-m55+cdecp), where N is the coprocessor numb= er 0 to 7=2E >>=20 >> Bootstrapped for arm-none-linux-gnueabihf target, regression tested >> on arm-none-eabi target and found no regressions=2E >>=20 >> [1] https://developer=2Earm=2Ecom/documentation/101051/0101/?lang=3Den = (version: r1p1)=2E >>=20 >> Ok for master? >>=20 >> Regards, >> Srinath=2E >>=20 >> gcc/ChangeLog: >>=20 >> 2022-10-07 Srinath Parvathaneni >>=20 >> * common/config/arm/arm-common=2Ecc (arm_canon_arch_option_1):= Ignore cde >> options for mlibarch=2E >> * config/arm/arm-cpus=2Ein (begin cpu cortex-m55): Add cde opt= ions=2E >> * doc/invoke=2Etexi (CDE): Document options for Cortex-M55 CPU= =2E >>=20 >> gcc/testsuite/ChangeLog: >>=20 >> 2022-10-07 Srinath Parvathaneni >>=20 >> * gcc=2Etarget/arm/multilib=2Eexp: Add multilib tests for Cort= ex-M55 CPU=2E >>=20 >>=20 >> ############### Attachment also inlined for ease of reply ######= ######### >>=20 >>=20 >> diff --git a/gcc/common/config/arm/arm-common=2Ecc b/gcc/common/config/= arm/arm-common=2Ecc >> index c38812f1ea6a690cd19b0dc74d963c4f5ae155ca=2E=2Eb6f955b3c012475f398= 382e72c9a3966412991ec 100644 >> --- a/gcc/common/config/arm/arm-common=2Ecc >> +++ b/gcc/common/config/arm/arm-common=2Ecc >> @@ -753,6 +753,15 @@ arm_canon_arch_option_1 (int argc, const char **ar= gv, bool arch_for_multilib) >> arm_initialize_isa (target_isa, selected_cpu->common=2Eisa_bits= ); >> arm_parse_option_features (target_isa, &selected_cpu->common, >> strchr (cpu, '+')); >> + if (arch_for_multilib) >> + { >> + const enum isa_feature removable_bits[] =3D {ISA_IGNORE_FOR_MULTILI= B, >> + isa_nobit}; >> + sbitmap isa_bits =3D sbitmap_alloc (isa_num_bits); >> + arm_initialize_isa (isa_bits, removable_bits); >> + bitmap_and_compl (target_isa, target_isa, isa_bits); >> + } >> + > >I can see the piece of code you add here is exactly the same as the one a= few lines above when handling "if (arch)"=2E Can this be moved below and t= hus be common to the two cases, or does it have to be performed before bitm= ap_ior of fpu_isa? > >Also, IIUC, CDE was already optional for other CPUs (M33, M35P, star-mc1)= , so the hunk above fixes a latent bug when handling multilibs for these CP= Us too? If so, maybe worth splitting the patch into two parts since the abo= ve is not strictly related to M55? > >But I'm not a maintainer ;-) Don't you have to sbitmap_free the thing, short of using an auto_sbitmap? thanks, > >Thanks, > >Christophe > >> if (fpu && strcmp (fpu, "auto") !=3D 0) >> { >> /* The easiest and safest way to remove the default fpu >> diff --git a/gcc/config/arm/arm-cpus=2Ein b/gcc/config/arm/arm-cpus=2Ei= n >> index 5a63bc548e54dbfdce5d1df425bd615d81895d80=2E=2Eaa02c04c4924662f3dd= d58e6967392ba3f4b4a87 100644 >> --- a/gcc/config/arm/arm-cpus=2Ein >> +++ b/gcc/config/arm/arm-cpus=2Ein >> @@ -1633,6 +1633,14 @@ begin cpu cortex-m55 >> option nomve remove mve mve_float >> option nofp remove ALL_FP mve_float >> option nodsp remove MVE mve_float >> + option cdecp0 add cdecp0 >> + option cdecp1 add cdecp1 >> + option cdecp2 add cdecp2 >> + option cdecp3 add cdecp3 >> + option cdecp4 add cdecp4 >> + option cdecp5 add cdecp5 >> + option cdecp6 add cdecp6 >> + option cdecp7 add cdecp7 >> isa quirk_no_asmcpu quirk_vlldm >> costs v7m >> vendor 41 >> diff --git a/gcc/doc/invoke=2Etexi b/gcc/doc/invoke=2Etexi >> index aa5655764a0360959f9c1061749d2cc9ebd23489=2E=2E26857f7a90e42d925bc= 6908686ac78138a53c4ad 100644 >> --- a/gcc/doc/invoke=2Etexi >> +++ b/gcc/doc/invoke=2Etexi >> @@ -21698,6 +21698,10 @@ floating-point instructions on @samp{cortex-m5= 5}=2E >> Disable the M-Profile Vector Extension (MVE) single precision floatin= g-point >> instructions on @samp{cortex-m55}=2E >> +@item +cdecp0, +cdecp1, =2E=2E=2E , +cdecp7 >> +Enable the Custom Datapath Extension (CDE) on selected coprocessors ac= cording >> +to the numbers given in the options in the range 0 to 7 on @samp{corte= x-m55}=2E >> + >> @item +nofp >> Disables the floating-point instructions on @samp{arm9e}, >> @samp{arm946e-s}, @samp{arm966e-s}, @samp{arm968e-s}, @samp{arm10e}, >> diff --git a/gcc/testsuite/gcc=2Etarget/arm/multilib=2Eexp b/gcc/testsu= ite/gcc=2Etarget/arm/multilib=2Eexp >> index 2fa648c61dafebb663969198bf7849400a7547f6=2E=2E7a977bff58b7b68bfe9= e49d7602989a39caa6534 100644 >> --- a/gcc/testsuite/gcc=2Etarget/arm/multilib=2Eexp >> +++ b/gcc/testsuite/gcc=2Etarget/arm/multilib=2Eexp >> @@ -851,6 +851,18 @@ if {[multilib_config "rmprofile"] } { >> {-mcpu=3Dcortex-m55+nomve+nofp -mfpu=3Dauto -mfloat-abi=3Dsoftfp} "t= humb/v8-m=2Emain/nofp" >> {-mcpu=3Dcortex-m55+nodsp+nofp -mfpu=3Dauto -mfloat-abi=3Dsoft} "thu= mb/v8-m=2Emain/nofp" >> {-mcpu=3Dcortex-m55+nodsp+nofp -mfpu=3Dauto -mfloat-abi=3Dsoftfp} "t= humb/v8-m=2Emain/nofp" >> + {-mcpu=3Dcortex-m55 -mfloat-abi=3Dhard -mfpu=3Dauto} "thumb/v8-m=2Ema= in+dp/hard" >> + {-mcpu=3Dcortex-m55+cdecp0 -mfloat-abi=3Dhard -mfpu=3Dauto} "thumb/v8= -m=2Emain+dp/hard" >> + {-mcpu=3Dcortex-m55+nomve+cdecp0 -mfloat-abi=3Dhard -mfpu=3Dauto} "th= umb/v8-m=2Emain+dp/hard" >> + {-mcpu=3Dcortex-m55+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+= cdecp7 -mfloat-abi=3Dhard -mfpu=3Dauto} "thumb/v8-m=2Emain+dp/hard" >> + {-mcpu=3Dcortex-m55 -mfloat-abi=3Dsoftfp -mfpu=3Dauto} "thumb/v8-m=2E= main+dp/softfp" >> + {-mcpu=3Dcortex-m55+cdecp0 -mfloat-abi=3Dsoftfp -mfpu=3Dauto} "thumb/= v8-m=2Emain+dp/softfp" >> + {-mcpu=3Dcortex-m55+nomve+cdecp0 -mfloat-abi=3Dsoftfp -mfpu=3Dauto} "= thumb/v8-m=2Emain+dp/softfp" >> + {-mcpu=3Dcortex-m55+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+= cdecp7 -mfloat-abi=3Dsoftfp -mfpu=3Dauto} "thumb/v8-m=2Emain+dp/softfp" >> + {-mcpu=3Dcortex-m55 -mfloat-abi=3Dsoft -mfpu=3Dauto} "thumb/v8-m=2Ema= in/nofp" >> + {-mcpu=3Dcortex-m55+cdecp0 -mfloat-abi=3Dsoft -mfpu=3Dauto} "thumb/v8= -m=2Emain/nofp" >> + {-mcpu=3Dcortex-m55+nomve+cdecp0 -mfloat-abi=3Dsoft -mfpu=3Dauto} "th= umb/v8-m=2Emain/nofp" >> + {-mcpu=3Dcortex-m55+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+= cdecp7 -mfloat-abi=3Dsoft -mfpu=3Dauto} "thumb/v8-m=2Emain/nofp" >> {-march=3Darmv8-m=2Emain+cdecp0 -mfpu=3Dauto -mfloat-abi=3Dsoft} "th= umb/v8-m=2Emain/nofp" >> {-march=3Darmv8-m=2Emain+fp+cdecp0 -mfpu=3Dauto -mfloat-abi=3Dsoft} = "thumb/v8-m=2Emain/nofp" >> {-march=3Darmv8-m=2Emain+fp=2Edp+cdecp0 -mfpu=3Dauto -mfloat-abi=3Ds= oft} "thumb/v8-m=2Emain/nofp" >>=20 >>=20 >>=20