From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 4403 invoked by alias); 4 Feb 2015 21:43:55 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 4389 invoked by uid 89); 4 Feb 2015 21:43:54 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: relay1.mentorg.com Received: from relay1.mentorg.com (HELO relay1.mentorg.com) (192.94.38.131) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 04 Feb 2015 21:43:53 +0000 Received: from svr-orw-fem-05.mgc.mentorg.com ([147.34.97.43]) by relay1.mentorg.com with esmtp id 1YJ7jh-0000Us-Q8 from Catherine_Moore@mentor.com ; Wed, 04 Feb 2015 13:43:49 -0800 Received: from NA-MBX-04.mgc.mentorg.com ([169.254.4.117]) by SVR-ORW-FEM-05.mgc.mentorg.com ([147.34.97.43]) with mapi id 14.03.0224.002; Wed, 4 Feb 2015 13:43:49 -0800 From: "Moore, Catherine" To: Matthew Fortune CC: "'gcc-patches@gcc.gnu.org' (gcc-patches@gcc.gnu.org)" Subject: RE: [PATCH,WWWDOCS] MIPS changes for GCC 5.0 Date: Wed, 04 Feb 2015 21:43:00 -0000 Message-ID: References: <6D39441BF12EF246A7ABCE6654B0235320FC7F04@LEMAIL01.le.imgtec.org> In-Reply-To: <6D39441BF12EF246A7ABCE6654B0235320FC7F04@LEMAIL01.le.imgtec.org> Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-SW-Source: 2015-02/txt/msg00288.txt.bz2 Hi Matthew, I made a few edits. I removed the markup in the process, so that will need= to be added back. See the text at the end. Thanks, Catherine > -----Original Message----- > From: Matthew Fortune [mailto:Matthew.Fortune@imgtec.com] > Sent: Wednesday, February 04, 2015 11:46 AM > To: Moore, Catherine > Cc: 'gcc-patches@gcc.gnu.org' (gcc-patches@gcc.gnu.org) > Subject: [PATCH,WWWDOCS] MIPS changes for GCC 5.0 >=20 > Hi Catherine, >=20 > I've made a first pass at writing up the MIPS changes for GCC 5.0. > Could you take a read and see what needs some more work? >=20 > Thanks, > Matthew >=20 > Index: htdocs/gcc-5/changes.html > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D > RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-5/changes.html,v > retrieving revision 1.77 > diff -r1.77 changes.html > 562a563,614 > >

MIPS

> >
    > >
  • MIPS Releases 3 and 5 are now directly supported using - > mips32r3, > > -mips64r3, -mips32r5 and -mips64r5 instead of relying on the > Release > > 2 options.
    • > >
  • Support for the Imagination P5600 processor has been added using > > -march=3Dp5600. > >
    • > >
  • Support for the Cavium Networks Octeon3 processor has been added > using > > -march=3Docteon3.
    • > >
  • MIPS Release 6 is now supported using -mips32r6 and - > mips64r6 > > . > >
  • The previous o32 64-bit floating-point register support has been > > obsoleted and removed. This was previously enabled using - > mfp64 > > which has been re-purposed for the new ABI extensions > described > > below.
    • > >
  • New o32 ABI extensions have been added to enable software to > transition > > away from the original layout of double-precision floating-point re= gisters. > >
      > >
    • The first of these extensions is o32 FPXX which places restri= ctions > > on code-generation to never access the upper 32-bits of double- > precision > > registers via odd-numbered single-precision registers. By defaul= t the > > odd-numbered single-precision registers are not used at all with = this > > extension. o32 FPXX code is link compatible with all other o32 > > double-precision ABI variants and will execute correctly in all h= ardware > > FPU modes. Enable o32 FPXX using -mabi=3D32 -mfpxx = for > > MIPS II onwards.
      • > >
    • The second extension is o32 FP64A which requires 64-bit > > floating-point registers and places a mandatory restriction on th= e use of > > odd-numbered single-precision registers. o32 FP64A is link compa= tible > > with all other o32 double-precision ABI variants. Enable o32 FP6= 4A > > using -mabi=3D32 -mfp64 -mno-odd-spreg for MIPS32R2 > onwards. > >
      • > >
    • Finally, the o32 FP64 extension which also requires 64-bit > > floating-point registers but permits the use of all single-precis= ion > > registers. Enable o32 FP64 using -mfp64 for MIPS32R2 > > onwards.
      • > >
    > > All new ABI variants can be enabled by default using configure time > > options --with-fp-32=3D[32|xx|64] and > > --with(out)-odd-sp-reg-32. It is strongly recommended > that > > all vendors begin to set o32 FPXX as default ABI to be able to run = the > > generated code on MIPSR5 cores alongside future MIPS SIMD (MSA) > code and > > MIPSR6 cores.
    • > >
  • When using binutils 2.25 GCC will now pass options like > > -msoft-float and -msingle-float to the > assembler. > > This change can affect inline assembly code that is built as soft-f= loat but > > contains hard-float instructions. In such cases the code must be > amended > > to use appropriate .set directives to override the glo= bal > > assembler options.
    • > >
> > MIPS Releases 3 and 5 are now directly supported. Use the command-line opt= ions -mips32r3, -mips64r3, -mips32r5 and -mips64r5 to enable code-generation for these processors. Support for the Imagination P5600 processor is now supported through use of the -march=3Dp5600 command-line option. The Cavium Octeon3 processor is now supported through the use of the command-line option -march=3Docteon3. MIPS Release 6 is now supported through the use of the -mips32r6 and -mips6= 4r6 command-line options. The o32 ABI has been modified and extended. The o32 64-bit floating-point register support is now obsolete and has been removed. It has been replace= d by three ABI extensions FPXX, FP64A, and FP64. The meaning of the -mfp64 command-line option has been changed and it is now used to enable the ABI extensions. The FPXX extension requires that code generated to access double-precision values use even-numbered registers. Code that adheres to this extension is link-compatible with the other o32 double-precision ABI variants and will execute correctly in all hardware FPU modes. The command-line options -mabi=3D32 -mfpxx can be used to enable this extension. MIPS II is the min= imum processor required. The o32 FP64A extension requires that floating-point registers be 64-bits and odd-numbered single-precisions registers are not allowed. Code that adheres to the The o32 FP64A variant is link-compatible with the other o32 double-precision ABI variants. The command-line options -mabi=3D32 -mfp64 -mno-odd-spreg can be used to enable this extension. MIPS32R2 is the minimum processor required. The o32 FP64 extension also requires that floating-point registers be 64-bi= ts, but permits the use of single-precision registers. The o32 FP64 extension = is enabled by using the -mfp64 command-line option. MIPS32R2 is the minimum processor required. The new ABI variants can be enabled by default using the configure time options --with-fp-32=3D[32|xx|64] and --with(out)-odd-sp-reg-32. It is strongly recommended that all vendors begin to set o32 FPXX as the default ABI. This will be required to run the generated code on MIPSR5 cores in conjunction with future MIPS SIMD (MSA) code and MIPSR6 cores. GCC will now pass explicit floating-point options to the assembler if GNU binutils 2.25 is being used. As a result, any inline assembly code that uses hard-float instructions should be amended to include a .set directive to override the global assembler options when compiling for soft-float targ= ets.