From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 83999 invoked by alias); 13 Jul 2015 21:11:42 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 83989 invoked by uid 89); 13 Jul 2015 21:11:41 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: relay1.mentorg.com Received: from relay1.mentorg.com (HELO relay1.mentorg.com) (192.94.38.131) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 13 Jul 2015 21:11:39 +0000 Received: from svr-orw-fem-05.mgc.mentorg.com ([147.34.97.43]) by relay1.mentorg.com with esmtp id 1ZEl0i-0004Mk-43 from Catherine_Moore@mentor.com ; Mon, 13 Jul 2015 14:11:36 -0700 Received: from NA-MBX-04.mgc.mentorg.com ([169.254.4.176]) by SVR-ORW-FEM-05.mgc.mentorg.com ([147.34.97.43]) with mapi id 14.03.0224.002; Mon, 13 Jul 2015 14:11:35 -0700 From: "Moore, Catherine" To: Robert Suchanek , Matthew Fortune , "gcc-patches@gcc.gnu.org" CC: "Moore, Catherine" Subject: RE: [PATCH, MIPS] Support new interrupt handler options Date: Mon, 13 Jul 2015 21:11:00 -0000 Message-ID: References: In-Reply-To: Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-SW-Source: 2015-07/txt/msg01083.txt.bz2 > -----Original Message----- > From: Robert Suchanek [mailto:Robert.Suchanek@imgtec.com] > Sent: Wednesday, July 08, 2015 6:43 AM > To: Matthew Fortune; Moore, Catherine; gcc-patches@gcc.gnu.org > Subject: [PATCH, MIPS] Support new interrupt handler options >=20 > Hi, >=20 > This patch adds support for optional arguments for interrupt and > use_shadow_register_set attributes. The patch also fixes an ICE if both > interrupt and use_shadow_register_set are enabled and compiled with - > mips64r2 -mabi=3D64 discovered during testing of the attached test. >=20 > The interrupt attribute accepts new arguments: "eic" and > "vector=3D[sw0|sw1|hw0|hw1|hw2|hw3|hw4|hw5]". The former is the > default if no argument is given and the latter changes the behaviour of G= CC > and masks interrupts from sw0 up to and including the specified vector. = As > part of this change, the EPC is now saved and restored unconditionally to > recover the state in nested interrupts. Only K1 register is clobbered for > masked interrupts but for non-masked interrupts K0 is still used. >=20 > The use_shadow_register_set attribute has a new option, "intstack", to > indicate that the shadow register set has a valid stack pointer. With th= is > option "rdpgpr $sp, $sp" will not be generated for an ISR. >=20 > Tested with mips-img-elf, mips-img-linux-gnu and mips64el-linux-gnu cross > compilers. Ok to apply? >=20 > Regards, > Robert >=20 > 2015-07-07 Matthew Fortune > Robert Suchanek >=20 > gcc/ > * config/mips/mips.c (mips_int_mask): New enum. > (mips_shadow_set): Likewise. > (int_mask): New variable. > (use_shadow_register_set_p): Change type to enum > mips_shadow_set. > (machine_function): Add int_mask and use_shadow_register_set. > (mips_attribute_table): Add attribute handlers for interrupt and > use_shadow_register_set. > (mips_interrupt_mask): New static function. > (mips_handle_interrupt_attr): Likewise. > (mips_handle_use_shadow_register_set_attr): Likewise. > (mips_use_shadow_register_set): Change return type to enum > mips_shadow_set. Add argument handling for > use_shadow_register_set > attribute. > (mips_interrupt_extra_called_saved_reg_p): Update the conditional > to > compare with mips_shadow_set enum. > (mips_compute_frame_info): Add interrupt mask and > use_shadow_register_set to per-function information structure. > Add a stack slot for EPC unconditionally. > (mips_expand_prologue): Compare use_shadow_register_set value > with mips_shadow_set enum. Save EPC always in K1, clobber only K1 > for > masked interrupt register but in EIC mode use K0 and save Cause in > K0. > EPC saved and restored unconditionally. Use PMODE_INSN macro > when > copying the stack pointer from the shadow register set. > * config/mips/mips.h (SR_IM0): New define. > * config/mips/mips.md (mips_rdpgpr): Rename to... > (mips_rdpgpr_): ...this. Use the Pmode iterator. > * doc/extend.texi (Declaring Attributes of Functions): Document > optional arguments for interrupt and use_shadow_register_set > attributes. >=20 > gcc/testsuite/ > * gcc.target/mips/interrupt_handler-4.c: New test. Hi Robert, I'm getting build errors with the current TOT and your patch. The first errors that I encounter are: gcc/config/mips/mips.c:1355:1: warning: 'mips_int_mask mips_interrupt_mask(= tree)' defined but not used [-Wunused-function] gcc/config/mips/mips.c:1392:1: warning: 'mips_shadow_set mips_use_shadow_re= gister_set(tree)' defined but not used [-Wunused-function] Removing these two functions results in further errors that I have not inve= stigated. Will you try applying and building your patch again? I have a couple of further comments on the existing patch, see below. Thanks, Catherine > diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index > ce21a0f..b6ad7db 100644 > --- a/gcc/config/mips/mips.c > +++ b/gcc/config/mips/mips.c > @@ -1325,13 +1359,62 @@ mips_interrupt_type_p (tree type) > return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) !=3D NUL= L; } >=20 > +static enum mips_int_mask > +mips_interrupt_mask (tree type) This function requires a comment. > +static enum mips_shadow_set > +mips_use_shadow_register_set (tree type) Likewise. > { > @@ -1537,6 +1620,87 @@ mips_can_inline_p (tree caller, tree callee) > return false; > return default_target_can_inline_p (caller, callee); } > + > +static tree > +mips_handle_interrupt_attr (tree *node, tree name, tree args, > + int flags ATTRIBUTE_UNUSED, bool *no_add_attrs) > { Likewise. > + > +static tree > +mips_handle_use_shadow_register_set_attr (tree *node, tree name, tree > args, And here as well. >=20