RE: [PATCH][MIPS] Scheduler fix for the 74k & 24k.

["Moore, Catherine" <Catherine_Moore@mentor.com>]

> -----Original Message-----
> From: gcc-patches-owner@gcc.gnu.org [mailto:gcc-patches-
> owner@gcc.gnu.org] On Behalf Of Simon Dardis
> Sent: Tuesday, July 21, 2015 6:39 AM
> To: gcc-patches@gcc.gnu.org
> Subject: [PATCH][MIPS] Scheduler fix for the 74k & 24k.
> 
> Hello,
> 
> This patch fixes a bug with the 74k & 24k schedulers.
> 
> Back in 2006  (2ca4dfa486bd358c6e466328839977250d160393) a
> mips_store_data_bypass_p was added to the mips backend. Unfortunately
> it was defined in terms of !store_data_bypass_p, though it was correctly
> used for the sb1 processor pipeline descriptor at that time. Later during a
> code-cleanup in 2012 (e053750d33e14ca245e14e1c467709a9bf6c6282) the 24k
> & 74k bypasses were changed from the correct !store_data_bypass_p to
> !mips_store_data_bypass_p. This lead to those bypasses having inverted
> guard conditions.
> 
> This patch brings mips_store_data_bypass_p into line with its comments and
> the comments of store_data_bypass_p. It also corrects the sb1's pipeline
> description.
> 
> Thanks,
> Simon
> 
> gcc/
> 	* config/mips/mips.c (mips_store_data_bypass_p): Bring code into
> 	line with comments.
> 	* config/mips/sb1.md: Update usage of mips_store_data_bypass_p.
> 

This patch is OK.