From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 113795 invoked by alias); 24 Nov 2015 18:35:01 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 113719 invoked by uid 89); 24 Nov 2015 18:35:00 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.3 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: relay1.mentorg.com Received: from relay1.mentorg.com (HELO relay1.mentorg.com) (192.94.38.131) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 24 Nov 2015 18:34:59 +0000 Received: from svr-orw-fem-05.mgc.mentorg.com ([147.34.97.43]) by relay1.mentorg.com with esmtp id 1a1IQZ-0000oe-PE from Catherine_Moore@mentor.com ; Tue, 24 Nov 2015 10:34:55 -0800 Received: from NA-MBX-04.mgc.mentorg.com ([169.254.4.113]) by SVR-ORW-FEM-05.mgc.mentorg.com ([147.34.97.43]) with mapi id 14.03.0224.002; Tue, 24 Nov 2015 10:34:55 -0800 From: "Moore, Catherine" To: "sellcey@imgtec.com" CC: "gcc-patches@gcc.gnu.org" , "matthew.fortune@imgtec.com" , "Moore, Catherine" Subject: RE: [Patch, MIPS] Frame header optimization for MIPS (part 2) Date: Tue, 24 Nov 2015 18:50:00 -0000 Message-ID: References: <5626C664.7030006@redhat.com> <863CD8C6-74F0-4D29-A48C-9B22B8F0E2BE@comcast.net> <5627DD3E.40306@redhat.com> <1445455491.2922.23.camel@ubuntu-sellcey> <562804FE.1030103@redhat.com> <1445623704.2982.2.camel@ubuntu-sellcey> In-Reply-To: <1445623704.2982.2.camel@ubuntu-sellcey> Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-SW-Source: 2015-11/txt/msg02943.txt.bz2 > -----Original Message----- > From: Steve Ellcey [mailto:sellcey@imgtec.com] > Sent: Friday, October 23, 2015 2:08 PM > To: Myers, Joseph > Cc: Bernd Schmidt; Mike Stump; gcc-patches@gcc.gnu.org; > matthew.fortune@imgtec.com; Moore, Catherine > Subject: Re: [Patch, MIPS] Frame header optimization for MIPS (part 2) >=20 > Just to follow up on this string, here is a new version of the patch > with the extraneous parenthesis removed. >=20 > Steve Ellcey > sellcey@imgtec.com >=20 >=20 > 2015-10-23 Steve Ellcey >=20 > * frame-header-opt.c (gate): Check for optimize > 0. > (has_inlined_assembly): New function. > (needs_frame_header_p): Remove is_leaf_function check, > add argument type check. > (callees_functions_use_frame_header): Add is_leaf_function > and has_inlined_assembly calls.. > (set_callers_may_not_allocate_frame): New function. > (frame_header_opt): Add is_leaf_function call, add > set_callers_may_not_allocate_frame call. > * config/mips/mips.c (mips_compute_frame_info): Add check > to see if callee saved regs can be put in frame header. > (mips_expand_prologue): Add check to see if step1 is zero, > fix cfa restores when using frame header to store regs. > (mips_can_use_return_insn): Check to see if registers are > stored in frame header. > * config/mips/mips.h (machine_function): Add > callers_may_not_allocate_frame and > use_frame_header_for_callee_saved_regs fields. This is okay after making the minor corrections embedded below. I'm sorry that it took me so long to review this patch. Catherine >=20 > diff --git a/gcc/config/mips/frame-header-opt.c b/gcc/config/mips/frame- > header-opt.c > index 7c7b1f2..2cf589d 100644 > --- a/gcc/config/mips/frame-header-opt.c > +++ b/gcc/config/mips/frame-header-opt.c > @@ -125,6 +125,29 @@ is_leaf_function (function *fn) > return true; > } >=20 > +/* Return true if this function has inline assembly code or if we cannot > + be certain that it does not. False if know that there is no inline > + assembly. */ > + s/False if know/False if we know/ > @@ -136,20 +159,26 @@ needs_frame_header_p (function *fn) > if (fn->decl =3D=3D NULL) > return true; >=20 > - if (fn->stdarg || !is_leaf_function (fn)) > + if (fn->stdarg) > return true; >=20 > for (t =3D DECL_ARGUMENTS (fn->decl); t; t =3D TREE_CHAIN (t)) > { > if (!use_register_for_decl (t)) > - return true; > + return true; > + > + /* Some 64 bit types may get copied to general registers using the= frame > + header, see mips_output_64bit_xfer. Checking for SImode only may be > + overly restrictive but it is gauranteed to be safe. */ s/64 bit/64-bit/ s/gauranteed/guaranteed/ > diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c > index c5affc8..5a9d48d 100644 > --- a/gcc/config/mips/mips.c > +++ b/gcc/config/mips/mips.c > @@ -10465,6 +10465,35 @@ mips_compute_frame_info (void) > frame->cop0_sp_offset =3D offset - UNITS_PER_WORD; > } >=20 > + /* Determine if we can save the callee saved registers in the frame > + header. Restrict this to functions where there is no other reason > + to allocate stack space so that we can completely eliminate the > + instructions that modify the stack pointer. */ > + s/callee saved/callee-saved/ s/completely// >=20 >=20 >=20 > 2015-10-23 Steve Ellcey >=20 > * gcc.target/mips/frame-header-4.c: New test. >=20 > diff --git a/gcc/testsuite/gcc.target/mips/frame-header-4.c > b/gcc/testsuite/gcc.target/mips/frame-header-4.c > index e69de29..3cddba1 100644 > --- a/gcc/testsuite/gcc.target/mips/frame-header-4.c > +++ b/gcc/testsuite/gcc.target/mips/frame-header-4.c > @@ -0,0 +1,20 @@ > +/* Verify that we can optimize away the frame header allocation in bar > + by having it use its frame header to store $31 in before calling foo.= */ > + > +/* { dg-do compile } */ > +/* { dg-options "-mframe-header-opt -mabi=3D32" } */ > +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ > +/* { dg-final { scan-assembler-not "\taddiu\t\\\$sp" } } */ > + > +int __attribute__ ((noinline)) > +foo (int a, int b) > +{ > + return a + b; > +} > + > +int __attribute__ ((noinline)) > +bar (int a, int b) > +{ > + return 1 + foo(a,b); > +} > + Space after foo, please. Change the two tabs to two space each.