Oh, Yes. 
It can be easily addressed by this:
emit_scalar_move_insn (code_for_pred_broadcast (m1_mode), scalar_move_ops);

This patch emit scalar move insn with AVL = 1 for all reduction. It can easily addressed when we recognize it is mask_len_fold_left_plus reduction,
we assign the AVL to the scalar move insn.



juzhe.zhong@rivai.ai
 
From: Kito Cheng
Date: 2023-07-20 15:42
To: Juzhe-Zhong
CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
Subject: Re: [PATCH] RISC-V: Support in-order floating-point reduction
Seems like there is a potential vsetvli optimization chance in the example?
 
> After this patch:
> foo:
>         lui     a5,%hi(.LC0)
>         flw     fa0,%lo(.LC0)(a5)
>         ble     a1,zero,.L4
> .L3:
>         vsetvli a5,a1,e32,m1,ta,ma
>         vle32.v v1,0(a0)
>         slli    a4,a5,2
>         vsetivli        zero,1,e32,m1,ta,ma
 
This could just use "vsetvli a5,a1,e32,m1,ta,ma"
 
>         sub     a1,a1,a5
>         vfmv.s.f        v2,fa0
>         add     a0,a0,a4
>         vsetvli zero,a5,e32,m1,ta,ma
 
And then this can be removed too.
 
>         vfredosum.vs    v1,v1,v2
>         vfmv.f.s        fa0,v1
>         bne     a1,zero,.L3
>         ret
> .L4:
>         ret