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Thread-Topic: [PATCH v5] RISC-V: Add vector psabi checking. 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: IA1PR11MB6466.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9823fe20-2955-4644-0b40-08db6b42943b X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Jun 2023 12:43:10.1497 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Sze3l5iJyeJM1jFBcF4cQ1RETOYj2/ZoK7/l9Lf03hCrjmcXdq3fW0wRPL5b2Lzjl/p7NJuiYHOFZFJ+dHw5bQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR11MB4702 X-OriginatorOrg: intel.com X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: I found there're still some test cases that does not pass. I'll push another version soon. Sorry for the inconvenience. > -----Original Message----- > From: Wang, Yanzhang > Sent: Monday, June 12, 2023 4:08 PM > To: gcc-patches@gcc.gnu.org > Cc: juzhe.zhong@rivai.ai; kito.cheng@sifive.com; Li, Pan2 > ; Wang, Yanzhang > Subject: [PATCH v5] RISC-V: Add vector psabi checking. >=20 > From: Yanzhang Wang >=20 > This patch adds support to check function's argument or return is vector > type and throw warning if yes. >=20 > There're two exceptions, > - The vector_size attribute. > - The intrinsic functions. >=20 > gcc/ChangeLog: >=20 > * config/riscv/riscv-protos.h (riscv_init_cumulative_args): Set > warning flag if func is not builtin > * config/riscv/riscv.cc > (riscv_scalable_vector_type_p): Determine whether the type is scalable > vector. > (riscv_arg_has_vector): Determine whether the arg is vector type. > (riscv_pass_in_vector_p): Check the vector type param is passed by > value. > (riscv_init_cumulative_args): The same as header. > (riscv_get_arg_info): Add the checking. > (riscv_function_value): Check the func return and set warning flag > * config/riscv/riscv.h (INIT_CUMULATIVE_ARGS): Add a flag to > determine whether warning psabi or not. >=20 > gcc/testsuite/ChangeLog: >=20 > * gcc.target/riscv/rvv/rvv.exp: Add -Wno-psabi > * gcc.target/riscv/vector-abi-1.c: New test. > * gcc.target/riscv/vector-abi-2.c: New test. > * gcc.target/riscv/vector-abi-3.c: New test. > * gcc.target/riscv/vector-abi-4.c: New test. > * gcc.target/riscv/vector-abi-5.c: New test. > * gcc.target/riscv/vector-abi-6.c: New test. >=20 > Signed-off-by: Yanzhang Wang > Co-authored-by: Kito Cheng > --- > gcc/config/riscv/riscv-protos.h | 2 + > gcc/config/riscv/riscv.cc | 112 +++++++++++++++++- > gcc/config/riscv/riscv.h | 5 +- > gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 2 +- > gcc/testsuite/gcc.target/riscv/vector-abi-1.c | 14 +++ > gcc/testsuite/gcc.target/riscv/vector-abi-2.c | 15 +++ > gcc/testsuite/gcc.target/riscv/vector-abi-3.c | 14 +++ > gcc/testsuite/gcc.target/riscv/vector-abi-4.c | 16 +++ > gcc/testsuite/gcc.target/riscv/vector-abi-5.c | 15 +++ > gcc/testsuite/gcc.target/riscv/vector-abi-6.c | 20 ++++ > 10 files changed, 212 insertions(+), 3 deletions(-) create mode 100644 > gcc/testsuite/gcc.target/riscv/vector-abi-1.c > create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-2.c > create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-3.c > create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-4.c > create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-5.c > create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-6.c >=20 > diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv- > protos.h index 66c1f535d60..90fde5f8be3 100644 > --- a/gcc/config/riscv/riscv-protos.h > +++ b/gcc/config/riscv/riscv-protos.h > @@ -302,4 +302,6 @@ th_mempair_output_move (rtx[4], bool, machine_mode, > RTX_CODE); #endif >=20 > extern bool riscv_use_divmod_expander (void); > +void riscv_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree, > +int); > + > #endif /* ! GCC_RISCV_PROTOS_H */ > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index > de30bf4e567..dd5361c2bd2 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -3795,6 +3795,99 @@ riscv_pass_fpr_pair (machine_mode mode, unsigned > regno1, > GEN_INT (offset2)))); > } >=20 > +/* Use the TYPE_SIZE to distinguish the type with vector_size attribute > and > + intrinsic vector type. Because we can't get the decl for the > +params. */ > + > +static bool > +riscv_scalable_vector_type_p (const_tree type) { > + tree size =3D TYPE_SIZE (type); > + if (size && TREE_CODE (size) =3D=3D INTEGER_CST) > + return false; > + > + /* For the data type like vint32m1_t, the size code is POLY_INT_CST. > +*/ > + return true; > +} > + > +static bool > +riscv_arg_has_vector (const_tree type) > +{ > + bool is_vector =3D false; > + > + switch (TREE_CODE (type)) > + { > + case RECORD_TYPE: > + if (!COMPLETE_TYPE_P (type)) > + break; > + > + for (tree f =3D TYPE_FIELDS (type); f; f =3D DECL_CHAIN (f)) > + if (TREE_CODE (f) =3D=3D FIELD_DECL) > + { > + tree field_type =3D TREE_TYPE (f); > + if (!TYPE_P (field_type)) > + break; > + > + /* Ignore it if it's fixed length vector. */ > + if (VECTOR_TYPE_P (field_type)) > + is_vector =3D riscv_scalable_vector_type_p (field_type); > + else > + is_vector =3D riscv_arg_has_vector (field_type); > + } > + > + break; > + > + case VECTOR_TYPE: > + is_vector =3D riscv_scalable_vector_type_p (type); > + break; > + > + default: > + is_vector =3D false; > + break; > + } > + > + return is_vector; > +} > + > +/* Pass the type to check whether it's a vector type or contains vector > type. > + Only check the value type and no checking for vector pointer type. > +*/ > + > +static void > +riscv_pass_in_vector_p (const_tree type) { > + static int warned =3D 0; > + > + if (type && riscv_arg_has_vector (type) && !warned) > + { > + warning (OPT_Wpsabi, "ABI for the scalable vector type is currentl= y > in " > + "experimental stage and may changes in the upcoming version of " > + "GCC."); > + warned =3D 1; > + } > +} > + > +/* Initialize a variable CUM of type CUMULATIVE_ARGS > + for a call to a function whose data type is FNTYPE. > + For a library call, FNTYPE is 0. */ > + > +void > +riscv_init_cumulative_args (CUMULATIVE_ARGS *cum, > + tree fntype ATTRIBUTE_UNUSED, > + rtx libname ATTRIBUTE_UNUSED, > + tree fndecl, > + int caller ATTRIBUTE_UNUSED) > +{ > + memset (cum, 0, sizeof (*cum)); > + > + if (fndecl) > + { > + const tree_function_decl &fn > + =3D FUNCTION_DECL_CHECK (fndecl)->function_decl; > + > + if (fn.built_in_class =3D=3D NOT_BUILT_IN) > + cum->rvv_psabi_warning =3D 1; > + } > +} > + > /* Fill INFO with information about a single argument, and return an > RTL pattern to pass or return the argument. CUM is the cumulative > state for earlier arguments. MODE is the mode of this argument and @= @ > -3816,6 +3909,12 @@ riscv_get_arg_info (struct riscv_arg_info *info, cons= t > CUMULATIVE_ARGS *cum, > info->gpr_offset =3D cum->num_gprs; > info->fpr_offset =3D cum->num_fprs; >=20 > + if (cum->rvv_psabi_warning) > + { > + /* Only check existing of vector type. */ > + riscv_pass_in_vector_p (type); > + } > + > /* TODO: Currently, it will cause an ICE for --param > riscv-autovec-preference=3Dfixed-vlmax. So, we just return NULL_RTX > here > let GCC generate loads/stores. Ideally, we should either warn the > user not @@ -3973,7 +4072,18 @@ riscv_function_value (const_tree type, > const_tree func, machine_mode mode) > } >=20 > memset (&args, 0, sizeof args); > - return riscv_get_arg_info (&info, &args, mode, type, true, true); > + > + const_tree arg_type =3D type; > + if (func && DECL_RESULT (func)) > + { > + const tree_function_decl &fn =3D FUNCTION_DECL_CHECK (func)- > >function_decl; > + if (fn.built_in_class =3D=3D NOT_BUILT_IN) > + args.rvv_psabi_warning =3D 1; > + > + arg_type =3D TREE_TYPE (DECL_RESULT (func)); > + } > + > + return riscv_get_arg_info (&info, &args, mode, arg_type, true, true); > } >=20 > /* Implement TARGET_PASS_BY_REFERENCE. */ diff --git > a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index > 4541255a8ae..bfd9b7551bc 100644 > --- a/gcc/config/riscv/riscv.h > +++ b/gcc/config/riscv/riscv.h > @@ -677,6 +677,8 @@ typedef struct { >=20 > /* Number of floating-point registers used so far, likewise. */ > unsigned int num_fprs; > + > + int rvv_psabi_warning; > } CUMULATIVE_ARGS; >=20 > /* Initialize a variable CUM of type CUMULATIVE_ARGS @@ -684,7 +686,8 @@ > typedef struct { > For a library call, FNTYPE is 0. */ >=20 > #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARG= S) > \ > - memset (&(CUM), 0, sizeof (CUM)) > + riscv_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT), > \ > + (N_NAMED_ARGS) !=3D -1) >=20 > #define EPILOGUE_USES(REGNO) riscv_epilogue_uses (REGNO) >=20 > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp > b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp > index 5e69235a268..ad79d0e9a8d 100644 > --- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp > +++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp > @@ -43,7 +43,7 @@ dg-init > # Main loop. > set CFLAGS "$DEFAULT_CFLAGS -march=3D$gcc_march -mabi=3D$gcc_mabi -O3" > dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.\[cS\]]] \ > - "" $CFLAGS > + "-Wno-psabi" $CFLAGS > gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vsetvl/*.\[cS\]]= ] > \ > "" $CFLAGS > dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[cS\]]] \ > diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-1.c > b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c > new file mode 100644 > index 00000000000..969f14277a4 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c > @@ -0,0 +1,14 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O0 -march=3Drv64gcv -mabi=3Dlp64d" } */ > + > +#include "riscv_vector.h" > + > +void > +fun (vint32m1_t a) { } /* { dg-warning "the scalable vector type" } */ > + > +void > +bar () > +{ > + vint32m1_t a; > + fun (a); > +} > diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-2.c > b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c > new file mode 100644 > index 00000000000..63d97d30fc5 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c > @@ -0,0 +1,15 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv -mabi=3Dlp64d" } */ > +/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */ > + > +#include "riscv_vector.h" > + > +vint32m1_t > +fun (vint32m1_t* a) { return *a; } /* { dg-warning "the scalable > +vector type" } */ > + > +void > +bar () > +{ > + vint32m1_t a; > + fun (&a); > +} > diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-3.c > b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c > new file mode 100644 > index 00000000000..90ece60cc6f > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c > @@ -0,0 +1,14 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv -mabi=3Dlp64d" } */ > + > +#include "riscv_vector.h" > + > +vint32m1_t* > +fun (vint32m1_t* a) { return a; } /* { dg-bogus "the scalable vector > +type" } */ > + > +void > +bar () > +{ > + vint32m1_t a; > + fun (&a); > +} > diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-4.c > b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c > new file mode 100644 > index 00000000000..ecf6d4cc26b > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c > @@ -0,0 +1,16 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv -mabi=3Dlp64d" } */ > + > +#include "riscv_vector.h" > + > +typedef int v4si __attribute__ ((vector_size (16))); > + > +v4si > +fun (v4si a) { return a; } /* { dg-bogus "the scalable vector type" } > +*/ > + > +void > +bar () > +{ > + v4si a; > + fun (a); > +} > diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-5.c > b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c > new file mode 100644 > index 00000000000..6053e0783b6 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c > @@ -0,0 +1,15 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv -mabi=3Dlp64d" } */ > + > +typedef int v4si __attribute__ ((vector_size (16))); struct A { int a; > +v4si b; }; > + > +void > +fun (struct A a) {} /* { dg-bogus "the scalable vector type" } */ > + > +void > +bar () > +{ > + struct A a; > + fun (a); > +} > diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-6.c > b/gcc/testsuite/gcc.target/riscv/vector-abi-6.c > new file mode 100644 > index 00000000000..63bc4a89805 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-6.c > @@ -0,0 +1,20 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv64gcv -mabi=3Dlp64d" } */ #include > +"riscv_vector.h" > + > +void > +foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, > + size_t n, int cond) { > + size_t vl; > + if (cond) > + vl =3D __riscv_vsetvlmax_e32m1(); > + else > + vl =3D __riscv_vsetvlmax_e16mf2(); > + for (size_t i =3D 0; i < n; i +=3D 1) > + { > + vint32m1_t a =3D __riscv_vle32_v_i32m1(in1, vl); /* { dg-bogus "th= e > scalable vector type" } */ > + vint32m1_t b =3D __riscv_vle32_v_i32m1_tu(a, in2, vl); > + vint32m1_t c =3D __riscv_vle32_v_i32m1_tu(b, in3, vl); > + __riscv_vse32_v_i32m1(out, c, vl); > + } > +} > -- > 2.40.1