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charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable For lane-reducing operation(dot-prod/widen-sum/sad) in loop reduction, curr= ent=0A= vectorizer could only handle the pattern if the reduction chain does not=0A= contain other operation, no matter the other is normal or lane-reducing.=0A= =0A= Acctually, to allow multiple arbitray lane-reducing operations, we need to= =0A= support vectorization of loop reduction chain with mixed input vectypes. Si= nce=0A= lanes of vectype may vary with operation, the effective ncopies of vectoriz= ed=0A= statements for operation also may not be same to each other, this causes=0A= mismatch on vectorized def-use cycles. A simple way is to align all operati= ons=0A= with the one that has the most ncopies, the gap could be complemented by=0A= generating extra trival pass-through copies. For example:=0A= =0A= int sum =3D 0;=0A= for (i)=0A= {=0A= sum +=3D d0[i] * d1[i]; // dot-prod =0A= sum +=3D w[i]; // widen-sum =0A= sum +=3D abs(s0[i] - s1[i]); // sad =0A= sum +=3D n[i]; // normal =0A= }=0A= =0A= The vector size is 128-bit=1B$B!$=1B(Bvectorization factor is 16. Reduction= statements=0A= would be transformed as:=0A= =0A= vector<4> int sum_v0 =3D { 0, 0, 0, 0 };=0A= vector<4> int sum_v1 =3D { 0, 0, 0, 0 };=0A= vector<4> int sum_v2 =3D { 0, 0, 0, 0 };=0A= vector<4> int sum_v3 =3D { 0, 0, 0, 0 };=0A= =0A= for (i / 16)=0A= {=0A= sum_v0 =3D DOT_PROD (d0_v0[i: 0 ~ 15], d1_v0[i: 0 ~ 15], sum_v0);=0A= sum_v1 =3D sum_v1; // copy=0A= sum_v2 =3D sum_v2; // copy=0A= sum_v3 =3D sum_v3; // copy=0A= =0A= sum_v0 =3D sum_v0; // copy=0A= sum_v1 =3D WIDEN_SUM (w_v1[i: 0 ~ 15], sum_v1);=0A= sum_v2 =3D sum_v2; // copy=0A= sum_v3 =3D sum_v3; // copy=0A= =0A= sum_v0 =3D sum_v0; // copy=0A= sum_v1 =3D sum_v1; // copy=0A= sum_v2 =3D SAD (s0_v2[i: 0 ~ 7 ], s1_v2[i: 0 ~ 7 ], sum_v2);=0A= sum_v3 =3D SAD (s0_v3[i: 8 ~ 15], s1_v3[i: 8 ~ 15], sum_v3);=0A= =0A= sum_v0 +=3D n_v0[i: 0 ~ 3 ];=0A= sum_v1 +=3D n_v1[i: 4 ~ 7 ];=0A= sum_v2 +=3D n_v2[i: 8 ~ 11];=0A= sum_v3 +=3D n_v3[i: 12 ~ 15];=0A= }=0A= =0A= Moreover, for a higher instruction parallelism in final vectorized loop, it= =0A= is considered to make those effective vectorized lane-reducing statements b= e=0A= distributed evenly among all def-use cycles. In the above example, DOT_PROD= ,=0A= WIDEN_SUM and SADs are generated into disparate cycles.=0A= =0A= Bootstrapped/regtested on x86_64-linux and aarch64-linux.=0A= =0A= Feng=0A= -------=0A= gcc/=0A= PR tree-optimization/114440=0A= * tree-vectorizer.h (struct _stmt_vec_info): Add a new field=0A= reduc_result_pos.=0A= (vectorizable_lane_reducing): New function declaration.=0A= * tree-vect-stmts.cc (vectorizable_condition): Treat the condition=0A= statement that is pointed by stmt_vec_info of reduction PHI as the=0A= real "for_reduction" statement.=0A= (vect_analyze_stmt): Call new function vectorizable_lane_reducing=0A= to analyze lane-reducing operation.=0A= * tree-vect-loop.cc (vect_is_emulated_mixed_dot_prod): Remove parameter=0A= loop_vinfo. Get input vectype from stmt_info instead of reduction PHI.=0A= (vect_model_reduction_cost): Remove cost computation code related to=0A= emulated_mixed_dot_prod.=0A= (vect_reduction_use_partial_vector): New function.=0A= (vectorizable_lane_reducing): New function.=0A= (vectorizable_reduction): Allow multiple lane-reducing operations in=0A= loop reduction. Move some original lane-reducing related code to=0A= vectorizable_lane_reducing, and move partial vectorization checking=0A= code to vect_reduction_use_partial_vector.=0A= (vect_transform_reduction): Extend transformation to support reduction=0A= statements with mixed input vectypes.=0A= =0A= gcc/testsuite/=0A= PR tree-optimization/114440=0A= * gcc.dg/vect/vect-reduc-chain-1.c=0A= * gcc.dg/vect/vect-reduc-chain-2.c=0A= * gcc.dg/vect/vect-reduc-chain-3.c=0A= * gcc.dg/vect/vect-reduc-dot-slp-1.c=0A= * gcc.dg/vect/vect-reduc-dot-slp-2.c=0A= ---=0A= .../gcc.dg/vect/vect-reduc-chain-1.c | 62 ++=0A= .../gcc.dg/vect/vect-reduc-chain-2.c | 77 ++=0A= .../gcc.dg/vect/vect-reduc-chain-3.c | 66 ++=0A= .../gcc.dg/vect/vect-reduc-dot-slp-1.c | 97 +++=0A= .../gcc.dg/vect/vect-reduc-dot-slp-2.c | 81 +++=0A= gcc/tree-vect-loop.cc | 668 ++++++++++++------=0A= gcc/tree-vect-stmts.cc | 13 +-=0A= gcc/tree-vectorizer.h | 8 +=0A= 8 files changed, 863 insertions(+), 209 deletions(-)=0A= create mode 100644 gcc/testsuite/gcc.dg/vect/vect-reduc-chain-1.c=0A= create mode 100644 gcc/testsuite/gcc.dg/vect/vect-reduc-chain-2.c=0A= create mode 100644 gcc/testsuite/gcc.dg/vect/vect-reduc-chain-3.c=0A= create mode 100644 gcc/testsuite/gcc.dg/vect/vect-reduc-dot-slp-1.c=0A= create mode 100644 gcc/testsuite/gcc.dg/vect/vect-reduc-dot-slp-2.c=0A= =0A= diff --git a/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-1.c b/gcc/testsuite= /gcc.dg/vect/vect-reduc-chain-1.c=0A= new file mode 100644=0A= index 00000000000..04bfc419dbd=0A= --- /dev/null=0A= +++ b/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-1.c=0A= @@ -0,0 +1,62 @@=0A= +/* Disabling epilogues until we find a better way to deal with scans. */= =0A= +/* { dg-additional-options "--param vect-epilogues-nomask=3D0" } */=0A= +/* { dg-require-effective-target vect_int } */=0A= +/* { dg-require-effective-target arm_v8_2a_dotprod_neon_hw { target { aarc= h64*-*-* || arm*-*-* } } } */=0A= +/* { dg-add-options arm_v8_2a_dotprod_neon } */=0A= +=0A= +#include "tree-vect.h"=0A= +=0A= +#define N 50=0A= +=0A= +#ifndef SIGNEDNESS_1=0A= +#define SIGNEDNESS_1 signed=0A= +#define SIGNEDNESS_2 signed=0A= +#endif=0A= +=0A= +SIGNEDNESS_1 int __attribute__ ((noipa))=0A= +f (SIGNEDNESS_1 int res,=0A= + SIGNEDNESS_2 char *restrict a,=0A= + SIGNEDNESS_2 char *restrict b,=0A= + SIGNEDNESS_2 char *restrict c,=0A= + SIGNEDNESS_2 char *restrict d,=0A= + SIGNEDNESS_1 int *restrict e)=0A= +{=0A= + for (int i =3D 0; i < N; ++i)=0A= + {=0A= + res +=3D a[i] * b[i];=0A= + res +=3D c[i] * d[i];=0A= + res +=3D e[i];=0A= + }=0A= + return res;=0A= +}=0A= +=0A= +#define BASE ((SIGNEDNESS_2 int) -1 < 0 ? -126 : 4)=0A= +#define OFFSET 20=0A= +=0A= +int=0A= +main (void)=0A= +{=0A= + check_vect ();=0A= +=0A= + SIGNEDNESS_2 char a[N], b[N];=0A= + SIGNEDNESS_2 char c[N], d[N];=0A= + SIGNEDNESS_1 int e[N];=0A= + int expected =3D 0x12345;=0A= + for (int i =3D 0; i < N; ++i)=0A= + {=0A= + a[i] =3D BASE + i * 5;=0A= + b[i] =3D BASE + OFFSET + i * 4;=0A= + c[i] =3D BASE + i * 2;=0A= + d[i] =3D BASE + OFFSET + i * 3;=0A= + e[i] =3D i;=0A= + asm volatile ("" ::: "memory");=0A= + expected +=3D a[i] * b[i];=0A= + expected +=3D c[i] * d[i];=0A= + expected +=3D e[i];=0A= + }=0A= + if (f (0x12345, a, b, c, d, e) !=3D expected)=0A= + __builtin_abort ();=0A= +}=0A= +=0A= +/* { dg-final { scan-tree-dump "vect_recog_dot_prod_pattern: detected" "ve= ct" } } */=0A= +/* { dg-final { scan-tree-dump-times "vectorizing statement: \\S+ =3D DOT_= PROD_EXPR" 2 "vect" { target vect_sdot_qi } } } */=0A= diff --git a/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-2.c b/gcc/testsuite= /gcc.dg/vect/vect-reduc-chain-2.c=0A= new file mode 100644=0A= index 00000000000..6c803b80120=0A= --- /dev/null=0A= +++ b/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-2.c=0A= @@ -0,0 +1,77 @@=0A= +/* Disabling epilogues until we find a better way to deal with scans. */= =0A= +/* { dg-additional-options "--param vect-epilogues-nomask=3D0" } */=0A= +/* { dg-require-effective-target vect_int } */=0A= +/* { dg-require-effective-target arm_v8_2a_dotprod_neon_hw { target { aarc= h64*-*-* || arm*-*-* } } } */=0A= +/* { dg-add-options arm_v8_2a_dotprod_neon } */=0A= +=0A= +#include "tree-vect.h"=0A= +=0A= +#define N 50=0A= +=0A= +#ifndef SIGNEDNESS_1=0A= +#define SIGNEDNESS_1 signed=0A= +#define SIGNEDNESS_2 unsigned=0A= +#define SIGNEDNESS_3 signed=0A= +#define SIGNEDNESS_4 signed=0A= +#endif=0A= +=0A= +SIGNEDNESS_1 int __attribute__ ((noipa))=0A= +fn (SIGNEDNESS_1 int res,=0A= + SIGNEDNESS_2 char *restrict a,=0A= + SIGNEDNESS_2 char *restrict b,=0A= + SIGNEDNESS_3 char *restrict c,=0A= + SIGNEDNESS_3 char *restrict d,=0A= + SIGNEDNESS_4 short *restrict e,=0A= + SIGNEDNESS_4 short *restrict f,=0A= + SIGNEDNESS_1 int *restrict g)=0A= +{=0A= + for (int i =3D 0; i < N; ++i)=0A= + {=0A= + res +=3D a[i] * b[i];=0A= + res +=3D i + 1;=0A= + res +=3D c[i] * d[i];=0A= + res +=3D e[i] * f[i];=0A= + res +=3D g[i];=0A= + }=0A= + return res;=0A= +}=0A= +=0A= +#define BASE2 ((SIGNEDNESS_2 int) -1 < 0 ? -126 : 4)=0A= +#define BASE3 ((SIGNEDNESS_3 int) -1 < 0 ? -126 : 4)=0A= +#define BASE4 ((SIGNEDNESS_4 int) -1 < 0 ? -1026 : 373)=0A= +#define OFFSET 20=0A= +=0A= +int=0A= +main (void)=0A= +{=0A= + check_vect ();=0A= +=0A= + SIGNEDNESS_2 char a[N], b[N];=0A= + SIGNEDNESS_3 char c[N], d[N];=0A= + SIGNEDNESS_4 short e[N], f[N];=0A= + SIGNEDNESS_1 int g[N];=0A= + int expected =3D 0x12345;=0A= + for (int i =3D 0; i < N; ++i)=0A= + {=0A= + a[i] =3D BASE2 + i * 5;=0A= + b[i] =3D BASE2 + OFFSET + i * 4;=0A= + c[i] =3D BASE3 + i * 2;=0A= + d[i] =3D BASE3 + OFFSET + i * 3;=0A= + e[i] =3D BASE4 + i * 6;=0A= + f[i] =3D BASE4 + OFFSET + i * 5;=0A= + g[i] =3D i;=0A= + asm volatile ("" ::: "memory");=0A= + expected +=3D a[i] * b[i];=0A= + expected +=3D i + 1;=0A= + expected +=3D c[i] * d[i];=0A= + expected +=3D e[i] * f[i];=0A= + expected +=3D g[i];=0A= + }=0A= + if (fn (0x12345, a, b, c, d, e, f, g) !=3D expected)=0A= + __builtin_abort ();=0A= +}=0A= +=0A= +/* { dg-final { scan-tree-dump "vect_recog_dot_prod_pattern: detected" "ve= ct" } } */=0A= +/* { dg-final { scan-tree-dump "vectorizing statement: \\S+ =3D DOT_PROD_E= XPR" "vect" { target { vect_sdot_qi } } } } */=0A= +/* { dg-final { scan-tree-dump "vectorizing statement: \\S+ =3D DOT_PROD_E= XPR" "vect" { target { vect_udot_qi } } } } */=0A= +/* { dg-final { scan-tree-dump "vectorizing statement: \\S+ =3D DOT_PROD_E= XPR" "vect" { target { vect_sdot_hi } } } } */=0A= diff --git a/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-3.c b/gcc/testsuite= /gcc.dg/vect/vect-reduc-chain-3.c=0A= new file mode 100644=0A= index 00000000000..a41e4b176c4=0A= --- /dev/null=0A= +++ b/gcc/testsuite/gcc.dg/vect/vect-reduc-chain-3.c=0A= @@ -0,0 +1,66 @@=0A= +/* Disabling epilogues until we find a better way to deal with scans. */= =0A= +/* { dg-additional-options "--param vect-epilogues-nomask=3D0" } */=0A= +/* { dg-require-effective-target vect_int } */=0A= +=0A= +#include "tree-vect.h"=0A= +=0A= +#define N 50=0A= +=0A= +#ifndef SIGNEDNESS_1=0A= +#define SIGNEDNESS_1 signed=0A= +#define SIGNEDNESS_2 unsigned=0A= +#define SIGNEDNESS_3 signed=0A= +#endif=0A= +=0A= +SIGNEDNESS_1 int __attribute__ ((noipa))=0A= +f (SIGNEDNESS_1 int res,=0A= + SIGNEDNESS_2 char *restrict a,=0A= + SIGNEDNESS_2 char *restrict b,=0A= + SIGNEDNESS_3 short *restrict c,=0A= + SIGNEDNESS_3 short *restrict d,=0A= + SIGNEDNESS_1 int *restrict e)=0A= +{=0A= + for (int i =3D 0; i < N; ++i)=0A= + {=0A= + short diff =3D a[i] - b[i];=0A= + SIGNEDNESS_2 short abs =3D diff < 0 ? -diff : diff;=0A= + res +=3D abs;=0A= + res +=3D c[i] * d[i];=0A= + res +=3D e[i];=0A= + }=0A= + return res;=0A= +}=0A= +=0A= +#define BASE2 ((SIGNEDNESS_2 int) -1 < 0 ? -126 : 4)=0A= +#define BASE3 ((SIGNEDNESS_3 int) -1 < 0 ? -1236 : 373)=0A= +#define OFFSET 20=0A= +=0A= +int=0A= +main (void)=0A= +{=0A= + check_vect ();=0A= +=0A= + SIGNEDNESS_2 char a[N], b[N];=0A= + SIGNEDNESS_3 short c[N], d[N];=0A= + SIGNEDNESS_1 int e[N];=0A= + int expected =3D 0x12345;=0A= + for (int i =3D 0; i < N; ++i)=0A= + {=0A= + a[i] =3D BASE2 + i * 5;=0A= + b[i] =3D BASE2 - i * 4;=0A= + c[i] =3D BASE3 + i * 2;=0A= + d[i] =3D BASE3 + OFFSET + i * 3;=0A= + e[i] =3D i;=0A= + asm volatile ("" ::: "memory");=0A= + short diff =3D a[i] - b[i];=0A= + SIGNEDNESS_2 short abs =3D diff < 0 ? -diff : diff;=0A= + expected +=3D abs;=0A= + expected +=3D c[i] * d[i];=0A= + expected +=3D e[i];=0A= + }=0A= + if (f (0x12345, a, b, c, d, e) !=3D expected)=0A= + __builtin_abort ();=0A= +}=0A= +=0A= +/* { dg-final { scan-tree-dump "vectorizing statement: \\S+ =3D SAD_EXPR" = "vect" { target vect_udot_qi } } } */=0A= +/* { dg-final { scan-tree-dump "vectorizing statement: \\S+ =3D DOT_PROD_E= XPR" "vect" { target vect_sdot_hi } } } */=0A= diff --git a/gcc/testsuite/gcc.dg/vect/vect-reduc-dot-slp-1.c b/gcc/testsui= te/gcc.dg/vect/vect-reduc-dot-slp-1.c=0A= new file mode 100644=0A= index 00000000000..51ef4eaaed8=0A= --- /dev/null=0A= +++ b/gcc/testsuite/gcc.dg/vect/vect-reduc-dot-slp-1.c=0A= @@ -0,0 +1,97 @@=0A= +/* Disabling epilogues until we find a better way to deal with scans. */= =0A= +/* { dg-additional-options "--param vect-epilogues-nomask=3D0" } */=0A= +/* { dg-require-effective-target vect_int } */=0A= +/* { dg-require-effective-target arm_v8_2a_dotprod_neon_hw { target { aarc= h64*-*-* || arm*-*-* } } } */=0A= +/* { dg-add-options arm_v8_2a_dotprod_neon } */=0A= +=0A= +#include "tree-vect.h"=0A= +=0A= +#define N 50=0A= +=0A= +#ifndef SIGNEDNESS_1=0A= +#define SIGNEDNESS_1 signed=0A= +#define SIGNEDNESS_2 signed=0A= +#endif=0A= +=0A= +SIGNEDNESS_1 int __attribute__ ((noipa))=0A= +f (SIGNEDNESS_1 int res,=0A= + SIGNEDNESS_2 char *a,=0A= + SIGNEDNESS_2 char *b,=0A= + int step, int n)=0A= +{=0A= + for (int i =3D 0; i < n; i++)=0A= + {=0A= + res +=3D a[0] * b[0];=0A= + res +=3D a[1] * b[1];=0A= + res +=3D a[2] * b[2];=0A= + res +=3D a[3] * b[3];=0A= + res +=3D a[4] * b[4];=0A= + res +=3D a[5] * b[5];=0A= + res +=3D a[6] * b[6];=0A= + res +=3D a[7] * b[7];=0A= + res +=3D a[8] * b[8];=0A= + res +=3D a[9] * b[9];=0A= + res +=3D a[10] * b[10];=0A= + res +=3D a[11] * b[11];=0A= + res +=3D a[12] * b[12];=0A= + res +=3D a[13] * b[13];=0A= + res +=3D a[14] * b[14];=0A= + res +=3D a[15] * b[15];=0A= +=0A= + a +=3D step;=0A= + b +=3D step;=0A= + }=0A= +=0A= + return res;=0A= +}=0A= +=0A= +#define BASE ((SIGNEDNESS_2 int) -1 < 0 ? -126 : 4)=0A= +#define OFFSET 20=0A= +=0A= +int=0A= +main (void)=0A= +{=0A= + check_vect ();=0A= +=0A= + SIGNEDNESS_2 char a[100], b[100];=0A= + int expected =3D 0x12345;=0A= + int step =3D 16;=0A= + int n =3D 2;=0A= + int t =3D 0;=0A= +=0A= + for (int i =3D 0; i < sizeof (a) / sizeof (a[0]); ++i)=0A= + {=0A= + a[i] =3D BASE + i * 5;=0A= + b[i] =3D BASE + OFFSET + i * 4;=0A= + asm volatile ("" ::: "memory");=0A= + }=0A= +=0A= + for (int i =3D 0; i < n; i++)=0A= + {=0A= + asm volatile ("" ::: "memory");=0A= + expected +=3D a[t + 0] * b[t + 0];=0A= + expected +=3D a[t + 1] * b[t + 1];=0A= + expected +=3D a[t + 2] * b[t + 2];=0A= + expected +=3D a[t + 3] * b[t + 3];=0A= + expected +=3D a[t + 4] * b[t + 4];=0A= + expected +=3D a[t + 5] * b[t + 5];=0A= + expected +=3D a[t + 6] * b[t + 6];=0A= + expected +=3D a[t + 7] * b[t + 7];=0A= + expected +=3D a[t + 8] * b[t + 8];=0A= + expected +=3D a[t + 9] * b[t + 9];=0A= + expected +=3D a[t + 10] * b[t + 10];=0A= + expected +=3D a[t + 11] * b[t + 11];=0A= + expected +=3D a[t + 12] * b[t + 12];=0A= + expected +=3D a[t + 13] * b[t + 13];=0A= + expected +=3D a[t + 14] * b[t + 14];=0A= + expected +=3D a[t + 15] * b[t + 15];=0A= + t +=3D step;=0A= + }=0A= +=0A= + if (f (0x12345, a, b, step, n) !=3D expected)=0A= + __builtin_abort ();=0A= +}=0A= +=0A= +/* { dg-final { scan-tree-dump "vect_recog_dot_prod_pattern: detected" "ve= ct" } } */=0A= +/* { dg-final { scan-tree-dump "vectorizing stmts using SLP" "vect" } } */= =0A= +/* { dg-final { scan-tree-dump-times "vectorizing statement: \\S+ =3D DOT_= PROD_EXPR" 16 "vect" } } */=0A= diff --git a/gcc/testsuite/gcc.dg/vect/vect-reduc-dot-slp-2.c b/gcc/testsui= te/gcc.dg/vect/vect-reduc-dot-slp-2.c=0A= new file mode 100644=0A= index 00000000000..1532833c3ae=0A= --- /dev/null=0A= +++ b/gcc/testsuite/gcc.dg/vect/vect-reduc-dot-slp-2.c=0A= @@ -0,0 +1,81 @@=0A= +/* Disabling epilogues until we find a better way to deal with scans. */= =0A= +/* { dg-additional-options "--param vect-epilogues-nomask=3D0" } */=0A= +/* { dg-require-effective-target vect_int } */=0A= +/* { dg-require-effective-target arm_v8_2a_dotprod_neon_hw { target { aarc= h64*-*-* || arm*-*-* } } } */=0A= +/* { dg-add-options arm_v8_2a_dotprod_neon } */=0A= +=0A= +#include "tree-vect.h"=0A= +=0A= +#define N 50=0A= +=0A= +#ifndef SIGNEDNESS_1=0A= +#define SIGNEDNESS_1 signed=0A= +#define SIGNEDNESS_2 signed=0A= +#endif=0A= +=0A= +SIGNEDNESS_1 int __attribute__ ((noipa))=0A= +f (SIGNEDNESS_1 int res,=0A= + SIGNEDNESS_2 short *a,=0A= + SIGNEDNESS_2 short *b,=0A= + int step, int n)=0A= +{=0A= + for (int i =3D 0; i < n; i++)=0A= + {=0A= + res +=3D a[0] * b[0];=0A= + res +=3D a[1] * b[1];=0A= + res +=3D a[2] * b[2];=0A= + res +=3D a[3] * b[3];=0A= + res +=3D a[4] * b[4];=0A= + res +=3D a[5] * b[5];=0A= + res +=3D a[6] * b[6];=0A= + res +=3D a[7] * b[7];=0A= +=0A= + a +=3D step;=0A= + b +=3D step;=0A= + }=0A= +=0A= + return res;=0A= +}=0A= +=0A= +#define BASE ((SIGNEDNESS_2 int) -1 < 0 ? -1026 : 373)=0A= +#define OFFSET 20=0A= +=0A= +int=0A= +main (void)=0A= +{=0A= + check_vect ();=0A= +=0A= + SIGNEDNESS_2 short a[100], b[100];=0A= + int expected =3D 0x12345;=0A= + int step =3D 8;=0A= + int n =3D 2;=0A= + int t =3D 0;=0A= +=0A= + for (int i =3D 0; i < sizeof (a) / sizeof (a[0]); ++i)=0A= + {=0A= + a[i] =3D BASE + i * 5;=0A= + b[i] =3D BASE + OFFSET + i * 4;=0A= + asm volatile ("" ::: "memory");=0A= + }=0A= +=0A= + for (int i =3D 0; i < n; i++)=0A= + {=0A= + asm volatile ("" ::: "memory");=0A= + expected +=3D a[t + 0] * b[t + 0];=0A= + expected +=3D a[t + 1] * b[t + 1];=0A= + expected +=3D a[t + 2] * b[t + 2];=0A= + expected +=3D a[t + 3] * b[t + 3];=0A= + expected +=3D a[t + 4] * b[t + 4];=0A= + expected +=3D a[t + 5] * b[t + 5];=0A= + expected +=3D a[t + 6] * b[t + 6];=0A= + expected +=3D a[t + 7] * b[t + 7];=0A= + t +=3D step;=0A= + }=0A= +=0A= + if (f (0x12345, a, b, step, n) !=3D expected)=0A= + __builtin_abort ();=0A= +}=0A= +=0A= +/* { dg-final { scan-tree-dump "vect_recog_dot_prod_pattern: detected" "ve= ct" } } */=0A= +/* { dg-final { scan-tree-dump "vectorizing stmts using SLP" "vect" } } */= =0A= +/* { dg-final { scan-tree-dump-times "vectorizing statement: \\S+ =3D DOT_= PROD_EXPR" 8 "vect" { target vect_sdot_hi } } } */=0A= diff --git a/gcc/tree-vect-loop.cc b/gcc/tree-vect-loop.cc=0A= index 984636edbc5..5a3339b6594 100644=0A= --- a/gcc/tree-vect-loop.cc=0A= +++ b/gcc/tree-vect-loop.cc=0A= @@ -5269,8 +5269,7 @@ have_whole_vector_shift (machine_mode mode)=0A= See vect_emulate_mixed_dot_prod for the actual sequence used. */=0A= =0A= static bool=0A= -vect_is_emulated_mixed_dot_prod (loop_vec_info loop_vinfo,=0A= - stmt_vec_info stmt_info)=0A= +vect_is_emulated_mixed_dot_prod (stmt_vec_info stmt_info)=0A= {=0A= gassign *assign =3D dyn_cast (stmt_info->stmt);=0A= if (!assign || gimple_assign_rhs_code (assign) !=3D DOT_PROD_EXPR)=0A= @@ -5281,10 +5280,9 @@ vect_is_emulated_mixed_dot_prod (loop_vec_info loop_= vinfo,=0A= if (TYPE_SIGN (TREE_TYPE (rhs1)) =3D=3D TYPE_SIGN (TREE_TYPE (rhs2)))=0A= return false;=0A= =0A= - stmt_vec_info reduc_info =3D info_for_reduction (loop_vinfo, stmt_info);= =0A= - gcc_assert (reduc_info->is_reduc_info);=0A= + gcc_assert (STMT_VINFO_REDUC_VECTYPE_IN (stmt_info));=0A= return !directly_supported_p (DOT_PROD_EXPR,=0A= - STMT_VINFO_REDUC_VECTYPE_IN (reduc_info),=0A= + STMT_VINFO_REDUC_VECTYPE_IN (stmt_info),=0A= optab_vector_mixed_sign);=0A= }=0A= =0A= @@ -5323,8 +5321,6 @@ vect_model_reduction_cost (loop_vec_info loop_vinfo,= =0A= if (!gimple_extract_op (orig_stmt_info->stmt, &op))=0A= gcc_unreachable ();=0A= =0A= - bool emulated_mixed_dot_prod=0A= - =3D vect_is_emulated_mixed_dot_prod (loop_vinfo, stmt_info);=0A= if (reduction_type =3D=3D EXTRACT_LAST_REDUCTION)=0A= /* No extra instructions are needed in the prologue. The loop body=0A= operations are costed in vectorizable_condition. */=0A= @@ -5359,12 +5355,8 @@ vect_model_reduction_cost (loop_vec_info loop_vinfo,= =0A= initial result of the data reduction, initial value of the index=0A= reduction. */=0A= prologue_stmts =3D 4;=0A= - else if (emulated_mixed_dot_prod)=0A= - /* We need the initial reduction value and two invariants:=0A= - one that contains the minimum signed value and one that=0A= - contains half of its negative. */=0A= - prologue_stmts =3D 3;=0A= else=0A= + /* We need the initial reduction value. */=0A= prologue_stmts =3D 1;=0A= prologue_cost +=3D record_stmt_cost (cost_vec, prologue_stmts,=0A= scalar_to_vec, stmt_info, 0,=0A= @@ -7376,6 +7368,244 @@ build_vect_cond_expr (code_helper code, tree vop[3]= , tree mask,=0A= }=0A= }=0A= =0A= +/* Given an operation with CODE in loop reduction path whose reduction PHI= is=0A= + specified by REDUC_INFO, the operation has TYPE of scalar result, and i= ts=0A= + input vectype is represented by VECTYPE_IN. The vectype of vectorized r= esult=0A= + may be different from VECTYPE_IN, either in base type or vectype lanes,= =0A= + lane-reducing operation is the case. This function check if it is poss= ible,=0A= + and how to perform partial vectorization on the operation in the contex= t=0A= + of LOOP_VINFO. */=0A= +=0A= +static void=0A= +vect_reduction_use_partial_vector (loop_vec_info loop_vinfo,=0A= + stmt_vec_info reduc_info,=0A= + slp_tree slp_node, code_helper code,=0A= + tree type, tree vectype_in)=0A= +{=0A= + if (!LOOP_VINFO_CAN_USE_PARTIAL_VECTORS_P (loop_vinfo))=0A= + return;=0A= +=0A= + enum vect_reduction_type reduc_type =3D STMT_VINFO_REDUC_TYPE (reduc_inf= o);=0A= + internal_fn reduc_fn =3D STMT_VINFO_REDUC_FN (reduc_info);=0A= + internal_fn cond_fn =3D get_conditional_internal_fn (code, type);=0A= +=0A= + if (reduc_type !=3D FOLD_LEFT_REDUCTION=0A= + && !use_mask_by_cond_expr_p (code, cond_fn, vectype_in)=0A= + && (cond_fn =3D=3D IFN_LAST=0A= + || !direct_internal_fn_supported_p (cond_fn, vectype_in,=0A= + OPTIMIZE_FOR_SPEED)))=0A= + {=0A= + if (dump_enabled_p ())=0A= + dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location,=0A= + "can't operate on partial vectors because"=0A= + " no conditional operation is available.\n");=0A= + LOOP_VINFO_CAN_USE_PARTIAL_VECTORS_P (loop_vinfo) =3D false;=0A= + }=0A= + else if (reduc_type =3D=3D FOLD_LEFT_REDUCTION=0A= + && reduc_fn =3D=3D IFN_LAST=0A= + && !expand_vec_cond_expr_p (vectype_in, truth_type_for (vectype_in),= =0A= + SSA_NAME))=0A= + {=0A= + if (dump_enabled_p ())=0A= + dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location,=0A= + "can't operate on partial vectors because"=0A= + " no conditional operation is available.\n");=0A= + LOOP_VINFO_CAN_USE_PARTIAL_VECTORS_P (loop_vinfo) =3D false;=0A= + }=0A= + else if (reduc_type =3D=3D FOLD_LEFT_REDUCTION=0A= + && internal_fn_mask_index (reduc_fn) =3D=3D -1=0A= + && FLOAT_TYPE_P (vectype_in)=0A= + && HONOR_SIGN_DEPENDENT_ROUNDING (vectype_in))=0A= + {=0A= + if (dump_enabled_p ())=0A= + dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location,=0A= + "can't operate on partial vectors because"=0A= + " signed zeros cannot be preserved.\n");=0A= + LOOP_VINFO_CAN_USE_PARTIAL_VECTORS_P (loop_vinfo) =3D false;=0A= + }=0A= + else=0A= + {=0A= + internal_fn mask_reduc_fn=0A= + =3D get_masked_reduction_fn (reduc_fn, vectype_in);=0A= + vec_loop_masks *masks =3D &LOOP_VINFO_MASKS (loop_vinfo);=0A= + vec_loop_lens *lens =3D &LOOP_VINFO_LENS (loop_vinfo);=0A= + unsigned nvectors;=0A= +=0A= + if (slp_node)=0A= + nvectors =3D SLP_TREE_NUMBER_OF_VEC_STMTS (slp_node);=0A= + else=0A= + nvectors =3D vect_get_num_copies (loop_vinfo, vectype_in);=0A= +=0A= + if (mask_reduc_fn =3D=3D IFN_MASK_LEN_FOLD_LEFT_PLUS)=0A= + vect_record_loop_len (loop_vinfo, lens, nvectors, vectype_in, 1);=0A= + else=0A= + vect_record_loop_mask (loop_vinfo, masks, nvectors, vectype_in, NULL);=0A= + }=0A= +}=0A= +=0A= +/* Check if STMT_INFO is a lane-reducing operation that can be vectorized = in=0A= + the context of LOOP_VINFO, and vector cost will be recorded in COST_VEC= .=0A= + Now there are three such kinds of operations: dot-prod/widen-sum/sad=0A= + (sum-of-absolute-differences).=0A= +=0A= + For a lane-reducing operation, the loop reduction path that it lies in,= =0A= + may contain normal operation, or other lane-reducing operation of diffe= rent=0A= + input type size, an example as:=0A= +=0A= + int sum =3D 0;=0A= + for (i)=0A= + {=0A= + ...=0A= + sum +=3D d0[i] * d1[i]; // dot-prod =0A= + sum +=3D w[i]; // widen-sum =0A= + sum +=3D abs(s0[i] - s1[i]); // sad =0A= + sum +=3D n[i]; // normal =0A= + ...=0A= + }=0A= +=0A= + Vectorization factor is essentially determined by operation whose input= =0A= + vectype has the most lanes ("vector(16) char" in the example), while we= =0A= + need to choose input vectype with the least lanes ("vector(4) int" in t= he=0A= + example) for the reduction PHI statement. */=0A= +=0A= +bool=0A= +vectorizable_lane_reducing (loop_vec_info loop_vinfo, stmt_vec_info stmt_i= nfo,=0A= + slp_tree slp_node, stmt_vector_for_cost *cost_vec)=0A= +{=0A= + gassign *stmt =3D dyn_cast (stmt_info->stmt);=0A= + if (!stmt)=0A= + return false;=0A= +=0A= + enum tree_code code =3D gimple_assign_rhs_code (stmt);=0A= +=0A= + if (code !=3D DOT_PROD_EXPR && code !=3D WIDEN_SUM_EXPR && code !=3D SAD= _EXPR)=0A= + return false;=0A= +=0A= + tree type =3D TREE_TYPE (gimple_assign_lhs (stmt));=0A= +=0A= + if (!INTEGRAL_TYPE_P (type) && !SCALAR_FLOAT_TYPE_P (type))=0A= + return false;=0A= +=0A= + /* Do not try to vectorize bit-precision reductions. */=0A= + if (!type_has_mode_precision_p (type))=0A= + return false;=0A= +=0A= + tree vectype_in =3D NULL_TREE;=0A= +=0A= + for (int i =3D 0; i < (int) gimple_num_ops (stmt) - 1; i++)=0A= + {=0A= + stmt_vec_info def_stmt_info;=0A= + slp_tree slp_op;=0A= + tree op;=0A= + tree vectype;=0A= + enum vect_def_type dt;=0A= +=0A= + if (!vect_is_simple_use (loop_vinfo, stmt_info, slp_node, i, &op,=0A= + &slp_op, &dt, &vectype, &def_stmt_info))=0A= + {=0A= + if (dump_enabled_p ())=0A= + dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location,=0A= + "use not simple.\n");=0A= + return false;=0A= + }=0A= +=0A= + if (!vectype)=0A= + {=0A= + vectype =3D get_vectype_for_scalar_type (loop_vinfo, TREE_TYPE (op),=0A= + slp_op);=0A= + if (!vectype)=0A= + return false;=0A= + }=0A= +=0A= + if (slp_node && !vect_maybe_update_slp_op_vectype (slp_op, vectype))= =0A= + {=0A= + if (dump_enabled_p ())=0A= + dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location,=0A= + "incompatible vector types for invariants\n");=0A= + return false;=0A= + }=0A= +=0A= + if (i =3D=3D STMT_VINFO_REDUC_IDX (stmt_info))=0A= + continue;=0A= +=0A= + /* There should be at most one cycle def in the stmt. */=0A= + if (VECTORIZABLE_CYCLE_DEF (dt))=0A= + return false;=0A= +=0A= + /* To properly compute ncopies we are interested in the widest=0A= + non-reduction input type in case we're looking at a widening=0A= + accumulation that we later handle in vect transformation. */=0A= + if (!vectype_in=0A= + || (GET_MODE_SIZE (SCALAR_TYPE_MODE (TREE_TYPE (vectype_in)))=0A= + < GET_MODE_SIZE (SCALAR_TYPE_MODE (TREE_TYPE (vectype)))))=0A= + vectype_in =3D vectype;=0A= + }=0A= +=0A= + STMT_VINFO_REDUC_VECTYPE_IN (stmt_info) =3D vectype_in;=0A= +=0A= + stmt_vec_info reduc_info =3D STMT_VINFO_REDUC_DEF (vect_orig_stmt (stmt_= info));=0A= +=0A= + /* TODO: Support lane-reducing operation that does not directly particip= ate=0A= + in loop reduction. */=0A= + if (!reduc_info || STMT_VINFO_REDUC_IDX (stmt_info) < 0)=0A= + return false;=0A= +=0A= + /* Lane-reducing pattern inside any inner loop of LOOP_VINFO is not=0A= + recoginized. */=0A= + gcc_assert (STMT_VINFO_DEF_TYPE (reduc_info) =3D=3D vect_reduction_def);= =0A= + gcc_assert (STMT_VINFO_REDUC_TYPE (reduc_info) =3D=3D TREE_CODE_REDUCTIO= N);=0A= +=0A= + tree vphi_vectype_in =3D STMT_VINFO_REDUC_VECTYPE_IN (reduc_info);=0A= +=0A= + /* To accommodate lane-reducing operations of mixed input vectypes, choo= se=0A= + input vectype with the least lanes for the reduction PHI statement, w= hich=0A= + would result in the most ncopies for vectorized reduction results. *= /=0A= + if (!vphi_vectype_in=0A= + || (GET_MODE_SIZE (SCALAR_TYPE_MODE (TREE_TYPE (vectype_in)))=0A= + > GET_MODE_SIZE (SCALAR_TYPE_MODE (TREE_TYPE (vphi_vectype_in)))))=0A= + STMT_VINFO_REDUC_VECTYPE_IN (reduc_info) =3D vectype_in;=0A= +=0A= + int ncopies_for_cost;=0A= +=0A= + if (slp_node)=0A= + {=0A= + /* Now lane-reducing operations in a slp node should only come from= =0A= + the same loop reduction path. */=0A= + gcc_assert (REDUC_GROUP_FIRST_ELEMENT (stmt_info));=0A= + ncopies_for_cost =3D 1;=0A= + }=0A= + else=0A= + {=0A= + ncopies_for_cost =3D vect_get_num_copies (loop_vinfo, vectype_in);= =0A= + gcc_assert (ncopies_for_cost >=3D 1);=0A= + }=0A= +=0A= + if (vect_is_emulated_mixed_dot_prod (stmt_info))=0A= + {=0A= + /* We need extra two invariants: one that contains the minimum signe= d=0A= + value and one that contains half of its negative. */=0A= + int prologue_stmts =3D 2;=0A= + unsigned cost =3D record_stmt_cost (cost_vec, prologue_stmts,=0A= + scalar_to_vec, stmt_info, 0,=0A= + vect_prologue);=0A= + if (dump_enabled_p ())=0A= + dump_printf (MSG_NOTE, "vectorizable_lane_reducing: "=0A= + "extra prologue_cost =3D %d .\n", cost);=0A= +=0A= + /* Three dot-products and a subtraction. */=0A= + ncopies_for_cost *=3D 4;=0A= + }=0A= +=0A= + record_stmt_cost (cost_vec, ncopies_for_cost, vector_stmt, stmt_info, 0,= =0A= + vect_body);=0A= +=0A= + vect_reduction_use_partial_vector (loop_vinfo, reduc_info, slp_node, cod= e,=0A= + type, vectype_in);=0A= +=0A= + STMT_VINFO_TYPE (stmt_info) =3D reduc_vec_info_type;=0A= + return true;=0A= +}=0A= +=0A= /* Function vectorizable_reduction.=0A= =0A= Check if STMT_INFO performs a reduction operation that can be vectorize= d.=0A= @@ -7441,7 +7671,6 @@ vectorizable_reduction (loop_vec_info loop_vinfo,=0A= bool single_defuse_cycle =3D false;=0A= bool nested_cycle =3D false;=0A= bool double_reduc =3D false;=0A= - int vec_num;=0A= tree cr_index_scalar_type =3D NULL_TREE, cr_index_vector_type =3D NULL_T= REE;=0A= tree cond_reduc_val =3D NULL_TREE;=0A= =0A= @@ -7522,6 +7751,7 @@ vectorizable_reduction (loop_vec_info loop_vinfo,=0A= (gimple_bb (reduc_def_phi)->loop_father));=0A= unsigned reduc_chain_length =3D 0;=0A= bool only_slp_reduc_chain =3D true;=0A= + bool only_lane_reduc_code_p =3D true;=0A= stmt_info =3D NULL;=0A= slp_tree slp_for_stmt_info =3D slp_node ? slp_node_instance->root : NULL= ;=0A= while (reduc_def !=3D PHI_RESULT (reduc_def_phi))=0A= @@ -7543,14 +7773,15 @@ vectorizable_reduction (loop_vec_info loop_vinfo,= =0A= all lanes here - even though we only will vectorize from=0A= the SLP node with live lane zero the other live lanes also=0A= need to be identified as part of a reduction to be able=0A= - to skip code generation for them. */=0A= + to skip code generation for them. For lane-reducing operation=0A= + vectorizable analysis needs the reduction PHI information. */=0A= if (slp_for_stmt_info)=0A= {=0A= for (auto s : SLP_TREE_SCALAR_STMTS (slp_for_stmt_info))=0A= if (STMT_VINFO_LIVE_P (s))=0A= STMT_VINFO_REDUC_DEF (vect_orig_stmt (s)) =3D phi_info;=0A= }=0A= - else if (STMT_VINFO_LIVE_P (vdef))=0A= + else=0A= STMT_VINFO_REDUC_DEF (def) =3D phi_info;=0A= gimple_match_op op;=0A= if (!gimple_extract_op (vdef->stmt, &op))=0A= @@ -7571,9 +7802,18 @@ vectorizable_reduction (loop_vec_info loop_vinfo,=0A= return false;=0A= }=0A= }=0A= - else if (!stmt_info)=0A= - /* First non-conversion stmt. */=0A= - stmt_info =3D vdef;=0A= + else=0A= + {=0A= + /* First non-conversion stmt. */=0A= + if (!stmt_info)=0A= + stmt_info =3D vdef;=0A= +=0A= + if (op.code !=3D DOT_PROD_EXPR=0A= + && op.code !=3D WIDEN_SUM_EXPR=0A= + && op.code !=3D SAD_EXPR)=0A= + only_lane_reduc_code_p =3D false;=0A= + }=0A= +=0A= reduc_def =3D op.ops[STMT_VINFO_REDUC_IDX (vdef)];=0A= reduc_chain_length++;=0A= if (!stmt_info && slp_node)=0A= @@ -7647,18 +7887,6 @@ vectorizable_reduction (loop_vec_info loop_vinfo,=0A= if (!type_has_mode_precision_p (op.type))=0A= return false;=0A= =0A= - /* For lane-reducing ops we're reducing the number of reduction PHIs=0A= - which means the only use of that may be in the lane-reducing operatio= n. */=0A= - if (lane_reduc_code_p=0A= - && reduc_chain_length !=3D 1=0A= - && !only_slp_reduc_chain)=0A= - {=0A= - if (dump_enabled_p ())=0A= - dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location,=0A= - "lane-reducing reduction with extra stmts.\n");=0A= - return false;=0A= - }=0A= -=0A= /* All uses but the last are expected to be defined in the loop.=0A= The last use is the reduction variable. In case of nested cycle this= =0A= assumption is not true: we use reduc_index to record the index of the= =0A= @@ -7687,9 +7915,6 @@ vectorizable_reduction (loop_vec_info loop_vinfo,=0A= "use not simple.\n");=0A= return false;=0A= }=0A= - if (i =3D=3D STMT_VINFO_REDUC_IDX (stmt_info))=0A= - continue;=0A= -=0A= /* For an IFN_COND_OP we might hit the reduction definition operand= =0A= twice (once as definition, once as else). */=0A= if (op.ops[i] =3D=3D op.ops[STMT_VINFO_REDUC_IDX (stmt_info)])=0A= @@ -7735,12 +7960,21 @@ vectorizable_reduction (loop_vec_info loop_vinfo,= =0A= }=0A= if (!vectype_in)=0A= vectype_in =3D STMT_VINFO_VECTYPE (phi_info);=0A= - STMT_VINFO_REDUC_VECTYPE_IN (reduc_info) =3D vectype_in;=0A= =0A= - enum vect_reduction_type v_reduc_type =3D STMT_VINFO_REDUC_TYPE (phi_inf= o);=0A= - STMT_VINFO_REDUC_TYPE (reduc_info) =3D v_reduc_type;=0A= + /* If there is a normal (non-lane-reducing) operation in the loop reduct= ion=0A= + path, to ensure there will be enough copies to hold vectorized result= s of=0A= + the operation, we need set the input vectype of the reduction PHI to = be=0A= + same as the reduction output vectype somewhere, here is a suitable pl= ace.=0A= + Otherwise the input vectype is set to the one with the least lanes, w= hich=0A= + can only be determined in vectorizable analysis routine of lane-reduc= ing=0A= + operation. */=0A= + if (!only_lane_reduc_code_p)=0A= + STMT_VINFO_REDUC_VECTYPE_IN (reduc_info) =3D STMT_VINFO_VECTYPE (phi_i= nfo);=0A= +=0A= + enum vect_reduction_type reduction_type =3D STMT_VINFO_REDUC_TYPE (phi_i= nfo);=0A= + STMT_VINFO_REDUC_TYPE (reduc_info) =3D reduction_type;=0A= /* If we have a condition reduction, see if we can simplify it further. = */=0A= - if (v_reduc_type =3D=3D COND_REDUCTION)=0A= + if (reduction_type =3D=3D COND_REDUCTION)=0A= {=0A= if (slp_node)=0A= return false;=0A= @@ -7906,8 +8140,8 @@ vectorizable_reduction (loop_vec_info loop_vinfo,=0A= }=0A= =0A= STMT_VINFO_REDUC_CODE (reduc_info) =3D orig_code;=0A= + reduction_type =3D STMT_VINFO_REDUC_TYPE (reduc_info);=0A= =0A= - vect_reduction_type reduction_type =3D STMT_VINFO_REDUC_TYPE (reduc_info= );=0A= if (reduction_type =3D=3D TREE_CODE_REDUCTION)=0A= {=0A= /* Check whether it's ok to change the order of the computation.=0A= @@ -8181,14 +8415,11 @@ vectorizable_reduction (loop_vec_info loop_vinfo,= =0A= && loop_vinfo->suggested_unroll_factor =3D=3D 1)=0A= single_defuse_cycle =3D true;=0A= =0A= - if (single_defuse_cycle || lane_reduc_code_p)=0A= + if (single_defuse_cycle && !lane_reduc_code_p)=0A= {=0A= gcc_assert (op.code !=3D COND_EXPR);=0A= =0A= - /* 4. Supportable by target? */=0A= - bool ok =3D true;=0A= -=0A= - /* 4.1. check support for the operation in the loop=0A= + /* 4. check support for the operation in the loop=0A= =0A= This isn't necessary for the lane reduction codes, since they=0A= can only be produced by pattern matching, and it's up to the=0A= @@ -8197,14 +8428,13 @@ vectorizable_reduction (loop_vec_info loop_vinfo,= =0A= mixed-sign dot-products can be implemented using signed=0A= dot-products. */=0A= machine_mode vec_mode =3D TYPE_MODE (vectype_in);=0A= - if (!lane_reduc_code_p=0A= - && !directly_supported_p (op.code, vectype_in, optab_vector))=0A= + if (!directly_supported_p (op.code, vectype_in, optab_vector))=0A= {=0A= if (dump_enabled_p ())=0A= dump_printf (MSG_NOTE, "op not supported by target.\n");=0A= if (maybe_ne (GET_MODE_SIZE (vec_mode), UNITS_PER_WORD)=0A= || !vect_can_vectorize_without_simd_p (op.code))=0A= - ok =3D false;=0A= + single_defuse_cycle =3D false;=0A= else=0A= if (dump_enabled_p ())=0A= dump_printf (MSG_NOTE, "proceeding using word mode.\n");=0A= @@ -8217,35 +8447,12 @@ vectorizable_reduction (loop_vec_info loop_vinfo,= =0A= dump_printf (MSG_NOTE, "using word mode not possible.\n");=0A= return false;=0A= }=0A= -=0A= - /* lane-reducing operations have to go through vect_transform_reduct= ion.=0A= - For the other cases try without the single cycle optimization. *= /=0A= - if (!ok)=0A= - {=0A= - if (lane_reduc_code_p)=0A= - return false;=0A= - else=0A= - single_defuse_cycle =3D false;=0A= - }=0A= }=0A= STMT_VINFO_FORCE_SINGLE_CYCLE (reduc_info) =3D single_defuse_cycle;=0A= =0A= - /* If the reduction stmt is one of the patterns that have lane=0A= - reduction embedded we cannot handle the case of ! single_defuse_cycle= . */=0A= - if ((ncopies > 1 && ! single_defuse_cycle)=0A= - && lane_reduc_code_p)=0A= - {=0A= - if (dump_enabled_p ())=0A= - dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location,=0A= - "multi def-use cycle not possible for lane-reducing "=0A= - "reduction operation\n");=0A= - return false;=0A= - }=0A= -=0A= - if (slp_node=0A= - && !(!single_defuse_cycle=0A= - && !lane_reduc_code_p=0A= - && reduction_type !=3D FOLD_LEFT_REDUCTION))=0A= + /* Reduction type of lane-reducing operation is TREE_CODE_REDUCTION, the= =0A= + below processing will be done in its own vectorizable function. */= =0A= + if (slp_node && reduction_type =3D=3D FOLD_LEFT_REDUCTION)=0A= for (i =3D 0; i < (int) op.num_ops; i++)=0A= if (!vect_maybe_update_slp_op_vectype (slp_op[i], vectype_op[i]))=0A= {=0A= @@ -8255,36 +8462,24 @@ vectorizable_reduction (loop_vec_info loop_vinfo,= =0A= return false;=0A= }=0A= =0A= - if (slp_node)=0A= - vec_num =3D SLP_TREE_NUMBER_OF_VEC_STMTS (slp_node);=0A= - else=0A= - vec_num =3D 1;=0A= -=0A= vect_model_reduction_cost (loop_vinfo, stmt_info, reduc_fn,=0A= reduction_type, ncopies, cost_vec);=0A= /* Cost the reduction op inside the loop if transformed via=0A= - vect_transform_reduction. Otherwise this is costed by the=0A= - separate vectorizable_* routines. */=0A= - if (single_defuse_cycle || lane_reduc_code_p)=0A= - {=0A= - int factor =3D 1;=0A= - if (vect_is_emulated_mixed_dot_prod (loop_vinfo, stmt_info))=0A= - /* Three dot-products and a subtraction. */=0A= - factor =3D 4;=0A= - record_stmt_cost (cost_vec, ncopies * factor, vector_stmt,=0A= - stmt_info, 0, vect_body);=0A= - }=0A= + vect_transform_reduction for non-lane-reducing operation. Otherwise= =0A= + this is costed by the separate vectorizable_* routines. */=0A= + if (single_defuse_cycle && !lane_reduc_code_p)=0A= + record_stmt_cost (cost_vec, ncopies, vector_stmt, stmt_info, 0, vect_b= ody);=0A= =0A= if (dump_enabled_p ()=0A= && reduction_type =3D=3D FOLD_LEFT_REDUCTION)=0A= dump_printf_loc (MSG_NOTE, vect_location,=0A= "using an in-order (fold-left) reduction.\n");=0A= STMT_VINFO_TYPE (orig_stmt_of_analysis) =3D cycle_phi_info_type;=0A= - /* All but single defuse-cycle optimized, lane-reducing and fold-left=0A= - reductions go through their own vectorizable_* routines. */=0A= - if (!single_defuse_cycle=0A= - && !lane_reduc_code_p=0A= - && reduction_type !=3D FOLD_LEFT_REDUCTION)=0A= +=0A= + /* All but single defuse-cycle optimized and fold-left reductions go=0A= + through their own vectorizable_* routines. */=0A= + if ((!single_defuse_cycle && reduction_type !=3D FOLD_LEFT_REDUCTION)=0A= + || lane_reduc_code_p)=0A= {=0A= stmt_vec_info tem=0A= =3D vect_stmt_to_vectorize (STMT_VINFO_REDUC_DEF (phi_info));=0A= @@ -8296,60 +8491,10 @@ vectorizable_reduction (loop_vec_info loop_vinfo,= =0A= STMT_VINFO_DEF_TYPE (vect_orig_stmt (tem)) =3D vect_internal_def;=0A= STMT_VINFO_DEF_TYPE (tem) =3D vect_internal_def;=0A= }=0A= - else if (loop_vinfo && LOOP_VINFO_CAN_USE_PARTIAL_VECTORS_P (loop_vinfo)= )=0A= - {=0A= - vec_loop_masks *masks =3D &LOOP_VINFO_MASKS (loop_vinfo);=0A= - vec_loop_lens *lens =3D &LOOP_VINFO_LENS (loop_vinfo);=0A= - internal_fn cond_fn =3D get_conditional_internal_fn (op.code, op.typ= e);=0A= -=0A= - if (reduction_type !=3D FOLD_LEFT_REDUCTION=0A= - && !use_mask_by_cond_expr_p (op.code, cond_fn, vectype_in)=0A= - && (cond_fn =3D=3D IFN_LAST=0A= - || !direct_internal_fn_supported_p (cond_fn, vectype_in,=0A= - OPTIMIZE_FOR_SPEED)))=0A= - {=0A= - if (dump_enabled_p ())=0A= - dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location,=0A= - "can't operate on partial vectors because"=0A= - " no conditional operation is available.\n");=0A= - LOOP_VINFO_CAN_USE_PARTIAL_VECTORS_P (loop_vinfo) =3D false;=0A= - }=0A= - else if (reduction_type =3D=3D FOLD_LEFT_REDUCTION=0A= - && reduc_fn =3D=3D IFN_LAST=0A= - && !expand_vec_cond_expr_p (vectype_in,=0A= - truth_type_for (vectype_in),=0A= - SSA_NAME))=0A= - {=0A= - if (dump_enabled_p ())=0A= - dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location,=0A= - "can't operate on partial vectors because"=0A= - " no conditional operation is available.\n");=0A= - LOOP_VINFO_CAN_USE_PARTIAL_VECTORS_P (loop_vinfo) =3D false;=0A= - }=0A= - else if (reduction_type =3D=3D FOLD_LEFT_REDUCTION=0A= - && internal_fn_mask_index (reduc_fn) =3D=3D -1=0A= - && FLOAT_TYPE_P (vectype_in)=0A= - && HONOR_SIGN_DEPENDENT_ROUNDING (vectype_in))=0A= - {=0A= - if (dump_enabled_p ())=0A= - dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location,=0A= - "can't operate on partial vectors because"=0A= - " signed zeros cannot be preserved.\n");=0A= - LOOP_VINFO_CAN_USE_PARTIAL_VECTORS_P (loop_vinfo) =3D false;=0A= - }=0A= - else=0A= - {=0A= - internal_fn mask_reduc_fn=0A= - =3D get_masked_reduction_fn (reduc_fn, vectype_in);=0A= + else=0A= + vect_reduction_use_partial_vector (loop_vinfo, reduc_info, slp_node,= =0A= + op.code, op.type, vectype_in);=0A= =0A= - if (mask_reduc_fn =3D=3D IFN_MASK_LEN_FOLD_LEFT_PLUS)=0A= - vect_record_loop_len (loop_vinfo, lens, ncopies * vec_num,=0A= - vectype_in, 1);=0A= - else=0A= - vect_record_loop_mask (loop_vinfo, masks, ncopies * vec_num,=0A= - vectype_in, NULL);=0A= - }=0A= - }=0A= return true;=0A= }=0A= =0A= @@ -8440,6 +8585,7 @@ vect_transform_reduction (loop_vec_info loop_vinfo,= =0A= class loop *loop =3D LOOP_VINFO_LOOP (loop_vinfo);=0A= int i;=0A= int ncopies;=0A= + int stmt_ncopies;=0A= int vec_num;=0A= =0A= stmt_vec_info reduc_info =3D info_for_reduction (loop_vinfo, stmt_info);= =0A= @@ -8463,15 +8609,28 @@ vect_transform_reduction (loop_vec_info loop_vinfo,= =0A= gphi *reduc_def_phi =3D as_a (phi_info->stmt);=0A= int reduc_index =3D STMT_VINFO_REDUC_IDX (stmt_info);=0A= tree vectype_in =3D STMT_VINFO_REDUC_VECTYPE_IN (reduc_info);=0A= + tree stmt_vectype_in =3D STMT_VINFO_REDUC_VECTYPE_IN (stmt_info);=0A= +=0A= + /* Get input vectypes from the reduction PHI and the statement to be=0A= + transformed, these two vectypes may have different lanes when=0A= + lane-reducing operation is present. */=0A= + if (!vectype_in)=0A= + vectype_in =3D STMT_VINFO_REDUC_VECTYPE (reduc_info);=0A= +=0A= + if (!stmt_vectype_in)=0A= + stmt_vectype_in =3D STMT_VINFO_VECTYPE (stmt_info);=0A= =0A= if (slp_node)=0A= {=0A= ncopies =3D 1;=0A= + stmt_ncopies =3D 1;=0A= vec_num =3D SLP_TREE_NUMBER_OF_VEC_STMTS (slp_node);=0A= }=0A= else=0A= {=0A= ncopies =3D vect_get_num_copies (loop_vinfo, vectype_in);=0A= + stmt_ncopies =3D vect_get_num_copies (loop_vinfo, stmt_vectype_in);= =0A= + gcc_assert (stmt_ncopies >=3D 1 && stmt_ncopies <=3D ncopies);=0A= vec_num =3D 1;=0A= }=0A= =0A= @@ -8480,14 +8639,10 @@ vect_transform_reduction (loop_vec_info loop_vinfo,= =0A= =0A= vec_loop_masks *masks =3D &LOOP_VINFO_MASKS (loop_vinfo);=0A= vec_loop_lens *lens =3D &LOOP_VINFO_LENS (loop_vinfo);=0A= - bool mask_by_cond_expr =3D use_mask_by_cond_expr_p (code, cond_fn, vecty= pe_in);=0A= -=0A= + bool mask_by_cond_expr =3D use_mask_by_cond_expr_p (code, cond_fn,=0A= + stmt_vectype_in);=0A= /* Transform. */=0A= - tree new_temp =3D NULL_TREE;=0A= - auto_vec vec_oprnds0;=0A= - auto_vec vec_oprnds1;=0A= - auto_vec vec_oprnds2;=0A= - tree def0;=0A= + auto_vec vec_oprnds[3];=0A= =0A= if (dump_enabled_p ())=0A= dump_printf_loc (MSG_NOTE, vect_location, "transform reduction.\n");= =0A= @@ -8510,8 +8665,6 @@ vect_transform_reduction (loop_vec_info loop_vinfo,= =0A= =3D=3D op.ops[internal_fn_else_index ((internal_fn) code)]));=0A= }=0A= =0A= - bool masked_loop_p =3D LOOP_VINFO_FULLY_MASKED_P (loop_vinfo);=0A= -=0A= vect_reduction_type reduction_type =3D STMT_VINFO_REDUC_TYPE (reduc_info= );=0A= if (reduction_type =3D=3D FOLD_LEFT_REDUCTION)=0A= {=0A= @@ -8519,7 +8672,7 @@ vect_transform_reduction (loop_vec_info loop_vinfo,= =0A= gcc_assert (code.is_tree_code () || cond_fn_p);=0A= return vectorize_fold_left_reduction=0A= (loop_vinfo, stmt_info, gsi, vec_stmt, slp_node, reduc_def_phi,=0A= - code, reduc_fn, op.ops, op.num_ops, vectype_in,=0A= + code, reduc_fn, op.ops, op.num_ops, stmt_vectype_in,=0A= reduc_index, masks, lens);=0A= }=0A= =0A= @@ -8533,55 +8686,160 @@ vect_transform_reduction (loop_vec_info loop_vinfo= ,=0A= tree scalar_dest =3D gimple_get_lhs (stmt_info->stmt);=0A= tree vec_dest =3D vect_create_destination_var (scalar_dest, vectype_out)= ;=0A= =0A= - /* Get NCOPIES vector definitions for all operands except the reduction= =0A= - definition. */=0A= - if (!cond_fn_p)=0A= + gcc_assert (reduc_index < 3);=0A= +=0A= + if (slp_node)=0A= {=0A= - vect_get_vec_defs (loop_vinfo, stmt_info, slp_node, ncopies,=0A= - single_defuse_cycle && reduc_index =3D=3D 0=0A= - ? NULL_TREE : op.ops[0], &vec_oprnds0,=0A= - single_defuse_cycle && reduc_index =3D=3D 1=0A= - ? NULL_TREE : op.ops[1], &vec_oprnds1,=0A= - op.num_ops =3D=3D 3=0A= - && !(single_defuse_cycle && reduc_index =3D=3D 2)=0A= - ? op.ops[2] : NULL_TREE, &vec_oprnds2);=0A= + gcc_assert (!single_defuse_cycle && op.num_ops <=3D 3);=0A= +=0A= + for (i =3D 0; i < (int) op.num_ops; i++)=0A= + vect_get_slp_defs (SLP_TREE_CHILDREN (slp_node)[i], &vec_oprnds[i]);=0A= }=0A= else=0A= {=0A= - /* For a conditional operation pass the truth type as mask=0A= - vectype. */=0A= - gcc_assert (single_defuse_cycle=0A= - && (reduc_index =3D=3D 1 || reduc_index =3D=3D 2));=0A= - vect_get_vec_defs (loop_vinfo, stmt_info, slp_node, ncopies,=0A= - op.ops[0], truth_type_for (vectype_in), &vec_oprnds0,=0A= - reduc_index =3D=3D 1 ? NULL_TREE : op.ops[1],=0A= - NULL_TREE, &vec_oprnds1,=0A= - reduc_index =3D=3D 2 ? NULL_TREE : op.ops[2],=0A= - NULL_TREE, &vec_oprnds2);=0A= - }=0A= + int result_pos =3D 0;=0A= +=0A= + /* The input vectype of the reduction PHI determines copies of=0A= + vectorized def-use cycles, which might be more than effective copies=0A= + of vectorized lane-reducing reduction statements. This could be=0A= + complemented by generating extra trivial pass-through copies. For=0A= + example:=0A= +=0A= + int sum =3D 0;=0A= + for (i)=0A= + {=0A= + sum +=3D d0[i] * d1[i]; // dot-prod =0A= + sum +=3D abs(s0[i] - s1[i]); // sad =0A= + sum +=3D n[i]; // normal =0A= + }=0A= +=0A= + The vector size is 128-bit=1B$B!$=1B(Bvectorization factor is 16. Reduc= tion=0A= + statements would be transformed as:=0A= +=0A= + vector<4> int sum_v0 =3D { 0, 0, 0, 0 };=0A= + vector<4> int sum_v1 =3D { 0, 0, 0, 0 };=0A= + vector<4> int sum_v2 =3D { 0, 0, 0, 0 };=0A= + vector<4> int sum_v3 =3D { 0, 0, 0, 0 };=0A= +=0A= + for (i / 16)=0A= + {=0A= + sum_v0 =3D DOT_PROD (d0_v0[i: 0 ~ 15], d1_v0[i: 0 ~ 15], sum_v0);= =0A= + sum_v1 =3D sum_v1; // copy=0A= + sum_v2 =3D sum_v2; // copy=0A= + sum_v3 =3D sum_v3; // copy=0A= +=0A= + sum_v0 =3D sum_v0; // copy=0A= + sum_v1 =3D SAD (s0_v1[i: 0 ~ 7 ], s1_v1[i: 0 ~ 7 ], sum_v1);=0A= + sum_v2 =3D SAD (s0_v2[i: 8 ~ 15], s1_v2[i: 8 ~ 15], sum_v2);=0A= + sum_v3 =3D sum_v3; // copy=0A= +=0A= + sum_v0 +=3D n_v0[i: 0 ~ 3 ];=0A= + sum_v1 +=3D n_v1[i: 4 ~ 7 ];=0A= + sum_v2 +=3D n_v2[i: 8 ~ 11];=0A= + sum_v3 +=3D n_v3[i: 12 ~ 15];=0A= + }=0A= +=0A= + Moreover, for a higher instruction parallelism in final vectorized=0A= + loop, it is considered to make those effective vectorized=0A= + lane-reducing statements be distributed evenly among all def-use=0A= + cycles. In the above example, SADs are generated into other cycles=0A= + rather than that of DOT_PROD. */=0A= +=0A= + if (stmt_ncopies < ncopies)=0A= + {=0A= + gcc_assert (code =3D=3D DOT_PROD_EXPR || code =3D=3D WIDEN_SUM_EXPR=0A= + || code =3D=3D SAD_EXPR);=0A= + result_pos =3D reduc_info->reduc_result_pos;=0A= + reduc_info->reduc_result_pos =3D (result_pos + stmt_ncopies) % ncopies;= =0A= + gcc_assert (result_pos >=3D 0 && result_pos < ncopies);=0A= + }=0A= +=0A= + for (i =3D 0; i < MIN (3, (int) op.num_ops); i++)=0A= + {=0A= + tree vectype =3D NULL_TREE;=0A= + int used_ncopies =3D ncopies;=0A= +=0A= + if (cond_fn_p && i =3D=3D 0)=0A= + {=0A= + /* For a conditional operation pass the truth type as mask=0A= + vectype. */=0A= + gcc_assert (single_defuse_cycle && reduc_index > 0);=0A= + vectype =3D truth_type_for (vectype_in);=0A= + }=0A= =0A= - /* For single def-use cycles get one copy of the vectorized reduction=0A= - definition. */=0A= - if (single_defuse_cycle)=0A= - {=0A= - gcc_assert (!slp_node);=0A= - vect_get_vec_defs_for_operand (loop_vinfo, stmt_info, 1,=0A= - op.ops[reduc_index],=0A= - reduc_index =3D=3D 0 ? &vec_oprnds0=0A= - : (reduc_index =3D=3D 1 ? &vec_oprnds1=0A= - : &vec_oprnds2));=0A= + if (i !=3D reduc_index)=0A= + {=0A= + /* For non-reduction operand, deduce effictive copies that are=0A= + involved in vectorized def-use cycles based on the input=0A= + vectype of the reduction statement. */=0A= + used_ncopies =3D stmt_ncopies;=0A= + }=0A= + else if (single_defuse_cycle)=0A= + {=0A= + /* For single def-use cycles get one copy of the vectorized=0A= + reduction definition. */=0A= + used_ncopies =3D 1;=0A= + }=0A= +=0A= + vect_get_vec_defs_for_operand (loop_vinfo, stmt_info, used_ncopies,=0A= + op.ops[i], &vec_oprnds[i], vectype);=0A= +=0A= + if (used_ncopies < ncopies)=0A= + {=0A= + vec_oprnds[i].safe_grow_cleared (ncopies);=0A= +=0A= + /* Find suitable def-use cycles to generate vectorized=0A= + statements into, and reorder operands based on the=0A= + selection. */=0A= + if (i !=3D reduc_index && result_pos)=0A= + {=0A= + int count =3D ncopies - used_ncopies;=0A= + int start =3D result_pos - count;=0A= +=0A= + if (start < 0)=0A= + {=0A= + count =3D result_pos;=0A= + start =3D 0;=0A= + }=0A= +=0A= + for (int j =3D used_ncopies - 1; j >=3D start; j--)=0A= + {=0A= + std::swap (vec_oprnds[i][j], vec_oprnds[i][j + count]);=0A= + gcc_assert (!vec_oprnds[i][j]);=0A= + }=0A= + }=0A= + }=0A= + }=0A= }=0A= =0A= - bool emulated_mixed_dot_prod=0A= - =3D vect_is_emulated_mixed_dot_prod (loop_vinfo, stmt_info);=0A= - FOR_EACH_VEC_ELT (vec_oprnds0, i, def0)=0A= + bool masked_loop_p =3D LOOP_VINFO_FULLY_MASKED_P (loop_vinfo);=0A= + bool emulated_mixed_dot_prod =3D vect_is_emulated_mixed_dot_prod (stmt_i= nfo);=0A= + tree def0;=0A= +=0A= + FOR_EACH_VEC_ELT (vec_oprnds[0], i, def0)=0A= {=0A= gimple *new_stmt;=0A= - tree vop[3] =3D { def0, vec_oprnds1[i], NULL_TREE };=0A= - if (masked_loop_p && !mask_by_cond_expr)=0A= + tree new_temp =3D NULL_TREE;=0A= + tree vop[3] =3D { def0, vec_oprnds[1][i], NULL_TREE };=0A= +=0A= + if (!vop[0] || !vop[1])=0A= + {=0A= + tree reduc_vop =3D vec_oprnds[reduc_index][i];=0A= +=0A= + /* Insert trivial copy if no need to generate vectorized=0A= + statement. */=0A= + gcc_assert (reduc_vop && stmt_ncopies < ncopies);=0A= +=0A= + new_stmt =3D gimple_build_assign (vec_dest, reduc_vop);=0A= + new_temp =3D make_ssa_name (vec_dest, new_stmt);=0A= + gimple_set_lhs (new_stmt, new_temp);=0A= + vect_finish_stmt_generation (loop_vinfo, stmt_info, new_stmt, gsi);=0A= + }=0A= + else if (masked_loop_p && !mask_by_cond_expr)=0A= {=0A= - /* No conditional ifns have been defined for dot-product yet. */=0A= - gcc_assert (code !=3D DOT_PROD_EXPR);=0A= + /* No conditional ifns have been defined for dot-product and sad=0A= + yet. */=0A= + gcc_assert (code !=3D DOT_PROD_EXPR && code !=3D SAD_EXPR);=0A= =0A= /* Make sure that the reduction accumulator is vop[0]. */=0A= if (reduc_index =3D=3D 1)=0A= @@ -8590,7 +8848,8 @@ vect_transform_reduction (loop_vec_info loop_vinfo,= =0A= std::swap (vop[0], vop[1]);=0A= }=0A= tree mask =3D vect_get_loop_mask (loop_vinfo, gsi, masks,=0A= - vec_num * ncopies, vectype_in, i);=0A= + vec_num * stmt_ncopies,=0A= + stmt_vectype_in, i);=0A= gcall *call =3D gimple_build_call_internal (cond_fn, 4, mask,=0A= vop[0], vop[1], vop[0]);=0A= new_temp =3D make_ssa_name (vec_dest, call);=0A= @@ -8602,12 +8861,13 @@ vect_transform_reduction (loop_vec_info loop_vinfo,= =0A= else=0A= {=0A= if (op.num_ops >=3D 3)=0A= - vop[2] =3D vec_oprnds2[i];=0A= + vop[2] =3D vec_oprnds[2][i];=0A= =0A= if (masked_loop_p && mask_by_cond_expr)=0A= {=0A= tree mask =3D vect_get_loop_mask (loop_vinfo, gsi, masks,=0A= - vec_num * ncopies, vectype_in, i);=0A= + vec_num * stmt_ncopies,=0A= + stmt_vectype_in, i);=0A= build_vect_cond_expr (code, vop, mask, gsi);=0A= }=0A= =0A= @@ -8634,16 +8894,8 @@ vect_transform_reduction (loop_vec_info loop_vinfo,= =0A= =0A= if (slp_node)=0A= slp_node->push_vec_def (new_stmt);=0A= - else if (single_defuse_cycle=0A= - && i < ncopies - 1)=0A= - {=0A= - if (reduc_index =3D=3D 0)=0A= - vec_oprnds0.safe_push (gimple_get_lhs (new_stmt));=0A= - else if (reduc_index =3D=3D 1)=0A= - vec_oprnds1.safe_push (gimple_get_lhs (new_stmt));=0A= - else if (reduc_index =3D=3D 2)=0A= - vec_oprnds2.safe_push (gimple_get_lhs (new_stmt));=0A= - }=0A= + else if (single_defuse_cycle && i < ncopies - 1)=0A= + vec_oprnds[reduc_index][i + 1] =3D gimple_get_lhs (new_stmt);=0A= else=0A= STMT_VINFO_VEC_STMTS (stmt_info).safe_push (new_stmt);=0A= }=0A= diff --git a/gcc/tree-vect-stmts.cc b/gcc/tree-vect-stmts.cc=0A= index f8d8636b139..15331ca87f2 100644=0A= --- a/gcc/tree-vect-stmts.cc=0A= +++ b/gcc/tree-vect-stmts.cc=0A= @@ -12093,11 +12093,20 @@ vectorizable_condition (vec_info *vinfo,=0A= vect_reduction_type reduction_type =3D TREE_CODE_REDUCTION;=0A= bool for_reduction=0A= =3D STMT_VINFO_REDUC_DEF (vect_orig_stmt (stmt_info)) !=3D NULL;=0A= + if (for_reduction)=0A= + {=0A= + reduc_info =3D info_for_reduction (vinfo, stmt_info);=0A= + if (STMT_VINFO_REDUC_DEF (reduc_info) !=3D vect_orig_stmt (stmt_info= ))=0A= + {=0A= + for_reduction =3D false;=0A= + reduc_info =3D NULL;=0A= + }=0A= + }=0A= +=0A= if (for_reduction)=0A= {=0A= if (slp_node)=0A= return false;=0A= - reduc_info =3D info_for_reduction (vinfo, stmt_info);=0A= reduction_type =3D STMT_VINFO_REDUC_TYPE (reduc_info);=0A= reduc_index =3D STMT_VINFO_REDUC_IDX (stmt_info);=0A= gcc_assert (reduction_type !=3D EXTRACT_LAST_REDUCTION=0A= @@ -13273,6 +13282,8 @@ vect_analyze_stmt (vec_info *vinfo,=0A= NULL, NULL, node, cost_vec)=0A= || vectorizable_load (vinfo, stmt_info, NULL, NULL, node, cost_vec)=0A= || vectorizable_store (vinfo, stmt_info, NULL, NULL, node, cost_vec)=0A= + || vectorizable_lane_reducing (as_a (vinfo),=0A= + stmt_info, node, cost_vec)=0A= || vectorizable_reduction (as_a (vinfo), stmt_info,=0A= node, node_instance, cost_vec)=0A= || vectorizable_induction (as_a (vinfo), stmt_info,=0A= diff --git a/gcc/tree-vectorizer.h b/gcc/tree-vectorizer.h=0A= index db44d730b70..a923e1cd657 100644=0A= --- a/gcc/tree-vectorizer.h=0A= +++ b/gcc/tree-vectorizer.h=0A= @@ -1399,6 +1399,12 @@ public:=0A= /* The vector type for performing the actual reduction. */=0A= tree reduc_vectype;=0A= =0A= + /* For loop reduction with multiple vectorized results (ncopies > 1), a= =0A= + lane-reducing operation participating in it may not use all of those= =0A= + results, this field specifies result index starting from which any=0A= + following land-reducing operation would be assigned to. */=0A= + int reduc_result_pos;=0A= +=0A= /* If IS_REDUC_INFO is true and if the vector code is performing=0A= N scalar reductions in parallel, this variable gives the initial=0A= scalar values of those N reductions. */=0A= @@ -2430,6 +2436,8 @@ extern loop_vec_info vect_create_loop_vinfo (class lo= op *, vec_info_shared *,=0A= extern bool vectorizable_live_operation (vec_info *, stmt_vec_info,=0A= slp_tree, slp_instance, int,=0A= bool, stmt_vector_for_cost *);=0A= +extern bool vectorizable_lane_reducing (loop_vec_info, stmt_vec_info,=0A= + slp_tree, stmt_vector_for_cost *);=0A= extern bool vectorizable_reduction (loop_vec_info, stmt_vec_info,=0A= slp_tree, slp_instance,=0A= stmt_vector_for_cost *);=0A= -- =0A= 2.17.1= --_002_LV2PR01MB783908343529A6204C432BC2F7012LV2PR01MB7839prod_ Content-Type: text/x-patch; name="0001-vect-Support-multiple-lane-reducing-operations-for-l.patch" Content-Description: 0001-vect-Support-multiple-lane-reducing-operations-for-l.patch Content-Disposition: attachment; filename="0001-vect-Support-multiple-lane-reducing-operations-for-l.patch"; size=51159; creation-date="Sun, 07 Apr 2024 06:58:44 GMT"; modification-date="Sun, 07 Apr 2024 06:58:44 GMT" Content-Transfer-Encoding: base64 RnJvbSBlY2RlNjIxMGZmNDgzYWQ4OTlhMmVlYmE5MWFhMWI2MjNjNDkxNzNhIE1vbiBTZXAgMTcg MDA6MDA6MDAgMjAwMQpGcm9tOiBGZW5nIFh1ZSA8Znh1ZUBvcy5hbXBlcmVjb21wdXRpbmcuY29t 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