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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5751.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4f9c9c37-17b3-4ac3-7111-08dc2d6025af X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Feb 2024 13:23:35.1776 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 1b0VduFzWvyHGEXz6f0dVYYmmbrnTkN3b/NMaDoMUybxNZIDUh1I3aZFWhSj5OOxYhtYsJHqHPeWalGjeJHwNQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7225 X-Spam-Status: No, score=-3.8 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: [Public] Hi, >>I assume the znver5 costs are smae as znver4 so far? Costing table updated for below entries. + {COSTS_N_INSNS (10), /* cost of a divide/mod for QI. */ + COSTS_N_INSNS (11), /* HI. */ + COSTS_N_INSNS (16), /* DI. */ + COSTS_N_INSNS (16)}, /* = other. */ + COSTS_N_INSNS (10), /* cost of DIVSS instructio= n. */ + COSTS_N_INSNS (14), /* cost of SQRTSS instructi= on. */ + COSTS_N_INSNS (20), /* cost of SQRTSD instructi= on. */ >> we can just change znver4.md to also work for znver5? We will combine znver4 and znver5 scheduler descriptions into one Thanks and Regards Karthiban -----Original Message----- From: Jan Hubicka Sent: Monday, February 12, 2024 9:30 PM To: Anbazhagan, Karthiban Cc: gcc-patches@gcc.gnu.org; Kumar, Venkataramanan ; Joshi, Tejas Sanjay ; Nagarajan, Muthu k= umar raj ; Gopalasubramanian, Ganesh Subject: Re: [PATCH] [X86_64]: Enable support for next generation AMD Zen5 = CPU with znver5 scheduler Model Caution: This message originated from an External Source. Use proper cautio= n when opening attachments, clicking links, or responding. Hi, > gcc/ChangeLog: > * common/config/i386/cpuinfo.h (get_amd_cpu): Recognize znver5. > * common/config/i386/i386-common.cc (processor_names): Add znver5= . > (processor_alias_table): Likewise. > * common/config/i386/i386-cpuinfo.h (processor_types): Add new ze= n > family. > (processor_subtypes): Add znver5. > * config.gcc (x86_64-*-* |...): Likewise. > * config/i386/driver-i386.cc (host_detect_local_cpu): Let > march=3Dnative detect znver5 cpu's. > * config/i386/i386-c.cc (ix86_target_macros_internal): Add znver5= . > * config/i386/i386-options.cc (m_ZNVER5): New definition > (processor_cost_table): Add znver5. > * config/i386/i386.cc (ix86_reassociation_width): Likewise. > * config/i386/i386.h (processor_type): Add PROCESSOR_ZNVER5 > (PTA_ZNVER5): New definition. > * config/i386/i386.md (define_attr "cpu"): Add znver5. > (Scheduling descriptions) Add znver5.md. > * config/i386/x86-tune-costs.h (znver5_cost): New definition. > * config/i386/x86-tune-sched.cc (ix86_issue_rate): Add znver5. > (ix86_adjust_cost): Likewise. > * config/i386/x86-tune.def (avx512_move_by_pieces): Add m_ZNVER5. > (avx512_store_by_pieces): Add m_ZNVER5. > * doc/extend.texi: Add znver5. > * doc/invoke.texi: Likewise. > * config/i386/znver5.md: New. > > gcc/testsuite/ChangeLog: > * g++.target/i386/mv29.C: Handle znver5 arch. > * gcc.target/i386/funcspec-56.inc:Likewise. > +/* This table currently replicates znver4_cost table. */ struct > +processor_costs znver5_cost =3D { I assume the znver5 costs are smae as znver4 so far? > +;; AMD znver5 Scheduling > +;; Modeling automatons for zen decoders, integer execution pipes, ;; > +AGU pipes, branch, floating point execution and fp store units. > +(define_automaton "znver5, znver5_ieu, znver5_idiv, znver5_fdiv, > +znver5_agu, znver5_fpu, znver5_fp_store") > + > +;; Decoders unit has 4 decoders and all of them can decode fast path > +;; and vector type instructions. > +(define_cpu_unit "znver5-decode0" "znver5") (define_cpu_unit > +"znver5-decode1" "znver5") (define_cpu_unit "znver5-decode2" > +"znver5") (define_cpu_unit "znver5-decode3" "znver5") Duplicating znver4 description to znver5 before scheduler description is tu= ned is basically just leads to increasing compiler binary size (scheduler m= odels are quite large). Depending on changes between generations, I think we should try to share CP= U unit DFAs where it makes sense (i.e. shared DFA is smaller than two DFAs)= . So perhaps unit scheduler is tuned, we can just change znver4.md to also= work for znver5? Honza