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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MW5PR11MB5908.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: cca9a65a-9fc9-4ec5-cdd5-08dbe327580e X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Nov 2023 02:30:32.3443 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: dcyHo14mYxkypXduhwohz30ZMfCCEyqCWbqDXzHdED4JrPtHrIuvmQ9EzFTiVHrErLWn7yOLq+rzlMUegtKS1Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR11MB7617 X-OriginatorOrg: intel.com X-Spam-Status: No, score=-6.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,KAM_SHORT,RCVD_IN_DNSWL_LOW,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Thanks Richard S and Jeff for comments. > Did you want to use known_le so that you'd pick up the case when the two= =20 > modes are the same size? Or was known_lt the test you really wanted=20 > (and if so, why). Take known_lt in v2 due to consideration that leave the equal go to origina= l code path. Just have a try for known_le and got sorts of ICE when test, I bet it may b= e related to the latent bug as Richard S mentioned. > instead. Alternatively, we could remove the is_constant condition > and fix PR87815 in a different way, e.g. by protecting the > smallest_int_mode_for_size with a tighter condition. That might > allow a similar DSE optimisation to this patch for nonzero offsets, > thanks to: Thus, looks like we should fix the PR87815 from the way suggested by Richar= d S, before we take known_le for vector here. I will have a try soon and keep you posted. Pan -----Original Message----- From: Richard Sandiford =20 Sent: Saturday, November 11, 2023 11:23 PM To: Jeff Law Cc: Li, Pan2 ; gcc-patches@gcc.gnu.org; juzhe.zhong@riva= i.ai; Wang, Yanzhang ; kito.cheng@gmail.com; richa= rd.guenther@gmail.com Subject: Re: [PATCH v2] DSE: Allow vector type for get_stored_val when read= < store Jeff Law writes: > On 11/8/23 23:08, pan2.li@intel.com wrote: >> From: Pan Li >>=20 >> Update in v2: >> * Move vector type support to get_stored_val. >>=20 >> Original log: >>=20 >> This patch would like to allow the vector mode in the >> get_stored_val in the DSE. It is valid for the read >> rtx if and only if the read bitsize is less than the >> stored bitsize. >>=20 >> Given below example code with >> --param=3Driscv-autovec-preference=3Dfixed-vlmax. >>=20 >> vuint8m1_t test () { >> uint8_t arr[32] =3D { >> 1, 2, 7, 1, 3, 4, 5, 3, 1, 0, 1, 2, 4, 4, 9, 9, >> 1, 2, 7, 1, 3, 4, 5, 3, 1, 0, 1, 2, 4, 4, 9, 9, >> }; >>=20 >> return __riscv_vle8_v_u8m1(arr, 32); >> } >>=20 >> Before this patch: >> test: >> lui a5,%hi(.LANCHOR0) >> addi sp,sp,-32 >> addi a5,a5,%lo(.LANCHOR0) >> li a3,32 >> vl2re64.v v2,0(a5) >> vsetvli zero,a3,e8,m1,ta,ma >> vs2r.v v2,0(sp) <=3D=3D Unnecessary store to stack >> vle8.v v1,0(sp) <=3D=3D Ditto >> vs1r.v v1,0(a0) >> addi sp,sp,32 >> jr ra >>=20 >> After this patch: >> test: >> lui a5,%hi(.LANCHOR0) >> addi a5,a5,%lo(.LANCHOR0) >> li a4,32 >> addi sp,sp,-32 >> vsetvli zero,a4,e8,m1,ta,ma >> vle8.v v1,0(a5) >> vs1r.v v1,0(a0) >> addi sp,sp,32 >> jr ra >>=20 >> Below tests are passed within this patch: >>=20 >> * The x86 bootstrap and regression test. >> * The aarch64 regression test. >> * The risc-v regression test. >>=20 >> PR target/111720 >>=20 >> gcc/ChangeLog: >>=20 >> * dse.cc (get_stored_val): Allow vector mode if the read >> bitsize is less than stored bitsize. >>=20 >> gcc/testsuite/ChangeLog: >>=20 >> * gcc.target/riscv/rvv/base/pr111720-0.c: New test. >> * gcc.target/riscv/rvv/base/pr111720-1.c: New test. >> * gcc.target/riscv/rvv/base/pr111720-10.c: New test. >> * gcc.target/riscv/rvv/base/pr111720-2.c: New test. >> * gcc.target/riscv/rvv/base/pr111720-3.c: New test. >> * gcc.target/riscv/rvv/base/pr111720-4.c: New test. >> * gcc.target/riscv/rvv/base/pr111720-5.c: New test. >> * gcc.target/riscv/rvv/base/pr111720-6.c: New test. >> * gcc.target/riscv/rvv/base/pr111720-7.c: New test. >> * gcc.target/riscv/rvv/base/pr111720-8.c: New test. >> * gcc.target/riscv/rvv/base/pr111720-9.c: New test. > We're always getting the lowpart here AFAICT and it appears that all the= =20 > right thing should happen if gen_lowpart_common fails (it returns NULL,=20 > which bubbles up and is the right return value from get_stored_val if it= =20 > can't be optimized). Yeah, we should always be operating on the lowpart, but it looks like there's a latent bug. This check: if (gap.is_constant () && maybe_ne (gap, 0)) { ... } else ... means that we ignore the gap if it's a nonzero runtime value. I guess it should be: if (maybe_ne (gap, 0)) { if (!gap.is_constant ()) return NULL_RTX; ... } instead. Alternatively, we could remove the is_constant condition and fix PR87815 in a different way, e.g. by protecting the smallest_int_mode_for_size with a tighter condition. That might allow a similar DSE optimisation to this patch for nonzero offsets, thanks to: if (multiple_p (shift, GET_MODE_BITSIZE (new_mode)) && known_le (GET_MODE_SIZE (new_mode), GET_MODE_SIZE (store_mode))) { /* Try to implement the shift using a subreg. */ ... > Did you want to use known_le so that you'd pick up the case when the two= =20 > modes are the same size? Or was known_lt the test you really wanted=20 > (and if so, why). Agree it should be known_le FWIW. Thanks, Richard