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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MW5PR11MB5908.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4f90769a-c3d3-4b3e-b304-08db4f9b04c2 X-MS-Exchange-CrossTenant-originalarrivaltime: 08 May 2023 08:05:42.1157 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: y5NMxL6ivba1HEpabU1ZihQcw2rvUJ5TMq13JXyPztTnF/K/i6YtntTIyaCd7Ct7Tlc7rVjPGLNoOpkG+ZHuPQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR11MB4990 X-OriginatorOrg: intel.com X-Spam-Status: No, score=-5.9 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: After the bits patch like below. rtx_def code 16 =3D> 8 bits. rtx_def mode 8 =3D> 16 bits. tree_base code unchanged. The structure layout of both the rtx_def and tree_base will be something si= milar as below. As I understand, the lower 8-bits of tree_base will be insp= ected when 'dv' is a tree for the rtx conversion. tree_base rtx_def code: 16 code: 8 side_effects_flag: 1 mode: 16 constant_flag: 1 addressable_flag: 1 volatile_flag: 1 readonly_flag: 1 asm_written_flag: 1 nowarning_flag: 1 visited: 1 used_flag: 1 nothrow_flag: 1 static_flag: 1 public_flag: 1 private_flag: 1 protected_flag: 1 deprecated_flag: 1 default_def_flag: 1 I have a try a similar approach (as below) as you mentioned, aka shrink tre= e_code as 1:1 overlap to rtx_code. And completed one memory allocated bytes= test in another email. rtx_def code 16 =3D> 12 bits. rtx_def mode 8 =3D> 12 bits. tree_base code 16 =3D> 12 bits. Pan -----Original Message----- From: Richard Biener =20 Sent: Monday, May 8, 2023 3:38 PM To: Li, Pan2 Cc: Jeff Law ; Kito Cheng ; ju= zhe.zhong@rivai.ai; richard.sandiford ; gcc-patc= hes ; palmer ; jakub Subject: RE: [PATCH] machine_mode type size: Extend enum size from 8-bit to= 16-bit On Mon, 8 May 2023, Li, Pan2 wrote: > return !dv || (int) GET_CODE ((rtx) dv) !=3D (int) VALUE; } is able to=20 > fix this ICE after mode bits change. Can you check which bits this will inspect when 'dv' is a tree after your p= atch? VALUE is 1 and would map to IDENTIFIER_NODE on the tree side when th= ere was a 1:1 overlap. I think for all cases but struct loc_exp_dep we could find a bit to record = wheter we deal with a VALUE or a decl, but for loc_exp_dep it's going to be= difficult (unless we start to take bits from pointer representations). That said, I agree with Jeff that the code is ugly, but a simplistic conver= sion isn't what we want. An alternative "solution" might be to also shrink tree_code when we shrink = rtx_code and keep the 1:1 overlap. Richard. > I will re-trigger the memory allocate bytes test with below changes=20 > for X86. >=20 > rtx_def code 16 =3D> 8 bits. > rtx_def mode 8 =3D> 16 bits. > tree_base code unchanged. >=20 > Pan >=20 > -----Original Message----- > From: Li, Pan2 > Sent: Monday, May 8, 2023 2:42 PM > To: Richard Biener ; Jeff Law=20 > > Cc: Kito Cheng ; juzhe.zhong@rivai.ai;=20 > richard.sandiford ; gcc-patches=20 > ; palmer ; jakub=20 > > Subject: RE: [PATCH] machine_mode type size: Extend enum size from=20 > 8-bit to 16-bit >=20 > Oops. Actually I am patching a version as you mentioned like storage allo= cation. Thank you Richard, will try your suggestion and keep you posted. >=20 > Pan >=20 > -----Original Message----- > From: Richard Biener > Sent: Monday, May 8, 2023 2:30 PM > To: Jeff Law > Cc: Li, Pan2 ; Kito Cheng ;=20 > juzhe.zhong@rivai.ai; richard.sandiford ;=20 > gcc-patches ; palmer ;=20 > jakub > Subject: Re: [PATCH] machine_mode type size: Extend enum size from=20 > 8-bit to 16-bit >=20 > On Sun, 7 May 2023, Jeff Law wrote: >=20 > >=20 > >=20 > > On 5/6/23 19:55, Li, Pan2 wrote: > > > It looks like we cannot simply swap the code and mode in rtx_def,=20 > > > the code may have to be the same bits as the tree_code in tree_base. > > > Or we will meet ICE like below. > > >=20 > > > rtx_def code 16 =3D> 8 bits. > > > rtx_def mode 8 =3D> 16 bits. > > >=20 > > > static inline decl_or_value > > > dv_from_value (rtx value) > > > { > > > decl_or_value dv; > > > dv =3D value; > > > gcc_checking_assert (dv_is_value_p (dv)); <=3D ICE > > > return dv; > > Ugh. We really just need to fix this code. It assumes particular=20 > > structure layouts and that's just wrong/dumb. >=20 > Well, it's a neat trick ... we just need to adjust it to >=20 > static inline bool > dv_is_decl_p (decl_or_value dv) > { > return !dv || (int) GET_CODE ((rtx) dv) !=3D (int) VALUE; } >=20 > I think (and hope for the 'decl' case the bits inspected are never 'VALUE= '). Of course the above stinks from a TBAA perspective ... >=20 > Any "real" fix would require allocating storage for a discriminator and t= hus hurt the resource constrained var-tracking a lot. >=20 > Richard. >=20 -- Richard Biener SUSE Software Solutions Germany GmbH, Frankenstrasse 146, 90461 Nuernberg, = Germany; GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman; HRB= 36809 (AG Nuernberg)