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Passed the rv64gcv fully regression test with isl build. Pan -----Original Message----- From: Li, Pan2 =20 Sent: Wednesday, April 24, 2024 8:59 PM To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai; kito.cheng@gmail.com; rdapp.gcc@gmail.com; Li, Pa= n2 Subject: [PATCH v1] Revert "RISC-V: Support highpart register overlap for v= wcvt" From: Pan Li This reverts commit bdad036da32f72b84a96070518e7d75c21706dc2. --- gcc/config/riscv/constraints.md | 23 ---- gcc/config/riscv/riscv.md | 24 ---- gcc/config/riscv/vector-crypto.md | 21 ++-- gcc/config/riscv/vector.md | 19 ++-- .../gcc.target/riscv/rvv/base/pr112431-1.c | 104 ------------------ .../gcc.target/riscv/rvv/base/pr112431-2.c | 68 ------------ .../gcc.target/riscv/rvv/base/pr112431-3.c | 51 --------- .../gcc.target/riscv/rvv/base/pr112431-39.c | 2 +- .../gcc.target/riscv/rvv/base/pr112431-40.c | 2 +- .../gcc.target/riscv/rvv/base/pr112431-41.c | 2 +- 10 files changed, 22 insertions(+), 294 deletions(-) delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-1.c delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-2.c delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-3.c diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints= .md index e37c6936bfa..a590df545d7 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -159,29 +159,6 @@ (define_register_constraint "vd" "TARGET_VECTOR ? VD_R= EGS : NO_REGS" (define_register_constraint "vm" "TARGET_VECTOR ? VM_REGS : NO_REGS" "A vector mask register (if available).") =20 -;; These following constraints are used by RVV instructions with dest EEW = > src EEW. -;; RISC-V 'V' Spec 5.2. Vector Operands: -;; The destination EEW is greater than the source EEW, the source EMUL is = at least 1, -;; and the overlap is in the highest-numbered part of the destination regi= ster group. -;; (e.g., when LMUL=3D8, vzext.vf4 v0, v6 is legal, but a source of v0, v2= , or v4 is not). -(define_register_constraint "W21" "TARGET_VECTOR ? V_REGS : NO_REGS" - "A vector register has register number % 2 =3D=3D 1." "regno % 2 =3D=3D = 1") - -(define_register_constraint "W42" "TARGET_VECTOR ? V_REGS : NO_REGS" - "A vector register has register number % 4 =3D=3D 2." "regno % 4 =3D=3D = 2") - -(define_register_constraint "W84" "TARGET_VECTOR ? V_REGS : NO_REGS" - "A vector register has register number % 8 =3D=3D 4." "regno % 8 =3D=3D = 4") - -(define_register_constraint "W41" "TARGET_VECTOR ? V_REGS : NO_REGS" - "A vector register has register number % 4 =3D=3D 1." "regno % 4 =3D=3D = 1") - -(define_register_constraint "W81" "TARGET_VECTOR ? V_REGS : NO_REGS" - "A vector register has register number % 8 =3D=3D 1." "regno % 8 =3D=3D = 1") - -(define_register_constraint "W82" "TARGET_VECTOR ? V_REGS : NO_REGS" - "A vector register has register number % 8 =3D=3D 2." "regno % 8 =3D=3D = 2") - ;; This constraint is used to match instruction "csrr %0, vlenb" which is = generated in "mov". ;; VLENB is a run-time constant which represent the vector register length= in bytes. ;; BYTES_PER_RISCV_VECTOR represent runtime invariant of vector register l= ength in bytes. diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 1693d4008c6..455715ab2f7 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -538,27 +538,6 @@ (define_attr "fp_vector_disabled" "no,yes" ] (const_string "no"))) =20 -(define_attr "vconstraint" "no,W21,W42,W84,W41,W81,W82" - (const_string "no")) - -(define_attr "vconstraint_enabled" "no,yes" - (cond [(eq_attr "vconstraint" "no") - (const_string "yes") - - (and (eq_attr "vconstraint" "W21") - (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0])) != =3D 2")) - (const_string "no") - - (and (eq_attr "vconstraint" "W42,W41") - (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0])) != =3D 4")) - (const_string "no") - - (and (eq_attr "vconstraint" "W84,W81,W82") - (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0])) != =3D 8")) - (const_string "no") - ] - (const_string "yes"))) - ;; This attribute marks the alternatives not matching the constraints ;; described in spec as disabled. (define_attr "spec_restriction" "none,thv,rvv" @@ -587,9 +566,6 @@ (define_attr "enabled" "no,yes" (eq_attr "fp_vector_disabled" "yes") (const_string "no") =20 - (eq_attr "vconstraint_enabled" "no") - (const_string "no") - (eq_attr "spec_restriction_disabled" "yes") (const_string "no") ] diff --git a/gcc/config/riscv/vector-crypto.md b/gcc/config/riscv/vector-cr= ypto.md index 23dc549e5b8..8a4888a7653 100755 --- a/gcc/config/riscv/vector-crypto.md +++ b/gcc/config/riscv/vector-crypto.md @@ -303,26 +303,25 @@ (define_insn "@pred_vwsll" (set_attr "mode" "")]) =20 (define_insn "@pred_vwsll_scalar" - [(set (match_operand:VWEXTI 0 "register_operand" "=3Dvd, vr, vd, vr, = vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr") + [(set (match_operand:VWEXTI 0 "register_operand" "=3Dvr, = vr") (if_then_else:VWEXTI (unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm= ,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK= , rK, rK, rK, rK, rK, rK, rK, rK, rK") - (match_operand 6 "const_int_operand" " i, i, i, i, i= , i, i, i, i, i, i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i, i= , i, i, i, i, i, i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i, i= , i, i, i, i, i, i, i, i, i") + [(match_operand: 1 "vector_mask_operand" "vmWc1, vm= Wc1") + (match_operand 5 "vector_length_operand" " rK, = rK") + (match_operand 6 "const_int_operand" " i, = i") + (match_operand 7 "const_int_operand" " i, = i") + (match_operand 8 "const_int_operand" " i, = i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (ashift:VWEXTI (zero_extend:VWEXTI - (match_operand: 3 "register_operand" "W21,W21,= W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr")) - (match_operand: 4 "pmode_reg_or_uimm5_operand" " rK, rK,= rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")) - (match_operand:VWEXTI 2 "vector_merge_operand" " vu, vu, = 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))] + (match_operand: 3 "register_operand" " vr, = vr")) + (match_operand: 4 "pmode_reg_or_uimm5_operand" " rK, = rK")) + (match_operand:VWEXTI 2 "vector_merge_operand" " vu, = 0")))] "TARGET_ZVBB" "vwsll.v%o4\t%0,%3,%4%p1" [(set_attr "type" "vwsll") - (set_attr "mode" "") - (set_attr "vconstraint" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W8= 4,no,no")]) + (set_attr "mode" "")]) =20 ;; vbrev.v vbrev8.v vrev8.v (define_insn "@pred_v" diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 6a4c0e6e10f..228d0f9a766 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -3945,22 +3945,22 @@ (define_insn "@pred_widen_mulsu_scalar" =20 ;; vwcvt.x.x.v (define_insn "@pred_" - [(set (match_operand:VWEXTI 0 "register_operand" "=3Dv= r, vr, vr, vr, vr, vr, ?&vr, ?&vr") + [(set (match_operand:VWEXTI 0 "register_operand" "=3D&v= r,&vr") (if_then_else:VWEXTI (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,v= mWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 4 "vector_length_operand" " rK, rK, = rK, rK, rK, rK, rK, rK") - (match_operand 5 "const_int_operand" " i, i, = i, i, i, i, i, i") - (match_operand 6 "const_int_operand" " i, i, = i, i, i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, = i, i, i, i, i, i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 4 "vector_length_operand" " rK, rK") + (match_operand 5 "const_int_operand" " i, i") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus:VWEXTI (any_extend:VWEXTI - (match_operand: 3 "register_operand" " W21, W21, = W42, W42, W84, W84, vr, vr")) + (match_operand: 3 "register_operand" " vr, vr")= ) (vec_duplicate:VWEXTI (reg: X0_REGNUM))) - (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0, = vu, 0, vu, 0, vu, 0")))] + (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")= ))] "TARGET_VECTOR" "vwcvt.x.x.v\t%0,%3%p1" [(set_attr "type" "viwalu") @@ -3968,8 +3968,7 @@ (define_insn "@pred_" (set_attr "vl_op_idx" "4") (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])")) (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])")) - (set (attr "avl_type_idx") (const_int 7)) - (set_attr "vconstraint" "W21,W21,W42,W42,W84,W84,no,no")]) + (set (attr "avl_type_idx") (const_int 7))]) =20 ;; -----------------------------------------------------------------------= -------- ;; ---- Predicated integer Narrowing operations diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-1.c b/gcc/tes= tsuite/gcc.target/riscv/rvv/base/pr112431-1.c deleted file mode 100644 index 6b9a7c448f0..00000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-1.c +++ /dev/null @@ -1,104 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=3Drv64gcv -mabi=3Dlp64d -O3" } */ - -#include "riscv_vector.h" - -size_t __attribute__ ((noinline)) -sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3, size_t sum4, - size_t sum5, size_t sum6, size_t sum7, size_t sum8, size_t sum9, - size_t sum10, size_t sum11, size_t sum12, size_t sum13, size_t sum14, - size_t sum15) -{ - return sum0 + sum1 + sum2 + sum3 + sum4 + sum5 + sum6 + sum7 + sum8 + su= m9 - + sum10 + sum11 + sum12 + sum13 + sum14 + sum15; -} - -size_t -foo (char const *buf, size_t len) -{ - size_t sum =3D 0; - size_t vl =3D __riscv_vsetvlmax_e8m8 (); - size_t step =3D vl * 4; - const char *it =3D buf, *end =3D buf + len; - for (; it + step <=3D end;) - { - vint8m1_t v0 =3D __riscv_vle8_v_i8m1 ((void *) it, vl); - it +=3D vl; - vint8m1_t v1 =3D __riscv_vle8_v_i8m1 ((void *) it, vl); - it +=3D vl; - vint8m1_t v2 =3D __riscv_vle8_v_i8m1 ((void *) it, vl); - it +=3D vl; - vint8m1_t v3 =3D __riscv_vle8_v_i8m1 ((void *) it, vl); - it +=3D vl; - vint8m1_t v4 =3D __riscv_vle8_v_i8m1 ((void *) it, vl); - it +=3D vl; - vint8m1_t v5 =3D __riscv_vle8_v_i8m1 ((void *) it, vl); - it +=3D vl; - vint8m1_t v6 =3D __riscv_vle8_v_i8m1 ((void *) it, vl); - it +=3D vl; - vint8m1_t v7 =3D __riscv_vle8_v_i8m1 ((void *) it, vl); - it +=3D vl; - vint8m1_t v8 =3D __riscv_vle8_v_i8m1 ((void *) it, vl); - it +=3D vl; - vint8m1_t v9 =3D __riscv_vle8_v_i8m1 ((void *) it, vl); - it +=3D vl; - vint8m1_t v10 =3D __riscv_vle8_v_i8m1 ((void *) it, vl); - it +=3D vl; - vint8m1_t v11 =3D __riscv_vle8_v_i8m1 ((void *) it, vl); - it +=3D vl; - vint8m1_t v12 =3D __riscv_vle8_v_i8m1 ((void *) it, vl); - it +=3D vl; - vint8m1_t v13 =3D __riscv_vle8_v_i8m1 ((void *) it, vl); - it +=3D vl; - vint8m1_t v14 =3D __riscv_vle8_v_i8m1 ((void *) it, vl); - it +=3D vl; - vint8m1_t v15 =3D __riscv_vle8_v_i8m1 ((void *) it, vl); - it +=3D vl; - =20 - asm volatile("nop" ::: "memory"); - vint16m2_t vw0 =3D __riscv_vwcvt_x_x_v_i16m2 (v0, vl); - vint16m2_t vw1 =3D __riscv_vwcvt_x_x_v_i16m2 (v1, vl); - vint16m2_t vw2 =3D __riscv_vwcvt_x_x_v_i16m2 (v2, vl); - vint16m2_t vw3 =3D __riscv_vwcvt_x_x_v_i16m2 (v3, vl); - vint16m2_t vw4 =3D __riscv_vwcvt_x_x_v_i16m2 (v4, vl); - vint16m2_t vw5 =3D __riscv_vwcvt_x_x_v_i16m2 (v5, vl); - vint16m2_t vw6 =3D __riscv_vwcvt_x_x_v_i16m2 (v6, vl); - vint16m2_t vw7 =3D __riscv_vwcvt_x_x_v_i16m2 (v7, vl); - vint16m2_t vw8 =3D __riscv_vwcvt_x_x_v_i16m2 (v8, vl); - vint16m2_t vw9 =3D __riscv_vwcvt_x_x_v_i16m2 (v9, vl); - vint16m2_t vw10 =3D __riscv_vwcvt_x_x_v_i16m2 (v10, vl); - vint16m2_t vw11 =3D __riscv_vwcvt_x_x_v_i16m2 (v11, vl); - vint16m2_t vw12 =3D __riscv_vwcvt_x_x_v_i16m2 (v12, vl); - vint16m2_t vw13 =3D __riscv_vwcvt_x_x_v_i16m2 (v13, vl); - vint16m2_t vw14 =3D __riscv_vwcvt_x_x_v_i16m2 (v14, vl); - vint16m2_t vw15 =3D __riscv_vwcvt_x_x_v_i16m2 (v15, vl); - - asm volatile("nop" ::: "memory"); - size_t sum0 =3D __riscv_vmv_x_s_i16m2_i16 (vw0); - size_t sum1 =3D __riscv_vmv_x_s_i16m2_i16 (vw1); - size_t sum2 =3D __riscv_vmv_x_s_i16m2_i16 (vw2); - size_t sum3 =3D __riscv_vmv_x_s_i16m2_i16 (vw3); - size_t sum4 =3D __riscv_vmv_x_s_i16m2_i16 (vw4); - size_t sum5 =3D __riscv_vmv_x_s_i16m2_i16 (vw5); - size_t sum6 =3D __riscv_vmv_x_s_i16m2_i16 (vw6); - size_t sum7 =3D __riscv_vmv_x_s_i16m2_i16 (vw7); - size_t sum8 =3D __riscv_vmv_x_s_i16m2_i16 (vw8); - size_t sum9 =3D __riscv_vmv_x_s_i16m2_i16 (vw9); - size_t sum10 =3D __riscv_vmv_x_s_i16m2_i16 (vw10); - size_t sum11 =3D __riscv_vmv_x_s_i16m2_i16 (vw11); - size_t sum12 =3D __riscv_vmv_x_s_i16m2_i16 (vw12); - size_t sum13 =3D __riscv_vmv_x_s_i16m2_i16 (vw13); - size_t sum14 =3D __riscv_vmv_x_s_i16m2_i16 (vw14); - size_t sum15 =3D __riscv_vmv_x_s_i16m2_i16 (vw15); - - sum +=3D sumation (sum0, sum1, sum2, sum3, sum4, sum5, sum6, sum7, s= um8, - sum9, sum10, sum11, sum12, sum13, sum14, sum15); - } - return sum; -} - -/* { dg-final { scan-assembler-not {vmv1r} } } */ -/* { dg-final { scan-assembler-not {vmv2r} } } */ -/* { dg-final { scan-assembler-not {vmv4r} } } */ -/* { dg-final { scan-assembler-not {vmv8r} } } */ -/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-2.c b/gcc/tes= tsuite/gcc.target/riscv/rvv/base/pr112431-2.c deleted file mode 100644 index da92d59406f..00000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-2.c +++ /dev/null @@ -1,68 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=3Drv64gcv -mabi=3Dlp64d -O3" } */ - -#include "riscv_vector.h" - -size_t __attribute__ ((noinline)) -sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3, size_t sum4, - size_t sum5, size_t sum6, size_t sum7) -{ - return sum0 + sum1 + sum2 + sum3 + sum4 + sum5 + sum6 + sum7; -} - -size_t -foo (char const *buf, size_t len) -{ - size_t sum =3D 0; - size_t vl =3D __riscv_vsetvlmax_e8m8 (); - size_t step =3D vl * 4; - const char *it =3D buf, *end =3D buf + len; - for (; it + step <=3D end;) - { - vint8m2_t v0 =3D __riscv_vle8_v_i8m2 ((void *) it, vl); - it +=3D vl; - vint8m2_t v1 =3D __riscv_vle8_v_i8m2 ((void *) it, vl); - it +=3D vl; - vint8m2_t v2 =3D __riscv_vle8_v_i8m2 ((void *) it, vl); - it +=3D vl; - vint8m2_t v3 =3D __riscv_vle8_v_i8m2 ((void *) it, vl); - it +=3D vl; - vint8m2_t v4 =3D __riscv_vle8_v_i8m2 ((void *) it, vl); - it +=3D vl; - vint8m2_t v5 =3D __riscv_vle8_v_i8m2 ((void *) it, vl); - it +=3D vl; - vint8m2_t v6 =3D __riscv_vle8_v_i8m2 ((void *) it, vl); - it +=3D vl; - vint8m2_t v7 =3D __riscv_vle8_v_i8m2 ((void *) it, vl); - it +=3D vl; - - asm volatile("nop" ::: "memory"); - vint16m4_t vw0 =3D __riscv_vwcvt_x_x_v_i16m4 (v0, vl); - vint16m4_t vw1 =3D __riscv_vwcvt_x_x_v_i16m4 (v1, vl); - vint16m4_t vw2 =3D __riscv_vwcvt_x_x_v_i16m4 (v2, vl); - vint16m4_t vw3 =3D __riscv_vwcvt_x_x_v_i16m4 (v3, vl); - vint16m4_t vw4 =3D __riscv_vwcvt_x_x_v_i16m4 (v4, vl); - vint16m4_t vw5 =3D __riscv_vwcvt_x_x_v_i16m4 (v5, vl); - vint16m4_t vw6 =3D __riscv_vwcvt_x_x_v_i16m4 (v6, vl); - vint16m4_t vw7 =3D __riscv_vwcvt_x_x_v_i16m4 (v7, vl); - - asm volatile("nop" ::: "memory"); - size_t sum0 =3D __riscv_vmv_x_s_i16m4_i16 (vw0); - size_t sum1 =3D __riscv_vmv_x_s_i16m4_i16 (vw1); - size_t sum2 =3D __riscv_vmv_x_s_i16m4_i16 (vw2); - size_t sum3 =3D __riscv_vmv_x_s_i16m4_i16 (vw3); - size_t sum4 =3D __riscv_vmv_x_s_i16m4_i16 (vw4); - size_t sum5 =3D __riscv_vmv_x_s_i16m4_i16 (vw5); - size_t sum6 =3D __riscv_vmv_x_s_i16m4_i16 (vw6); - size_t sum7 =3D __riscv_vmv_x_s_i16m4_i16 (vw7); - - sum +=3D sumation (sum0, sum1, sum2, sum3, sum4, sum5, sum6, sum7); - } - return sum; -} - -/* { dg-final { scan-assembler-not {vmv1r} } } */ -/* { dg-final { scan-assembler-not {vmv2r} } } */ -/* { dg-final { scan-assembler-not {vmv4r} } } */ -/* { dg-final { scan-assembler-not {vmv8r} } } */ -/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-3.c b/gcc/tes= tsuite/gcc.target/riscv/rvv/base/pr112431-3.c deleted file mode 100644 index 46f93a9049b..00000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-3.c +++ /dev/null @@ -1,51 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=3Drv64gcv -mabi=3Dlp64d -O3" } */ - -#include "riscv_vector.h" - -size_t __attribute__ ((noinline)) -sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3) -{ - return sum0 + sum1 + sum2 + sum3; -} - -size_t -foo (char const *buf, size_t len) -{ - size_t sum =3D 0; - size_t vl =3D __riscv_vsetvlmax_e8m8 (); - size_t step =3D vl * 4; - const char *it =3D buf, *end =3D buf + len; - for (; it + step <=3D end;) - { - vint8m4_t v0 =3D __riscv_vle8_v_i8m4 ((void *) it, vl); - it +=3D vl; - vint8m4_t v1 =3D __riscv_vle8_v_i8m4 ((void *) it, vl); - it +=3D vl; - vint8m4_t v2 =3D __riscv_vle8_v_i8m4 ((void *) it, vl); - it +=3D vl; - vint8m4_t v3 =3D __riscv_vle8_v_i8m4 ((void *) it, vl); - it +=3D vl; - - asm volatile("nop" ::: "memory"); - vint16m8_t vw0 =3D __riscv_vwcvt_x_x_v_i16m8 (v0, vl); - vint16m8_t vw1 =3D __riscv_vwcvt_x_x_v_i16m8 (v1, vl); - vint16m8_t vw2 =3D __riscv_vwcvt_x_x_v_i16m8 (v2, vl); - vint16m8_t vw3 =3D __riscv_vwcvt_x_x_v_i16m8 (v3, vl); - - asm volatile("nop" ::: "memory"); - size_t sum0 =3D __riscv_vmv_x_s_i16m8_i16 (vw0); - size_t sum1 =3D __riscv_vmv_x_s_i16m8_i16 (vw1); - size_t sum2 =3D __riscv_vmv_x_s_i16m8_i16 (vw2); - size_t sum3 =3D __riscv_vmv_x_s_i16m8_i16 (vw3); - - sum +=3D sumation (sum0, sum1, sum2, sum3); - } - return sum; -} - -/* { dg-final { scan-assembler-not {vmv1r} } } */ -/* { dg-final { scan-assembler-not {vmv2r} } } */ -/* { dg-final { scan-assembler-not {vmv4r} } } */ -/* { dg-final { scan-assembler-not {vmv8r} } } */ -/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-39.c b/gcc/te= stsuite/gcc.target/riscv/rvv/base/pr112431-39.c index 770b5411666..1234718bb35 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-39.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-39.c @@ -155,4 +155,4 @@ foo2 (void *in, void *out, int n) /* { dg-final { scan-assembler-not {vmv2r} { xfail riscv*-*-* } } } */ /* { dg-final { scan-assembler-not {vmv4r} } } */ /* { dg-final { scan-assembler-not {vmv8r} } } */ -/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-40.c b/gcc/te= stsuite/gcc.target/riscv/rvv/base/pr112431-40.c index f044a504fc8..5d6577cfe6e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-40.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-40.c @@ -91,4 +91,4 @@ foo2 (void *in, void *out, int n) /* { dg-final { scan-assembler-not {vmv2r} } } */ /* { dg-final { scan-assembler-not {vmv4r} { xfail riscv*-*-* } } } */ /* { dg-final { scan-assembler-not {vmv8r} } } */ -/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-41.c b/gcc/te= stsuite/gcc.target/riscv/rvv/base/pr112431-41.c index 6bdcac82ea8..c31144c05b5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-41.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-41.c @@ -59,4 +59,4 @@ foo2 (void *in, void *out, int n) /* { dg-final { scan-assembler-not {vmv2r} } } */ /* { dg-final { scan-assembler-not {vmv4r} } } */ /* { dg-final { scan-assembler-not {vmv8r} { xfail riscv*-*-* } } } */ -/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */ --=20 2.34.1