RE: [PATCH v1] RISC-V: Support RVV VFWSUB rounding mode intrinsic API

["Li, Pan2" <pan2.li@intel.com>]

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Committed, thanks Kito.

Pan

From: Kito Cheng <kito.cheng@gmail.com>
Sent: Wednesday, August 2, 2023 9:48 PM
To: Li, Pan2 <pan2.li@intel.com>
Cc: GCC Patches <gcc-patches@gcc.gnu.org>; 钟居哲 <juzhe.zhong@rivai.ai>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: [PATCH v1] RISC-V: Support RVV VFWSUB rounding mode intrinsic API

LGTM, thanks:)

Pan Li via Gcc-patches <gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>> 於 2023年8月2日 週三 18:19 寫道：
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>

This patch would like to support the rounding mode API for the VFWSUB
for the below samples.

    * __riscv_vfwsub_vv_f64m2_rm
    * __riscv_vfwsub_vv_f64m2_rm_m
    * __riscv_vfwsub_vf_f64m2_rm
    * __riscv_vfwsub_vf_f64m2_rm_m
    * __riscv_vfwsub_wv_f64m2_rm
    * __riscv_vfwsub_wv_f64m2_rm_m
    * __riscv_vfwsub_wf_f64m2_rm
    * __riscv_vfwsub_wf_f64m2_rm_m

Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>

gcc/ChangeLog:

        * config/riscv/riscv-vector-builtins-bases.cc (BASE): Add
        vfwsub frm.
        * config/riscv/riscv-vector-builtins-bases.h: Add declaration.
        * config/riscv/riscv-vector-builtins-functions.def (vfwsub_frm):
        Add vfwsub function definitions.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/base/float-point-widening-sub.c: New test.
---
 .../riscv/riscv-vector-builtins-bases.cc      |  3 +
 .../riscv/riscv-vector-builtins-bases.h       |  1 +
 .../riscv/riscv-vector-builtins-functions.def |  4 ++
 .../riscv/rvv/base/float-point-widening-sub.c | 66 +++++++++++++++++++
 4 files changed, 74 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-sub.c

diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 981a4a7ede8..ddf694c771c 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -317,6 +317,7 @@ public:

 /* Implements below instructions for frm
    - vfwadd
+   - vfwsub
 */
 template<rtx_code CODE>
 class widen_binop_frm : public function_base
@@ -2100,6 +2101,7 @@ static CONSTEXPR const reverse_binop_frm<MINUS> vfrsub_frm_obj;
 static CONSTEXPR const widen_binop<PLUS> vfwadd_obj;
 static CONSTEXPR const widen_binop_frm<PLUS> vfwadd_frm_obj;
 static CONSTEXPR const widen_binop<MINUS> vfwsub_obj;
+static CONSTEXPR const widen_binop_frm<MINUS> vfwsub_frm_obj;
 static CONSTEXPR const binop<MULT> vfmul_obj;
 static CONSTEXPR const binop<DIV> vfdiv_obj;
 static CONSTEXPR const reverse_binop<DIV> vfrdiv_obj;
@@ -2330,6 +2332,7 @@ BASE (vfrsub_frm)
 BASE (vfwadd)
 BASE (vfwadd_frm)
 BASE (vfwsub)
+BASE (vfwsub_frm)
 BASE (vfmul)
 BASE (vfdiv)
 BASE (vfrdiv)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h
index f9e1df5fe75..5800fca0169 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -150,6 +150,7 @@ extern const function_base *const vfrsub_frm;
 extern const function_base *const vfwadd;
 extern const function_base *const vfwadd_frm;
 extern const function_base *const vfwsub;
+extern const function_base *const vfwsub_frm;
 extern const function_base *const vfmul;
 extern const function_base *const vfmul;
 extern const function_base *const vfdiv;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 743205a9b97..58a7224fe0c 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -306,8 +306,12 @@ DEF_RVV_FUNCTION (vfwsub, widen_alu, full_preds, f_wwv_ops)
 DEF_RVV_FUNCTION (vfwsub, widen_alu, full_preds, f_wwf_ops)
 DEF_RVV_FUNCTION (vfwadd_frm, widen_alu_frm, full_preds, f_wvv_ops)
 DEF_RVV_FUNCTION (vfwadd_frm, widen_alu_frm, full_preds, f_wvf_ops)
+DEF_RVV_FUNCTION (vfwsub_frm, widen_alu_frm, full_preds, f_wvv_ops)
+DEF_RVV_FUNCTION (vfwsub_frm, widen_alu_frm, full_preds, f_wvf_ops)
 DEF_RVV_FUNCTION (vfwadd_frm, widen_alu_frm, full_preds, f_wwv_ops)
 DEF_RVV_FUNCTION (vfwadd_frm, widen_alu_frm, full_preds, f_wwf_ops)
+DEF_RVV_FUNCTION (vfwsub_frm, widen_alu_frm, full_preds, f_wwv_ops)
+DEF_RVV_FUNCTION (vfwsub_frm, widen_alu_frm, full_preds, f_wwf_ops)

 // 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
 DEF_RVV_FUNCTION (vfmul, alu, full_preds, f_vvv_ops)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-sub.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-sub.c
new file mode 100644
index 00000000000..4325cc510a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-sub.c
@@ -0,0 +1,66 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat64m2_t
+test_vfwsub_vv_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
+  return __riscv_vfwsub_vv_f64m2_rm (op1, op2, 0, vl);
+}
+
+vfloat64m2_t
+test_vfwsub_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2,
+                          size_t vl) {
+  return __riscv_vfwsub_vv_f64m2_rm_m (mask, op1, op2, 1, vl);
+}
+
+vfloat64m2_t
+test_vfwsub_vf_f32m1_rm (vfloat32m1_t op1, float32_t op2, size_t vl) {
+  return __riscv_vfwsub_vf_f64m2_rm (op1, op2, 2, vl);
+}
+
+vfloat64m2_t
+test_vfwsub_vf_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2,
+                          size_t vl) {
+  return __riscv_vfwsub_vf_f64m2_rm_m (mask, op1, op2, 3, vl);
+}
+
+vfloat64m2_t
+test_vfwsub_wv_f32m1_rm (vfloat64m2_t op1, vfloat32m1_t op2, size_t vl) {
+  return __riscv_vfwsub_wv_f64m2_rm (op1, op2, 0, vl);
+}
+
+vfloat64m2_t
+test_vfwsub_wv_f32m1_rm_m (vbool32_t mask, vfloat64m2_t op1, vfloat32m1_t op2,
+                          size_t vl) {
+  return __riscv_vfwsub_wv_f64m2_rm_m (mask, op1, op2, 1, vl);
+}
+
+vfloat64m2_t
+test_vfwsub_wf_f32m1_rm (vfloat64m2_t op1, float32_t op2, size_t vl) {
+  return __riscv_vfwsub_wf_f64m2_rm (op1, op2, 2, vl);
+}
+
+vfloat64m2_t
+test_vfwsub_wf_f32m1_rm_m (vbool32_t mask, vfloat64m2_t op1, float32_t op2,
+                          size_t vl) {
+  return __riscv_vfwsub_wf_f64m2_rm_m (mask, op1, op2, 3, vl);
+}
+
+vfloat64m2_t
+test_vfwsub_vv_f32m1 (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
+  return __riscv_vfwsub_vv_f64m2 (op1, op2, vl);
+}
+
+vfloat64m2_t
+test_vfwsub_vv_f32m1_m (vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2,
+                       size_t vl) {
+  return __riscv_vfwsub_vv_f64m2_m (mask, op1, op2, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfwsub\.[vw][vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 10 } } */
+/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 8 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 8 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 8 } } */
--
2.34.1