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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MW5PR11MB5908.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: c25c4635-c052-4b30-4a34-08db3682796f X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Apr 2023 09:37:01.3913 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: nhJWNfIi4Ot8T5biv5odrugOkDk5ah8wxZfYI1LfD7I1WB7mRSQ39hxy5iZGd6JVLxWsWT6s6yttQId54uwUxw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR11MB8143 X-OriginatorOrg: intel.com X-Spam-Status: No, score=-5.9 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Yes, RISC-V riscv.h defined the WORD_REGISTER_OPERATIONS to be 1, while aar= ch64.h defined it as 0, with below comments. No idea this can fit RISC-V or= not. /* WORD_REGISTER_OPERATIONS does not hold for AArch64. The assigned word_mode is DImode but operations narrower than SImode behave as 32-bit operations if using the W-form of the registers rather than as word_mode (64-bit) operations as WORD_REGISTER_OPERATIONS expects. */ #define WORD_REGISTER_OPERATIONS 0 Pan -----Original Message----- From: Gcc-patches On = Behalf Of Richard Sandiford via Gcc-patches Sent: Thursday, April 6, 2023 5:31 PM To: Jeff Law Cc: Jakub Jelinek ; Richard Biener ; E= ric Botcazou ; gcc-patches@gcc.gnu.org Subject: Re: [PATCH] dse: Handle SUBREGs of word REGs differently for WORD_= REGISTER_OPERATIONS targets [PR109040] Jeff Law writes: > On 4/5/23 10:48, Jakub Jelinek wrote: >> On Wed, Apr 05, 2023 at 10:17:59AM -0600, Jeff Law wrote: >>>> It is true that an instruction like (insn 8 7 9 2 (set (reg:HI 141) >>>> (subreg:HI (reg:SI 142) 0)) "aauu.c":6:18 181 {*movhi_intern= al} >>>> (nil)) >>>> can appear in the IL on WORD_REGISTER_OPERATIONS target, but I=20 >>>> think the upper bits shouldn't be random garbage in that case, it=20 >>>> should be zero extended or sign extended. >>> Well, that's one of the core questions here. What are the state of=20 >>> the upper 16 bits of (reg:HI 141)? The WORD_REGISTER_OPERATIONS=20 >>> docs aren't 100% clear as we're not really doing any operation. >>> >>> So again, I think we need to decide if the DSE transformation is=20 >>> correct or not. I *think* we can aggree that insn 39 is OK. It's=20 >>> really the semantics of insn 47 that I think we need to agree on. =20 >>> What is the state of the upper >>> 16 bits of (reg:HI 175) after insn 47? >>=20 >> I'm afraid I don't know the answers here, I think Eric is=20 >> WORD_REGISTER_OPERATIONS expert here I think these days (most of the=20 >> major targets are !WORD_REGISTER_OPERATIONS). > Hopefully he'll chime in. Just curious: have you experimented with making RISC-V !WORD_REGISTER_OPERA= TIONS too? Realise it's not the right way to fix the bug, just curious in = general. Not defining it seems to have worked well for AArch64. And IMO the semanti= cs are much easier to follow when there is no special treatment of upper bi= ts. Subregs are hard enough to reason about as it is... Richard