[PATCH v1] RISC-V: Bugfix for legitimize address PR/111634

[PATCH v1] RISC-V: Bugfix for legitimize address PR/111634

[pan2.li]

From: Pan Li <pan2.li@intel.com>

Given we have RTL as below.

(plus:DI (mult:DI (reg:DI 138 [ g.4_6 ])
                  (const_int 8 [0x8]))
         (lo_sum:DI (reg:DI 167)
                    (symbol_ref:DI ("f") [flags 0x86] <var_decl 0x7fa96ea1cc60 f>)
))

When handling (plus (plus (mult (a) (mem_shadd_constant)) (fp)) (C)) case,
the fp will be the lo_sum operand as above. We have assumption that the fp
is reg but actually not here. It will have ICE when building with option
--enable-checking=rtl.

This patch would like to fix it by adding the REG_P to ensure the operand
is a register. The test case gcc/testsuite/gcc.dg/pr109417.c covered this
fix when build with --enable-checking=rtl.

	PR target/111634

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_legitimize_address): Bugfix.

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 gcc/config/riscv/riscv.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index d5446b63dbf..2b839241f1a 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2042,7 +2042,7 @@ riscv_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
 	{
 	  rtx index = XEXP (base, 0);
 	  rtx fp = XEXP (base, 1);
-	  if (REGNO (fp) == VIRTUAL_STACK_VARS_REGNUM)
+	  if (REG_P (fp) && REGNO (fp) == VIRTUAL_STACK_VARS_REGNUM)
 	    {
 
 	      /* If we were given a MULT, we must fix the constant
-- 
2.34.1

Re: [PATCH v1] RISC-V: Bugfix for legitimize address PR/111634

[Jeff Law]

On 10/6/23 22:49, pan2.li@intel.com wrote:
> From: Pan Li <pan2.li@intel.com>
> 
> Given we have RTL as below.
> 
> (plus:DI (mult:DI (reg:DI 138 [ g.4_6 ])
>                    (const_int 8 [0x8]))
>           (lo_sum:DI (reg:DI 167)
>                      (symbol_ref:DI ("f") [flags 0x86] <var_decl 0x7fa96ea1cc60 f>)
> ))
> 
> When handling (plus (plus (mult (a) (mem_shadd_constant)) (fp)) (C)) case,
> the fp will be the lo_sum operand as above. We have assumption that the fp
> is reg but actually not here. It will have ICE when building with option
> --enable-checking=rtl.
> 
> This patch would like to fix it by adding the REG_P to ensure the operand
> is a register. The test case gcc/testsuite/gcc.dg/pr109417.c covered this
> fix when build with --enable-checking=rtl.
> 
> 	PR target/111634
> 
> gcc/ChangeLog:
> 
> 	* config/riscv/riscv.cc (riscv_legitimize_address): Bugfix.
OK, though the ChangeLog entry could be better.  Perhaps

	* config/riscv/riscv.cc (riscv_legitimize_address): Ensure
	object is a REG before extracting its register number.


Jeff

RE: [PATCH v1] RISC-V: Bugfix for legitimize address PR/111634

[Li, Pan2]

Thanks Jeff, committed with a better Changelog as your suggestion.

Pan

-----Original Message-----
From: Jeff Law <jeffreyalaw@gmail.com> 
Sent: Saturday, October 7, 2023 12:53 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches@gcc.gnu.org
Cc: juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng@gmail.com
Subject: Re: [PATCH v1] RISC-V: Bugfix for legitimize address PR/111634



On 10/6/23 22:49, pan2.li@intel.com wrote:
> From: Pan Li <pan2.li@intel.com>
> 
> Given we have RTL as below.
> 
> (plus:DI (mult:DI (reg:DI 138 [ g.4_6 ])
>                    (const_int 8 [0x8]))
>           (lo_sum:DI (reg:DI 167)
>                      (symbol_ref:DI ("f") [flags 0x86] <var_decl 0x7fa96ea1cc60 f>)
> ))
> 
> When handling (plus (plus (mult (a) (mem_shadd_constant)) (fp)) (C)) case,
> the fp will be the lo_sum operand as above. We have assumption that the fp
> is reg but actually not here. It will have ICE when building with option
> --enable-checking=rtl.
> 
> This patch would like to fix it by adding the REG_P to ensure the operand
> is a register. The test case gcc/testsuite/gcc.dg/pr109417.c covered this
> fix when build with --enable-checking=rtl.
> 
> 	PR target/111634
> 
> gcc/ChangeLog:
> 
> 	* config/riscv/riscv.cc (riscv_legitimize_address): Bugfix.
OK, though the ChangeLog entry could be better.  Perhaps

	* config/riscv/riscv.cc (riscv_legitimize_address): Ensure
	object is a REG before extracting its register number.


Jeff