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* [PATCH v1] RISC-V: Fix fortran ICE/PR111546 when RV32 vec_init
@ 2023-09-24  3:45 pan2.li
  2023-09-24  4:14 ` 钟居哲
  2023-09-24  5:50 ` [PATCH v2] " pan2.li
  0 siblings, 2 replies; 5+ messages in thread
From: pan2.li @ 2023-09-24  3:45 UTC (permalink / raw)
  To: gcc-patches; +Cc: juzhe.zhong, pan2.li, yanzhang.wang, kito.cheng, patrick

From: Pan Li <pan2.li@intel.com>

When broadcast the reperated element, we take the mask machine mode
by mistake. This patch would like to fix it by leveraging the machine
mode of the element.

The below test case in RV32 will be fixed.

* gcc/testsuite/gfortran.dg/overload_5.f90

	PR target/111546

gcc/ChangeLog:

	* config/riscv/riscv-v.cc
	(expand_vector_init_merge_repeating_sequence): Bugfix

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 gcc/config/riscv/riscv-v.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index c2466b1354f..6fcbd1622af 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -2059,7 +2059,7 @@ expand_vector_init_merge_repeating_sequence (rtx target,
   uint64_t full_nelts = builder.full_nelts ().to_constant ();
 
   /* Step 1: Broadcast the first pattern.  */
-  rtx ops[] = {target, force_reg (GET_MODE_INNER (dup_mode), builder.elt (0))};
+  rtx ops[] = {target, force_reg (builder.inner_mode (), builder.elt (0))};
   emit_vlmax_insn (code_for_pred_broadcast (builder.mode ()),
 		    UNARY_OP, ops);
   /* Step 2: Merge the rest iteration of pattern.  */
-- 
2.34.1


^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH v1] RISC-V: Fix fortran ICE/PR111546 when RV32 vec_init
  2023-09-24  3:45 [PATCH v1] RISC-V: Fix fortran ICE/PR111546 when RV32 vec_init pan2.li
@ 2023-09-24  4:14 ` 钟居哲
  2023-09-24  5:50 ` [PATCH v2] " pan2.li
  1 sibling, 0 replies; 5+ messages in thread
From: 钟居哲 @ 2023-09-24  4:14 UTC (permalink / raw)
  To: pan2.li, gcc-patches; +Cc: pan2.li, yanzhang.wang, kito.cheng, patrick

[-- Attachment #1: Type: text/plain, Size: 1923 bytes --]

The codes here are quite confusing.
Plz rename it:

  /* We can't use BIT mode (BI) directly to generate mask = 0b01010...
     since we don't have such instruction in RVV.
     Instead, we should use INT mode (QI/HI/SI/DI) with integer move instruction
     to generate the mask data we want.  */
  machine_mode mask_int_mode = get_repeating_sequence_dup_machine_mode (builder);
  machine_mode mask_bit_mode = get_mask_mode (builder.mode ());



juzhe.zhong@rivai.ai
 
From: pan2.li
Date: 2023-09-24 11:45
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng; patrick
Subject: [PATCH v1] RISC-V: Fix fortran ICE/PR111546 when RV32 vec_init
From: Pan Li <pan2.li@intel.com>
 
When broadcast the reperated element, we take the mask machine mode
by mistake. This patch would like to fix it by leveraging the machine
mode of the element.
 
The below test case in RV32 will be fixed.
 
* gcc/testsuite/gfortran.dg/overload_5.f90
 
PR target/111546
 
gcc/ChangeLog:
 
* config/riscv/riscv-v.cc
(expand_vector_init_merge_repeating_sequence): Bugfix
 
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/config/riscv/riscv-v.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
 
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index c2466b1354f..6fcbd1622af 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -2059,7 +2059,7 @@ expand_vector_init_merge_repeating_sequence (rtx target,
   uint64_t full_nelts = builder.full_nelts ().to_constant ();
   /* Step 1: Broadcast the first pattern.  */
-  rtx ops[] = {target, force_reg (GET_MODE_INNER (dup_mode), builder.elt (0))};
+  rtx ops[] = {target, force_reg (builder.inner_mode (), builder.elt (0))};
   emit_vlmax_insn (code_for_pred_broadcast (builder.mode ()),
    UNARY_OP, ops);
   /* Step 2: Merge the rest iteration of pattern.  */
-- 
2.34.1
 
 

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH v2] RISC-V: Fix fortran ICE/PR111546 when RV32 vec_init
  2023-09-24  3:45 [PATCH v1] RISC-V: Fix fortran ICE/PR111546 when RV32 vec_init pan2.li
  2023-09-24  4:14 ` 钟居哲
@ 2023-09-24  5:50 ` pan2.li
  2023-09-24  6:06   ` 钟居哲
  1 sibling, 1 reply; 5+ messages in thread
From: pan2.li @ 2023-09-24  5:50 UTC (permalink / raw)
  To: gcc-patches; +Cc: juzhe.zhong, pan2.li, yanzhang.wang, kito.cheng, patrick

From: Pan Li <pan2.li@intel.com>

When broadcast the reperated element, we take the mask_int_mode
by mistake. This patch would like to fix it by leveraging the machine
mode of the element.

The below test case in RV32 will be fixed.

* gcc/testsuite/gfortran.dg/overload_5.f90

	PR target/111546

gcc/ChangeLog:

	* config/riscv/riscv-v.cc
	(expand_vector_init_merge_repeating_sequence): Bugfix

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 gcc/config/riscv/riscv-v.cc | 22 ++++++++++++++--------
 1 file changed, 14 insertions(+), 8 deletions(-)

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index c2466b1354f..a1ffefb23f3 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -2054,12 +2054,17 @@ static void
 expand_vector_init_merge_repeating_sequence (rtx target,
 					     const rvv_builder &builder)
 {
-  machine_mode dup_mode = get_repeating_sequence_dup_machine_mode (builder);
-  machine_mode mask_mode = get_mask_mode (builder.mode ());
+  /* We can't use BIT mode (BI) directly to generate mask = 0b01010...
+     since we don't have such instruction in RVV.
+     Instead, we should use INT mode (QI/HI/SI/DI) with integer move
+     instruction to generate the mask data we want.  */
+  machine_mode mask_int_mode
+    = get_repeating_sequence_dup_machine_mode (builder);
+  machine_mode mask_bit_mode = get_mask_mode (builder.mode ());
   uint64_t full_nelts = builder.full_nelts ().to_constant ();
 
   /* Step 1: Broadcast the first pattern.  */
-  rtx ops[] = {target, force_reg (GET_MODE_INNER (dup_mode), builder.elt (0))};
+  rtx ops[] = {target, force_reg (builder.inner_mode (), builder.elt (0))};
   emit_vlmax_insn (code_for_pred_broadcast (builder.mode ()),
 		    UNARY_OP, ops);
   /* Step 2: Merge the rest iteration of pattern.  */
@@ -2067,8 +2072,8 @@ expand_vector_init_merge_repeating_sequence (rtx target,
     {
       /* Step 2-1: Generate mask register v0 for each merge.  */
       rtx merge_mask = builder.get_merge_scalar_mask (i);
-      rtx mask = gen_reg_rtx (mask_mode);
-      rtx dup = gen_reg_rtx (dup_mode);
+      rtx mask = gen_reg_rtx (mask_bit_mode);
+      rtx dup = gen_reg_rtx (mask_int_mode);
 
       if (full_nelts <= builder.inner_bits_size ()) /* vmv.s.x.  */
 	{
@@ -2078,14 +2083,15 @@ expand_vector_init_merge_repeating_sequence (rtx target,
 	}
       else /* vmv.v.x.  */
 	{
-	  rtx ops[] = {dup, force_reg (GET_MODE_INNER (dup_mode), merge_mask)};
+	  rtx ops[] = {dup,
+		       force_reg (GET_MODE_INNER (mask_int_mode), merge_mask)};
 	  rtx vl = gen_int_mode (CEIL (full_nelts, builder.inner_bits_size ()),
 				 Pmode);
-	  emit_nonvlmax_insn (code_for_pred_broadcast (dup_mode), UNARY_OP,
+	  emit_nonvlmax_insn (code_for_pred_broadcast (mask_int_mode), UNARY_OP,
 			       ops, vl);
 	}
 
-      emit_move_insn (mask, gen_lowpart (mask_mode, dup));
+      emit_move_insn (mask, gen_lowpart (mask_bit_mode, dup));
 
       /* Step 2-2: Merge pattern according to the mask.  */
       rtx ops[] = {target, target, builder.elt (i), mask};
-- 
2.34.1


^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH v2] RISC-V: Fix fortran ICE/PR111546 when RV32 vec_init
  2023-09-24  5:50 ` [PATCH v2] " pan2.li
@ 2023-09-24  6:06   ` 钟居哲
  2023-09-24  9:10     ` Li, Pan2
  0 siblings, 1 reply; 5+ messages in thread
From: 钟居哲 @ 2023-09-24  6:06 UTC (permalink / raw)
  To: pan2.li, gcc-patches; +Cc: pan2.li, yanzhang.wang, kito.cheng, patrick

[-- Attachment #1: Type: text/plain, Size: 3349 bytes --]

LGTM



juzhe.zhong@rivai.ai
 
From: pan2.li
Date: 2023-09-24 13:50
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng; patrick
Subject: [PATCH v2] RISC-V: Fix fortran ICE/PR111546 when RV32 vec_init
From: Pan Li <pan2.li@intel.com>
 
When broadcast the reperated element, we take the mask_int_mode
by mistake. This patch would like to fix it by leveraging the machine
mode of the element.
 
The below test case in RV32 will be fixed.
 
* gcc/testsuite/gfortran.dg/overload_5.f90
 
PR target/111546
 
gcc/ChangeLog:
 
* config/riscv/riscv-v.cc
(expand_vector_init_merge_repeating_sequence): Bugfix
 
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/config/riscv/riscv-v.cc | 22 ++++++++++++++--------
1 file changed, 14 insertions(+), 8 deletions(-)
 
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index c2466b1354f..a1ffefb23f3 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -2054,12 +2054,17 @@ static void
expand_vector_init_merge_repeating_sequence (rtx target,
     const rvv_builder &builder)
{
-  machine_mode dup_mode = get_repeating_sequence_dup_machine_mode (builder);
-  machine_mode mask_mode = get_mask_mode (builder.mode ());
+  /* We can't use BIT mode (BI) directly to generate mask = 0b01010...
+     since we don't have such instruction in RVV.
+     Instead, we should use INT mode (QI/HI/SI/DI) with integer move
+     instruction to generate the mask data we want.  */
+  machine_mode mask_int_mode
+    = get_repeating_sequence_dup_machine_mode (builder);
+  machine_mode mask_bit_mode = get_mask_mode (builder.mode ());
   uint64_t full_nelts = builder.full_nelts ().to_constant ();
   /* Step 1: Broadcast the first pattern.  */
-  rtx ops[] = {target, force_reg (GET_MODE_INNER (dup_mode), builder.elt (0))};
+  rtx ops[] = {target, force_reg (builder.inner_mode (), builder.elt (0))};
   emit_vlmax_insn (code_for_pred_broadcast (builder.mode ()),
    UNARY_OP, ops);
   /* Step 2: Merge the rest iteration of pattern.  */
@@ -2067,8 +2072,8 @@ expand_vector_init_merge_repeating_sequence (rtx target,
     {
       /* Step 2-1: Generate mask register v0 for each merge.  */
       rtx merge_mask = builder.get_merge_scalar_mask (i);
-      rtx mask = gen_reg_rtx (mask_mode);
-      rtx dup = gen_reg_rtx (dup_mode);
+      rtx mask = gen_reg_rtx (mask_bit_mode);
+      rtx dup = gen_reg_rtx (mask_int_mode);
       if (full_nelts <= builder.inner_bits_size ()) /* vmv.s.x.  */
{
@@ -2078,14 +2083,15 @@ expand_vector_init_merge_repeating_sequence (rtx target,
}
       else /* vmv.v.x.  */
{
-   rtx ops[] = {dup, force_reg (GET_MODE_INNER (dup_mode), merge_mask)};
+   rtx ops[] = {dup,
+        force_reg (GET_MODE_INNER (mask_int_mode), merge_mask)};
  rtx vl = gen_int_mode (CEIL (full_nelts, builder.inner_bits_size ()),
Pmode);
-   emit_nonvlmax_insn (code_for_pred_broadcast (dup_mode), UNARY_OP,
+   emit_nonvlmax_insn (code_for_pred_broadcast (mask_int_mode), UNARY_OP,
       ops, vl);
}
-      emit_move_insn (mask, gen_lowpart (mask_mode, dup));
+      emit_move_insn (mask, gen_lowpart (mask_bit_mode, dup));
       /* Step 2-2: Merge pattern according to the mask.  */
       rtx ops[] = {target, target, builder.elt (i), mask};
-- 
2.34.1
 
 

^ permalink raw reply	[flat|nested] 5+ messages in thread

* RE: [PATCH v2] RISC-V: Fix fortran ICE/PR111546 when RV32 vec_init
  2023-09-24  6:06   ` 钟居哲
@ 2023-09-24  9:10     ` Li, Pan2
  0 siblings, 0 replies; 5+ messages in thread
From: Li, Pan2 @ 2023-09-24  9:10 UTC (permalink / raw)
  To: 钟居哲, gcc-patches; +Cc: Wang, Yanzhang, kito.cheng, patrick

[-- Attachment #1: Type: text/plain, Size: 4063 bytes --]

Committed, thanks Juzhe.

Pan

From: 钟居哲 <juzhe.zhong@rivai.ai>
Sent: Sunday, September 24, 2023 2:06 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Li, Pan2 <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng <kito.cheng@gmail.com>; patrick <patrick@rivosinc.com>
Subject: Re: [PATCH v2] RISC-V: Fix fortran ICE/PR111546 when RV32 vec_init

LGTM

________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>

From: pan2.li<mailto:pan2.li@intel.com>
Date: 2023-09-24 13:50
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; pan2.li<mailto:pan2.li@intel.com>; yanzhang.wang<mailto:yanzhang.wang@intel.com>; kito.cheng<mailto:kito.cheng@gmail.com>; patrick<mailto:patrick@rivosinc.com>
Subject: [PATCH v2] RISC-V: Fix fortran ICE/PR111546 when RV32 vec_init
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>

When broadcast the reperated element, we take the mask_int_mode
by mistake. This patch would like to fix it by leveraging the machine
mode of the element.

The below test case in RV32 will be fixed.

* gcc/testsuite/gfortran.dg/overload_5.f90

PR target/111546

gcc/ChangeLog:

* config/riscv/riscv-v.cc
(expand_vector_init_merge_repeating_sequence): Bugfix

Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
---
gcc/config/riscv/riscv-v.cc | 22 ++++++++++++++--------
1 file changed, 14 insertions(+), 8 deletions(-)

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index c2466b1354f..a1ffefb23f3 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -2054,12 +2054,17 @@ static void
expand_vector_init_merge_repeating_sequence (rtx target,
     const rvv_builder &builder)
{
-  machine_mode dup_mode = get_repeating_sequence_dup_machine_mode (builder);
-  machine_mode mask_mode = get_mask_mode (builder.mode ());
+  /* We can't use BIT mode (BI) directly to generate mask = 0b01010...
+     since we don't have such instruction in RVV.
+     Instead, we should use INT mode (QI/HI/SI/DI) with integer move
+     instruction to generate the mask data we want.  */
+  machine_mode mask_int_mode
+    = get_repeating_sequence_dup_machine_mode (builder);
+  machine_mode mask_bit_mode = get_mask_mode (builder.mode ());
   uint64_t full_nelts = builder.full_nelts ().to_constant ();
   /* Step 1: Broadcast the first pattern.  */
-  rtx ops[] = {target, force_reg (GET_MODE_INNER (dup_mode), builder.elt (0))};
+  rtx ops[] = {target, force_reg (builder.inner_mode (), builder.elt (0))};
   emit_vlmax_insn (code_for_pred_broadcast (builder.mode ()),
    UNARY_OP, ops);
   /* Step 2: Merge the rest iteration of pattern.  */
@@ -2067,8 +2072,8 @@ expand_vector_init_merge_repeating_sequence (rtx target,
     {
       /* Step 2-1: Generate mask register v0 for each merge.  */
       rtx merge_mask = builder.get_merge_scalar_mask (i);
-      rtx mask = gen_reg_rtx (mask_mode);
-      rtx dup = gen_reg_rtx (dup_mode);
+      rtx mask = gen_reg_rtx (mask_bit_mode);
+      rtx dup = gen_reg_rtx (mask_int_mode);
       if (full_nelts <= builder.inner_bits_size ()) /* vmv.s.x.  */
{
@@ -2078,14 +2083,15 @@ expand_vector_init_merge_repeating_sequence (rtx target,
}
       else /* vmv.v.x.  */
{
-   rtx ops[] = {dup, force_reg (GET_MODE_INNER (dup_mode), merge_mask)};
+   rtx ops[] = {dup,
+        force_reg (GET_MODE_INNER (mask_int_mode), merge_mask)};
  rtx vl = gen_int_mode (CEIL (full_nelts, builder.inner_bits_size ()),
Pmode);
-   emit_nonvlmax_insn (code_for_pred_broadcast (dup_mode), UNARY_OP,
+   emit_nonvlmax_insn (code_for_pred_broadcast (mask_int_mode), UNARY_OP,
       ops, vl);
}
-      emit_move_insn (mask, gen_lowpart (mask_mode, dup));
+      emit_move_insn (mask, gen_lowpart (mask_bit_mode, dup));
       /* Step 2-2: Merge pattern according to the mask.  */
       rtx ops[] = {target, target, builder.elt (i), mask};
--
2.34.1



^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2023-09-24  9:10 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2023-09-24  3:45 [PATCH v1] RISC-V: Fix fortran ICE/PR111546 when RV32 vec_init pan2.li
2023-09-24  4:14 ` 钟居哲
2023-09-24  5:50 ` [PATCH v2] " pan2.li
2023-09-24  6:06   ` 钟居哲
2023-09-24  9:10     ` Li, Pan2

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