From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by sourceware.org (Postfix) with ESMTPS id 827213858D37 for ; Fri, 3 Nov 2023 03:37:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 827213858D37 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 827213858D37 Authentication-Results: server2.sourceware.org; arc=pass smtp.remote-ip=192.55.52.43 ARC-Seal: i=2; a=rsa-sha256; d=sourceware.org; s=key; t=1698982633; cv=pass; b=BpoPqcOia0pGeGmHZ3chDXZgBAOmSid3gq6+NmV+UYTZiQQomh8tQUKX55CfTHCYiqjZDNI2UlMBiFzndLQSWKd4HJtsN2rrslIogh3FwOmwc2wpVaWhqhXmLVwn4kNGEo3swqAuP/6FOmNISNzZqSV6uSAeAtML6iNlItADldo= ARC-Message-Signature: i=2; a=rsa-sha256; d=sourceware.org; s=key; t=1698982633; c=relaxed/simple; bh=R+jnARf75BlloeflW9zaE3aG1Lvz8TyXqG5WDBidIf4=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=Si7ZaNj6C/A6dcVxs2nOO972I4M9cuz6RCKttoMH+U5G3yChV0/mjMylp8bXlnV8PjvWljiesZFsVFOdoIGcsXFBIGAsgKsHljl1aBRqVNQ1jT/QOAkdxDuYyIOmhR2ghErEkjfj4LPIm6qf2jk/8vfTkaPt8zKB/30/IDEzkrQ= ARC-Authentication-Results: i=2; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698982621; x=1730518621; h=from:to:cc:subject:date:message-id:references: in-reply-to:mime-version; bh=R+jnARf75BlloeflW9zaE3aG1Lvz8TyXqG5WDBidIf4=; b=a+oVp2O6ZvMyTu4JC3IhYQlmBM0vLc9J323CJMmIXqM2DmlwOzE02ao+ ogXGB4v4wUIWPOCzag/Wkgof8A6YGpgrZCcu6NpRLHUpxIF+0up/X4Q6c CpNwhsyeXk/h8WLyG0ZPpgRSVJBk0XT/cGX3YSr8OsEP9zqNYYY76vtzt YAL1pwtTB2OgymHw/Px37llpkCB26tKrwu4hbFKeVv0rrs4v08aaWuw5t 2W/PJJ5DQlT1FwKj5IOA3zLtD1VykJZglPFRfceLtoEFLxVuoUxp3V/wr HzOVToycoqL6kV5ax5TEL1HCFz+xwxo7bhRGH6+Y2VBNbAjNtu/gYzz9c Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10882"; a="475111018" X-IronPort-AV: E=Sophos;i="6.03,273,1694761200"; d="scan'208,217";a="475111018" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Nov 2023 20:36:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.03,273,1694761200"; d="scan'208,217";a="9232337" Received: from orsmsx602.amr.corp.intel.com ([10.22.229.15]) by orviesa001.jf.intel.com with ESMTP/TLS/AES256-GCM-SHA384; 02 Nov 2023 20:37:00 -0700 Received: from orsmsx612.amr.corp.intel.com (10.22.229.25) by ORSMSX602.amr.corp.intel.com (10.22.229.15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Thu, 2 Nov 2023 20:36:59 -0700 Received: from orsedg603.ED.cps.intel.com (10.7.248.4) by orsmsx612.amr.corp.intel.com (10.22.229.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34 via Frontend Transport; Thu, 2 Nov 2023 20:36:59 -0700 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (104.47.55.169) by edgegateway.intel.com (134.134.137.100) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.34; Thu, 2 Nov 2023 20:36:54 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=PA8XD4JytqhETtuYuQ1ulWbX6Qs/JSddhsKhCko/1HGVXXjJZrGYy3hrbZM/3h4WzzJAsdmVaBJ6Zud9IkdPbjEJ0A+HQFWCuHh5BFEZO6qcunYfNtoiNy5BS7sUFQFduGLS7J6aN9j5I5hOf7SyxGXhF2+2ONJidLiWHU/zMcrsNqXcDBx3NPJiiRl5gyExOwSjQgUz+YTemaYdJLF9ovZLslGFiCp57h5zpUBsYZsnTkOhy692Cf5PXVX7ZsPXAO5QbGMxB2ZXVo9d2N/Lwhk1Smg6IBbkgc3ncxa1asmjB3o7xPOX0XFhZiNT2dIg/2LntSuufwi7/ZM7hC2koA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=3ULlCfuKzDaGmVhONfTT1kgPtY220w56o+u4Vebg40g=; b=SIcVx/Bzc+QJtsoXEC0L8tltJc8af+Fd4d5cUks2veIJuV44jBTUtfm5CiWxUnDknL4Sj0V8iPTa/HIEy4FmmNU/7U7nSXjoIVVoEVtwbTXKMZV6gXsupVbKDCuHi7jR2pVV7J41si3lSQd/CZ7kjsTl6arIt0Yd/pu2nT5McN7iuTyamBwbvEzQg4gGD7EEaE0cSf+XoO57D+Z/n5b9kQLvM9/Ai2nf4SHmjrcxv5AKRz4ssxCUUCcjJQtkwegm5eC2Ivee/muayq8FTdHG8OPVsiwopc/m2V5TxbnRdmMOraxtZKbW+LXqRCjLMyjszEURYiQ2+fXf5mW0vy17zg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Received: from MW5PR11MB5908.namprd11.prod.outlook.com (2603:10b6:303:194::10) by SA1PR11MB6685.namprd11.prod.outlook.com (2603:10b6:806:258::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6954.21; Fri, 3 Nov 2023 03:36:49 +0000 Received: from MW5PR11MB5908.namprd11.prod.outlook.com ([fe80::4317:53a0:2638:358c]) by MW5PR11MB5908.namprd11.prod.outlook.com ([fe80::4317:53a0:2638:358c%5]) with mapi id 15.20.6954.021; Fri, 3 Nov 2023 03:36:49 +0000 From: "Li, Pan2" To: "juzhe.zhong@rivai.ai" , gcc-patches CC: "Wang, Yanzhang" , kito.cheng Subject: RE: [PATCH v2] RISC-V: Refactor prefix [I/L/LL] rounding API autovec iterator Thread-Topic: [PATCH v2] RISC-V: Refactor prefix [I/L/LL] rounding API autovec iterator Thread-Index: AQHaDgWS2RP4KK3p7Eui1Szny5/877Bn8J3NgAABPqA= Date: Fri, 3 Nov 2023 03:36:49 +0000 Message-ID: References: <20231102114802.17020-1-pan2.li@intel.com>, <20231103032634.2983364-1-pan2.li@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: MW5PR11MB5908:EE_|SA1PR11MB6685:EE_ x-ms-office365-filtering-correlation-id: 4bc11552-9c4d-4d25-abe5-08dbdc1e1cf9 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: TGxB0B6JEDXUBs7HgXbJS5J2vOMygIv4qLqNBy/JP4pzVLrRTVL6MKsCiXDsnOxMbW29fpwqPTTrWYZxmOZdY0l6EsW9mIR9p4mS7RoqbN16jWxuS4D3khWPR0pTrH6WSQ45TpVKAWbZYup/iP3/CWRhA7oMMQFeosyxIAF4T7CK8WCUbqDeQBLodjwsh09rXo0hX3jILFVuO3A6LThE0smm0ncvf8AjzsTZ/4fB/y1gql3HVxlni2McYFfMveW4ni8Rp72yrQOSyrLorhYL/pqz9KjQqMq8Xw26LVwzjEdsOIZtW397CGzHu7WInGDN72Hb9ygmYMst1fiR8lsI9ohNdergQBYfSl8oG0YsuTSvtWDPSxpypurnVnsoJq36ULQjWHjiAvCo1Fvf5lXWtbFDQqWtsjTgFN/Tx2TJXV0rS9sua34SIAZqRSN/z7C9ge8v30ZFKDPLmJr8KTzmkaImS+vZZJ13dpJH4Le33HB+6miTpz52Eqbft8ImDsql7AV3JEXKcw3Y22MLaT5q3MTMsw2DdXj+CAWs9FtRYaXSRZ3v7uP2fEGdoRHp/RgpEqtvAbqfvKhiKeJXh+NjERDpthM/T+rVFlnLtqMrxgXFDCeN9cWbdj/joA02Waxm x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MW5PR11MB5908.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(396003)(346002)(39860400002)(366004)(136003)(376002)(230922051799003)(64100799003)(186009)(451199024)(1800799009)(2906002)(30864003)(9686003)(7696005)(53546011)(86362001)(26005)(6506007)(33656002)(71200400001)(38070700009)(38100700002)(83380400001)(122000001)(82960400001)(41300700001)(478600001)(76116006)(66476007)(64756008)(66556008)(54906003)(316002)(110136005)(66946007)(52536014)(4326008)(8676002)(8936002)(66446008)(5660300002)(55016003)(579004)(559001);DIR:OUT;SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?9Nbf9cjd4R1IsphaYD9qB4YcudyFjwWlAu20D+E4xRx8wBfWjE/VED4MwHQM?= =?us-ascii?Q?kJ8SCKNZqSllMpDoCxodOoGkKb5PR/QaWXtNMPBE5Rr8vUlrufkMlvuWs1jw?= =?us-ascii?Q?IfKScQ3Zrr8bYMtesfiKjl+tHSxZrqCj+5EPh2QPpvvoqBDj6yLbcFsTeknp?= =?us-ascii?Q?jfXNdPRSuaRFv965ozeCDnmICQyHeFMXodhWigD2IhufWcyk6PCfaMCtJFaL?= =?us-ascii?Q?2DpWr7YDYnOQtCLJX3pQIZbSYN9aljcoLVV2mgKIcqtO0sTS3aVZxueBnT08?= =?us-ascii?Q?ElUMWS4uXvKI3HsZculgpbCAui3O1q6aex2fgTMYSInSdlNSJklf8ZH0xHku?= =?us-ascii?Q?24ExFIa+Tj3xM/lvXDgDF6ykbUpvQ+vMY0xJ1XQJeCVQakO2qdxuBk0PbDPh?= =?us-ascii?Q?9kC+cF+RR6e/umIm6EKmCBLDdLF1fvSny1fCcTeSWN14d7H0LrJ7bLXfHDFK?= =?us-ascii?Q?zCZ5LJHc1nXQLSn6v+wpSShfKwZ8I6544FjrB75tV5a6qVdwwp68f7XIrrNM?= =?us-ascii?Q?lNLTUGfqkv8Z0v3dvGcv8ZOCsNx+v6HRdAzKVo9iP6y2f1huQm8VBNPJEk92?= =?us-ascii?Q?D7COJaM1VCmSdF0rFsf/L95q5TaCEKyqMhpNh8qdjGmx9aWgIyAYI23430Ja?= =?us-ascii?Q?WDvNWmTlY+B5r3YPUNlRmuB4iC/8aEkpEkKDIA7LuiRM05foc3X5vx8TmVUk?= =?us-ascii?Q?2+yzwrG4pSAHqCSB2Xq/Wo6bky69xJPgqf6ZmtFVXWqIaVszJ9DcOF2ZXUJS?= =?us-ascii?Q?LI+8ETmn9oN5/HLslBSNa4XWmXKsUgV3qd/nVktW9wQtPadzZjUo5nf+nKGJ?= =?us-ascii?Q?rFw6UdE/aYvWv+bU/4q3nZ7Y+MnbJLpXIIqFTxP7rF44dqkEy3zU/zfCoyoB?= =?us-ascii?Q?yHnbYSYwV2PdbJ3d+1rw55XUfmYdQR6exoALmWnHBPROtAuJJTNWK1kBm19Q?= =?us-ascii?Q?73wMdeg4A0AeOIz+Mj2E2g3Sn5n24+Fn3pUS3c85hHbI6tXd0JflLH4JJjhz?= =?us-ascii?Q?Wh3h7gJPiKF+o6w6YiiGEUf63ekXGF6uV/AOibh/rfpqt5VTuUX3sqbxRFeu?= =?us-ascii?Q?9lDgCuP2zvcL6kUVRUNbbUHefnTJQDNpIlSRtGPsCOs3U3dPwMqcuRjSydGv?= =?us-ascii?Q?DLoYqwRfzl5WyA6OqH89qfFQF5ZmXDygsr18VfzlU/fKchZq1olZNgpAjxXk?= =?us-ascii?Q?da/tAa+8y/0V3XdoDqSa/z86UVE6jk9rqlrv6DQsNrJepnjFuKvnFF/KzyfA?= =?us-ascii?Q?TpjBGOJpOmB3tuC4L1Ew9cV7/Nv4u4xGlUeKk/G3V1Sic64GEgjdDWK9JtZA?= =?us-ascii?Q?PLrEb2GPaMrHjIvtusF11XZ0lNtSJqWTK0x+0qzFnvcrnJVUVGXnY7abAt0l?= =?us-ascii?Q?XiE7xTxZuiNouDuTe1CcBv+arDftsaSn8zmcv/Z5phlz9ZYsF50wvi7yJawg?= =?us-ascii?Q?raVx2i30U9n8OxzWZXosef5m9d2atJQaozy/XjiCaC1sqEqbx6YB+tei5oNO?= =?us-ascii?Q?9oQ48ydPFdgedFE7E5aqn/YWa5Uznyzowxi+z43hotMiXp3BYOet8lOC0g78?= =?us-ascii?Q?rbOXdKrQ07LT02i4j0A=3D?= Content-Type: multipart/alternative; boundary="_000_MW5PR11MB59082F8756F7B25CDC451AE3A9A5AMW5PR11MB5908namp_" MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MW5PR11MB5908.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4bc11552-9c4d-4d25-abe5-08dbdc1e1cf9 X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Nov 2023 03:36:49.6229 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: ASxFkeVcduLwChjA+X6FkCjWV1EzBbE0ubeR6O2i2kcqNULRxATIGdBTkGDFqnIjNvyNn/kesxMW0M4jjqtENA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR11MB6685 X-OriginatorOrg: intel.com X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,HTML_MESSAGE,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --_000_MW5PR11MB59082F8756F7B25CDC451AE3A9A5AMW5PR11MB5908namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Committed, thanks Juzhe. Pan From: juzhe.zhong@rivai.ai Sent: Friday, November 3, 2023 11:31 AM To: Li, Pan2 ; gcc-patches Cc: Li, Pan2 ; Wang, Yanzhang ;= kito.cheng Subject: Re: [PATCH v2] RISC-V: Refactor prefix [I/L/LL] rounding API autov= ec iterator LGTM. ________________________________ juzhe.zhong@rivai.ai From: pan2.li Date: 2023-11-03 11:26 To: gcc-patches CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng Subject: [PATCH v2] RISC-V: Refactor prefix [I/L/LL] rounding API autovec i= terator From: Pan Li > Update in v2: * Add mode size equal check to disable different mode size when expand, because the underlying codegen is not implemented yet. Original log: The previous rounding API start with i/l/ll only works on the same mode types. For example as below, and we arrange the iterator similar to fcvt. * SF =3D> SI * DF =3D> DI After we refined this limination from middle-end, these API can also vectorized with different type sizes, aka: * HF =3D> SI, HF =3D> DI * SF =3D> DI, SF =3D> SI * DF =3D> SI, DF =3D> DI Then the iterator cannot take care of this simply and this patch would like to re-arrange the iterator in two items. * V_VLS_F_CONVERT_SI: handle (HF, SF, DF) =3D> SI * V_VLS_F_CONVERT_DI: handle (HF, SF, DF) =3D> DI As well as related mode_attr to reconcile the new iterator. gcc/ChangeLog: * config/riscv/autovec.md (lrint2): Remove. (lround2): Ditto. (lceil2): Ditto. (lfloor2): Ditto. (lrint2): New pattern for cvt from FP to SI. (lround2): Ditto. (lceil2): Ditto. (lfloor2): Ditto. (lrint2): New pattern for cvt from FP to DI. (lround2): Ditto. (lceil2): Ditto. (lfloor2): Ditto. * config/riscv/vector-iterators.md: Renew iterators for both the SI and DI. Signed-off-by: Pan Li > --- gcc/config/riscv/autovec.md | 90 +++++++++--- gcc/config/riscv/vector-iterators.md | 199 ++++++++++++++++++++++++--- 2 files changed, 251 insertions(+), 38 deletions(-) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index f5e3e347ace..cc4c9596bbf 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -2395,42 +2395,92 @@ (define_expand "roundeven2" } ) -(define_expand "lrint2" - [(match_operand: 0 "register_operand") - (match_operand:V_VLS_FCONVERT_I_L_LL 1 "register_operand")] - "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math" +;; Add mode_size equal check as we opened the modes for different sizes. +;; The check will be removed soon after related codegen implemented +(define_expand "lrint2" + [(match_operand: 0 "register_operand") + (match_operand:V_VLS_F_CONVERT_SI 1 "register_operand")] + "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math + && known_eq (GET_MODE_SIZE (mode), GET_MODE_SIZE (mode))" { - riscv_vector::expand_vec_lrint (operands[0], operands[1], mode, = mode); + riscv_vector::expand_vec_lrint (operands[0], operands[1], mode, = mode); DONE; } ) -(define_expand "lround2" - [(match_operand: 0 "register_operand") - (match_operand:V_VLS_FCONVERT_I_L_LL 1 "register_operand")] - "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math" +(define_expand "lrint2" + [(match_operand: 0 "register_operand") + (match_operand:V_VLS_F_CONVERT_DI 1 "register_operand")] + "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math + && known_eq (GET_MODE_SIZE (mode), GET_MODE_SIZE (mode))" { - riscv_vector::expand_vec_lround (operands[0], operands[1], mode,= mode); + riscv_vector::expand_vec_lrint (operands[0], operands[1], mode, = mode); DONE; } ) -(define_expand "lceil2" - [(match_operand: 0 "register_operand") - (match_operand:V_VLS_FCONVERT_I_L_LL 1 "register_operand")] - "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math" +(define_expand "lround2" + [(match_operand: 0 "register_operand") + (match_operand:V_VLS_F_CONVERT_SI 1 "register_operand")] + "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math + && known_eq (GET_MODE_SIZE (mode), GET_MODE_SIZE (mode))" { - riscv_vector::expand_vec_lceil (operands[0], operands[1], mode, = mode); + riscv_vector::expand_vec_lround (operands[0], operands[1], mode,= mode); DONE; } ) -(define_expand "lfloor2" - [(match_operand: 0 "register_operand") - (match_operand:V_VLS_FCONVERT_I_L_LL 1 "register_operand")] - "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math" +(define_expand "lround2" + [(match_operand: 0 "register_operand") + (match_operand:V_VLS_F_CONVERT_DI 1 "register_operand")] + "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math + && known_eq (GET_MODE_SIZE (mode), GET_MODE_SIZE (mode))" + { + riscv_vector::expand_vec_lround (operands[0], operands[1], mode,= mode); + DONE; + } +) + +(define_expand "lceil2" + [(match_operand: 0 "register_operand") + (match_operand:V_VLS_F_CONVERT_SI 1 "register_operand")] + "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math + && known_eq (GET_MODE_SIZE (mode), GET_MODE_SIZE (mode))" + { + riscv_vector::expand_vec_lceil (operands[0], operands[1], mode, = mode); + DONE; + } +) + +(define_expand "lceil2" + [(match_operand: 0 "register_operand") + (match_operand:V_VLS_F_CONVERT_DI 1 "register_operand")] + "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math + && known_eq (GET_MODE_SIZE (mode), GET_MODE_SIZE (mode))" + { + riscv_vector::expand_vec_lceil (operands[0], operands[1], mode, = mode); + DONE; + } +) + +(define_expand "lfloor2" + [(match_operand: 0 "register_operand") + (match_operand:V_VLS_F_CONVERT_SI 1 "register_operand")] + "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math + && known_eq (GET_MODE_SIZE (mode), GET_MODE_SIZE (mode))" + { + riscv_vector::expand_vec_lfloor (operands[0], operands[1], mode,= mode); + DONE; + } +) + +(define_expand "lfloor2" + [(match_operand: 0 "register_operand") + (match_operand:V_VLS_F_CONVERT_DI 1 "register_operand")] + "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math + && known_eq (GET_MODE_SIZE (mode), GET_MODE_SIZE (mode))" { - riscv_vector::expand_vec_lfloor (operands[0], operands[1], mode,= mode); + riscv_vector::expand_vec_lfloor (operands[0], operands[1], mode,= mode); DONE; } ) diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector= -iterators.md index d9b5dec5edb..f2d9f60b631 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -3175,44 +3175,104 @@ (define_mode_attr vnnconvert [ (V512DI "v512hf") ]) -;; Convert to int, long and long long -(define_mode_attr V_I_L_LL_CONVERT [ +;; +;; Convert float (VHF, VSF, VDF) to VSI/VDI. +;; The are sorts of rounding mode return integer (take rint as example) +;; - irint +;; - lrint +;; - llrint +;; +;; The long type has different bitsize in RV32 and RV64 makes them even +;; more complicated, details as below. +;; +------------+------------------+------------------+ +;; | builtin | RV32 | RV64 | +;; +------------+------------------+------------------+ +;; | lrintf16 | HF =3D> SI | HF =3D> DI | +;; +------------+------------------+------------------+ +;; | lrintf | SF =3D> SI | SF =3D> DI | +;; +------------+------------------+------------------+ +;; | lrint | DF =3D> SI | DF =3D> DI | +;; +------------+------------------+------------------+ +;; | llrintf16 | HF =3D> DI | Same as RV32 | +;; +------------+------------------+------------------+ +;; | llrintf | SF =3D> DI | Same as RV32 | +;; +------------+------------------+------------------+ +;; | llrint | DF =3D> DI | Same as RV32 | +;; +------------+------------------+------------------+ +;; | irintf16 | HF =3D> SI | Same as RV32 | +;; +------------+------------------+------------------+ +;; | irintf | SF =3D> SI | Same as RV32 | +;; +------------+------------------+------------------+ +;; | irint | DF =3D> SI | Same as RV32 | +;; +------------+------------------+------------------+ +;; +;; The [i/l/ll]rint share the same standard name lrint, +;; and both the RV32 and RV64 has the cases to the SI and DI. +;; For example, both RV32 and RV64 has the below convert: +;; +;; HF =3D> SI (RV32: lrintf16) (RV64: irintf16) +;; HF =3D> DI (RV32: llrintf16) (RV64: lrintf16) +;; +;; Due to we cannot define a mode_attr mapping one HF to both +;; the SI and DI, we use 2 different mode_atter to cover all +;; the combination as above, as well as the different iterator +;; for the lrint patterns. Aka: +;; +;; V_F2SI_CONVERT: (HF, SF, DF) =3D> SI +;; V_F2DI_CONVERT: (HF, SF, DF) =3D> DI +;; +(define_mode_attr V_F2SI_CONVERT [ + (RVVM4HF "RVVM8SI") (RVVM2HF "RVVM4SI") (RVVM1HF "RVVM2SI") + (RVVMF2HF "RVVM1SI") (RVVMF4HF "RVVMF2SI") + (RVVM8SF "RVVM8SI") (RVVM4SF "RVVM4SI") (RVVM2SF "RVVM2SI") (RVVM1SF "RVVM1SI") (RVVMF2SF "RVVMF2SI") - (RVVM8DF "RVVM8DI") (RVVM4DF "RVVM4DI") (RVVM2DF "RVVM2DI") - (RVVM1DF "RVVM1DI") + (RVVM8DF "RVVM4SI") (RVVM4DF "RVVM2SI") (RVVM2DF "RVVM1SI") + (RVVM1DF "RVVMF2SI") + + (V1HF "V1SI") (V2HF "V2SI") (V4HF "V4SI") (V8HF "V8SI") (V16HF "V16SI") + (V32HF "V32SI") (V64HF "V64SI") (V128HF "V128SI") (V256HF "V256SI") + (V512HF "V512SI") (V1024HF "V1024SI") (V1SF "V1SI") (V2SF "V2SI") (V4SF "V4SI") (V8SF "V8SI") (V16SF "V16SI") (V32SF "V32SI") (V64SF "V64SI") (V128SF "V128SI") (V256SF "V256SI") (V512SF "V512SI") (V1024SF "V1024SI") - (V1DF "V1DI") (V2DF "V2DI") (V4DF "V4DI") (V8DF "V8DI") (V16DF "V16DI") - (V32DF "V32DI") (V64DF "V64DI") (V128DF "V128DI") (V256DF "V256DI") - (V512DF "V512DI") + (V1DF "V1SI") (V2DF "V2SI") (V4DF "V4SI") (V8DF "V8SI") (V16DF "V16SI") + (V32DF "V32SI") (V64DF "V64SI") (V128DF "V128SI") (V256DF "V256SI") + (V512DF "V512SI") ]) -(define_mode_attr v_i_l_ll_convert [ +(define_mode_attr v_f2si_convert [ + (RVVM4HF "rvvm8si") (RVVM2HF "rvvm4si") (RVVM1HF "rvvm2si") + (RVVMF2HF "rvvm1si") (RVVMF4HF "rvvmf2si") + (RVVM8SF "rvvm8si") (RVVM4SF "rvvm4si") (RVVM2SF "rvvm2si") (RVVM1SF "rvvm1si") (RVVMF2SF "rvvmf2si") - (RVVM8DF "rvvm8di") (RVVM4DF "rvvm4di") (RVVM2DF "rvvm2di") - (RVVM1DF "rvvm1di") + (RVVM8DF "rvvm4si") (RVVM4DF "rvvm2si") (RVVM2DF "rvvm1si") + (RVVM1DF "rvvmf2si") + + (V1HF "v1si") (V2HF "v2si") (V4HF "v4si") (V8HF "v8si") (V16HF "v16si") + (V32HF "v32si") (V64HF "v64si") (V128HF "v128si") (V256HF "v256si") + (V512HF "v512si") (V1024HF "v1024si") (V1SF "v1si") (V2SF "v2si") (V4SF "v4si") (V8SF "v8si") (V16SF "v16si") (V32SF "v32si") (V64SF "v64si") (V128SF "v128si") (V256SF "v256si") (V512SF "v512si") (V1024SF "v1024si") - (V1DF "v1di") (V2DF "v2di") (V4DF "v4di") (V8DF "v8di") (V16DF "v16di") - (V32DF "v32di") (V64DF "v64di") (V128DF "v128di") (V256DF "v256di") - (V512DF "v512di") + (V1DF "v1si") (V2DF "v2si") (V4DF "v4si") (V8DF "v8si") (V16DF "v16si") + (V32DF "v32si") (V64DF "v64si") (V128DF "v128si") (V256DF "v256si") + (V512DF "v512si") ]) -(define_mode_iterator V_VLS_FCONVERT_I_L_LL [ - (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") - (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") - (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") - (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") +(define_mode_iterator V_VLS_F_CONVERT_SI [ + (RVVM4HF "TARGET_ZVFH") (RVVM2HF "TARGET_ZVFH") (RVVM1HF "TARGET_ZVFH") + (RVVMF2HF "TARGET_ZVFH") (RVVMF4HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32") + + (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") + (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") @@ -3220,6 +3280,18 @@ (define_mode_iterator V_VLS_FCONVERT_I_L_LL [ (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64") + (V1HF "riscv_vector::vls_mode_valid_p (V1HFmode) && TARGET_ZVFH") + (V2HF "riscv_vector::vls_mode_valid_p (V2HFmode) && TARGET_ZVFH") + (V4HF "riscv_vector::vls_mode_valid_p (V4HFmode) && TARGET_ZVFH") + (V8HF "riscv_vector::vls_mode_valid_p (V8HFmode) && TARGET_ZVFH") + (V16HF "riscv_vector::vls_mode_valid_p (V16HFmode) && TARGET_ZVFH") + (V32HF "riscv_vector::vls_mode_valid_p (V32HFmode) && TARGET_ZVFH && TAR= GET_MIN_VLEN >=3D 64") + (V64HF "riscv_vector::vls_mode_valid_p (V64HFmode) && TARGET_ZVFH && TAR= GET_MIN_VLEN >=3D 128") + (V128HF "riscv_vector::vls_mode_valid_p (V128HFmode) && TARGET_ZVFH && T= ARGET_MIN_VLEN >=3D 256") + (V256HF "riscv_vector::vls_mode_valid_p (V256HFmode) && TARGET_ZVFH && T= ARGET_MIN_VLEN >=3D 512") + (V512HF "riscv_vector::vls_mode_valid_p (V512HFmode) && TARGET_ZVFH && T= ARGET_MIN_VLEN >=3D 1024") + (V1024HF "riscv_vector::vls_mode_valid_p (V1024HFmode) && TARGET_ZVFH &&= TARGET_MIN_VLEN >=3D 2048") + (V1SF "riscv_vector::vls_mode_valid_p (V1SFmode) && TARGET_VECTOR_ELEN_F= P_32") (V2SF "riscv_vector::vls_mode_valid_p (V2SFmode) && TARGET_VECTOR_ELEN_F= P_32") (V4SF "riscv_vector::vls_mode_valid_p (V4SFmode) && TARGET_VECTOR_ELEN_F= P_32") @@ -3244,6 +3316,97 @@ (define_mode_iterator V_VLS_FCONVERT_I_L_LL [ (V512DF "riscv_vector::vls_mode_valid_p (V512DFmode) && TARGET_VECTOR_EL= EN_FP_64 && TARGET_MIN_VLEN >=3D 4096") ]) +(define_mode_attr V_F2DI_CONVERT [ + (RVVM2HF "RVVM8DI") (RVVM1HF "RVVM4DI") (RVVMF2HF "RVVM2DI") + (RVVMF4HF "RVVM1DI") + + (RVVM4SF "RVVM8DI") (RVVM2SF "RVVM4DI") (RVVM1SF "RVVM2DI") + (RVVMF2SF "RVVM1DI") + + (RVVM8DF "RVVM8DI") (RVVM4DF "RVVM4DI") (RVVM2DF "RVVM2DI") + (RVVM1DF "RVVM1DI") + + (V1HF "V1DI") (V2HF "V2DI") (V4HF "V4DI") (V8HF "V8DI") (V16HF "V16DI") + (V32HF "V32DI") (V64HF "V64DI") (V128HF "V128DI") (V256HF "V256DI") + (V512HF "V512DI") + + (V1SF "V1DI") (V2SF "V2DI") (V4SF "V4DI") (V8SF "V8DI") (V16SF "V16DI") + (V32SF "V32DI") (V64SF "V64DI") (V128SF "V128DI") (V256SF "V256DI") + (V512SF "V512DI") + + (V1DF "V1DI") (V2DF "V2DI") (V4DF "V4DI") (V8DF "V8DI") (V16DF "V16DI") + (V32DF "V32DI") (V64DF "V64DI") (V128DF "V128DI") (V256DF "V256DI") + (V512DF "V512DI") +]) + +(define_mode_attr v_f2di_convert [ + (RVVM2HF "rvvm8di") (RVVM1HF "rvvm4di") (RVVMF2HF "rvvm2di") + (RVVMF4HF "rvvm1di") + + (RVVM4SF "rvvm8di") (RVVM2SF "rvvm4di") (RVVM1SF "rvvm2di") + (RVVMF2SF "rvvm1di") + + (RVVM8DF "rvvm8di") (RVVM4DF "rvvm4di") (RVVM2DF "rvvm2di") + (RVVM1DF "rvvm1di") + + (V1HF "v1di") (V2HF "v2di") (V4HF "v4di") (V8HF "v8di") (V16HF "v16di") + (V32HF "v32di") (V64HF "v64di") (V128HF "v128di") (V256HF "v256di") + (V512HF "v512di") + + (V1SF "v1di") (V2SF "v2di") (V4SF "v4di") (V8SF "v8di") (V16SF "v16di") + (V32SF "v32di") (V64SF "v64di") (V128SF "v128di") (V256SF "v256di") + (V512SF "v512di") + + (V1DF "v1di") (V2DF "v2di") (V4DF "v4di") (V8DF "v8di") (V16DF "v16di") + (V32DF "v32di") (V64DF "v64di") (V128DF "v128di") (V256DF "v256di") + (V512DF "v512di") +]) + +(define_mode_iterator V_VLS_F_CONVERT_DI [ + (RVVM2HF "TARGET_ZVFH") (RVVM1HF "TARGET_ZVFH") (RVVMF2HF "TARGET_ZVFH") + (RVVMF4HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32") + + (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") + (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") + (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") + + (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64") + (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64") + + (V1HF "riscv_vector::vls_mode_valid_p (V1HFmode) && TARGET_ZVFH") + (V2HF "riscv_vector::vls_mode_valid_p (V2HFmode) && TARGET_ZVFH") + (V4HF "riscv_vector::vls_mode_valid_p (V4HFmode) && TARGET_ZVFH") + (V8HF "riscv_vector::vls_mode_valid_p (V8HFmode) && TARGET_ZVFH") + (V16HF "riscv_vector::vls_mode_valid_p (V16HFmode) && TARGET_ZVFH") + (V32HF "riscv_vector::vls_mode_valid_p (V32HFmode) && TARGET_ZVFH && TAR= GET_MIN_VLEN >=3D 64") + (V64HF "riscv_vector::vls_mode_valid_p (V64HFmode) && TARGET_ZVFH && TAR= GET_MIN_VLEN >=3D 128") + (V128HF "riscv_vector::vls_mode_valid_p (V128HFmode) && TARGET_ZVFH && T= ARGET_MIN_VLEN >=3D 256") + (V256HF "riscv_vector::vls_mode_valid_p (V256HFmode) && TARGET_ZVFH && T= ARGET_MIN_VLEN >=3D 512") + (V512HF "riscv_vector::vls_mode_valid_p (V512HFmode) && TARGET_ZVFH && T= ARGET_MIN_VLEN >=3D 1024") + + (V1SF "riscv_vector::vls_mode_valid_p (V1SFmode) && TARGET_VECTOR_ELEN_F= P_32") + (V2SF "riscv_vector::vls_mode_valid_p (V2SFmode) && TARGET_VECTOR_ELEN_F= P_32") + (V4SF "riscv_vector::vls_mode_valid_p (V4SFmode) && TARGET_VECTOR_ELEN_F= P_32") + (V8SF "riscv_vector::vls_mode_valid_p (V8SFmode) && TARGET_VECTOR_ELEN_F= P_32") + (V16SF "riscv_vector::vls_mode_valid_p (V16SFmode) && TARGET_VECTOR_ELEN= _FP_32 && TARGET_MIN_VLEN >=3D 64") + (V32SF "riscv_vector::vls_mode_valid_p (V32SFmode) && TARGET_VECTOR_ELEN= _FP_32 && TARGET_MIN_VLEN >=3D 128") + (V64SF "riscv_vector::vls_mode_valid_p (V64SFmode) && TARGET_VECTOR_ELEN= _FP_32 && TARGET_MIN_VLEN >=3D 256") + (V128SF "riscv_vector::vls_mode_valid_p (V128SFmode) && TARGET_VECTOR_EL= EN_FP_32 && TARGET_MIN_VLEN >=3D 512") + (V256SF "riscv_vector::vls_mode_valid_p (V256SFmode) && TARGET_VECTOR_EL= EN_FP_32 && TARGET_MIN_VLEN >=3D 1024") + (V512SF "riscv_vector::vls_mode_valid_p (V512SFmode) && TARGET_VECTOR_EL= EN_FP_32 && TARGET_MIN_VLEN >=3D 2048") + + (V1DF "riscv_vector::vls_mode_valid_p (V1DFmode) && TARGET_VECTOR_ELEN_F= P_64") + (V2DF "riscv_vector::vls_mode_valid_p (V2DFmode) && TARGET_VECTOR_ELEN_F= P_64") + (V4DF "riscv_vector::vls_mode_valid_p (V4DFmode) && TARGET_VECTOR_ELEN_F= P_64") + (V8DF "riscv_vector::vls_mode_valid_p (V8DFmode) && TARGET_VECTOR_ELEN_F= P_64 && TARGET_MIN_VLEN >=3D 64") + (V16DF "riscv_vector::vls_mode_valid_p (V16DFmode) && TARGET_VECTOR_ELEN= _FP_64 && TARGET_MIN_VLEN >=3D 128") + (V32DF "riscv_vector::vls_mode_valid_p (V32DFmode) && TARGET_VECTOR_ELEN= _FP_64 && TARGET_MIN_VLEN >=3D 256") + (V64DF "riscv_vector::vls_mode_valid_p (V64DFmode) && TARGET_VECTOR_ELEN= _FP_64 && TARGET_MIN_VLEN >=3D 512") + (V128DF "riscv_vector::vls_mode_valid_p (V128DFmode) && TARGET_VECTOR_EL= EN_FP_64 && TARGET_MIN_VLEN >=3D 1024") + (V256DF "riscv_vector::vls_mode_valid_p (V256DFmode) && TARGET_VECTOR_EL= EN_FP_64 && TARGET_MIN_VLEN >=3D 2048") + (V512DF "riscv_vector::vls_mode_valid_p (V512DFmode) && TARGET_VECTOR_EL= EN_FP_64 && TARGET_MIN_VLEN >=3D 4096") +]) + (define_mode_attr VDEMOTE [ (RVVM8DI "RVVM8SI") (RVVM4DI "RVVM4SI") (RVVM2DI "RVVM2SI") (RVVM1DI "RV= VM1SI") (V1DI "V1SI") -- 2.34.1 --_000_MW5PR11MB59082F8756F7B25CDC451AE3A9A5AMW5PR11MB5908namp_--