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From: "Li, Pan2" <>
To: Jeff Law <>,
	Juzhe-Zhong <>,
	"" <>
Cc: "" <>,
	"" <>,
	"" <>
Subject: RE: [PATCH] RISC-V: Refactor the integer ternary autovec pattern
Date: Sat, 24 Jun 2023 14:43:52 +0000	[thread overview]
Message-ID: <> (raw)
In-Reply-To: <>

Committed, thanks Jeff.


-----Original Message-----
From: Gcc-patches <> On Behalf Of Jeff Law via Gcc-patches
Sent: Saturday, June 24, 2023 10:04 PM
To: Juzhe-Zhong <>;
Subject: Re: [PATCH] RISC-V: Refactor the integer ternary autovec pattern

On 6/21/23 16:38, Juzhe-Zhong wrote:
> Long time ago, I encounter ICE when trying to set clobber register as Pmode
> and I forgot the reason.
> So, I clobber SI scratch and PUT_MODE to make it Pmode after reload which
> makes patterns look unreasonable.
> According to Jeff's comments, I tried it again, it works now when we try to
> set clobber register as Pmode and the patterns look more reasonable now.
> The tests are all passed, Ok for trunk.
> gcc/ChangeLog:
>          * config/riscv/ (*fma<mode>): set clobber to Pmode in expand stage.
>          (*fma<VI:mode><P:mode>): Ditto.
>          (*fnma<mode>): Ditto.
>          (*fnma<VI:mode><P:mode>): Ditto.

      reply	other threads:[~2023-06-24 14:44 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-21 22:38 Juzhe-Zhong
2023-06-24  1:32 ` 钟居哲
2023-06-24 14:03 ` Jeff Law
2023-06-24 14:43   ` Li, Pan2 [this message]

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