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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Thanks Juzhe, addressed conflict and passed RV32/RV64 tests with below PATC= H v2. https://gcc.gnu.org/pipermail/gcc-patches/2023-July/624723.html Pan From: juzhe.zhong@rivai.ai Sent: Tuesday, July 18, 2023 9:09 AM To: Li, Pan2 ; gcc-patches Cc: Li, Pan2 ; Wang, Yanzhang ;= kito.cheng Subject: Re: [PATCH v1] RISC-V: Fix RVV frm run test failure on RV32 LGTM ________________________________ juzhe.zhong@rivai.ai From: pan2.li Date: 2023-07-14 21:20 To: gcc-patches CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng Subject: [PATCH v1] RISC-V: Fix RVV frm run test failure on RV32 From: Pan Li > Refine the run test case to avoid interactive checking in RV32, by separating each checks in different functions. Signed-off-by: Pan Li > gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-frm-run-1.c: Fix failure on RV32. --- .../riscv/rvv/base/float-point-frm-run-1.c | 58 ++++++++++--------- 1 file changed, 31 insertions(+), 27 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.= c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c index 210c49c5e8d..1d90b4f50d9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c @@ -5,6 +5,24 @@ #include #include +#define DEFINE_TEST_FRM_FUNC(FRM) \ +vfloat32m1_t __attribute__ ((noinline)) \ +test_float_point_frm_run_##FRM (vfloat32m1_t op1, vfloat32m1_t op2, size_t= vl) \ +{ = \ + vfloat32m1_t result; = \ + = \ + set_frm (0); = \ + = \ + result =3D __riscv_vfadd_vv_f32m1_rm (op1, result, FRM, vl); = \ + = \ + assert_equal (FRM, get_frm (), "The value of frm should be " #FRM "."); = \ + = \ + return result; = \ +} + +#define CALL_TEST_FUNC(FRM, op1, op2, vl) \ + test_float_point_frm_run_##FRM (op1, op2, vl) + static int get_frm () { @@ -31,40 +49,22 @@ set_frm (int frm) ); } -static inline void +void __attribute__ ((noinline)) \ assert_equal (int a, int b, char *message) { if (a !=3D b) { - printf (message); + fprintf (stdout, message); + fflush (stdout); __builtin_abort (); } } -vfloat32m1_t __attribute__ ((noinline)) -test_float_point_frm_run (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) -{ - set_frm (0); - - vfloat32m1_t result; - - result =3D __riscv_vfadd_vv_f32m1_rm (op1, result, 1, vl); - assert_equal (1, get_frm (), "The value of frm register should be 1."); - - result =3D __riscv_vfadd_vv_f32m1_rm (op1, result, 2, vl); - assert_equal (2, get_frm (), "The value of frm register should be 2."); - - result =3D __riscv_vfadd_vv_f32m1_rm (op1, result, 3, vl); - assert_equal (3, get_frm (), "The value of frm register should be 3."); - - result =3D __riscv_vfadd_vv_f32m1_rm (op1, result, 4, vl); - assert_equal (4, get_frm (), "The value of frm register should be 4."); - - result =3D __riscv_vfadd_vv_f32m1_rm (op1, result, 0, vl); - assert_equal (0, get_frm (), "The value of frm register should be 0."); - - return result; -} +DEFINE_TEST_FRM_FUNC (0) +DEFINE_TEST_FRM_FUNC (1) +DEFINE_TEST_FRM_FUNC (2) +DEFINE_TEST_FRM_FUNC (3) +DEFINE_TEST_FRM_FUNC (4) int main () @@ -73,7 +73,11 @@ main () vfloat32m1_t op1; vfloat32m1_t op2; - test_float_point_frm_run (op1, op2, vl); + CALL_TEST_FUNC (0, op1, op2, vl); + CALL_TEST_FUNC (1, op1, op2, vl); + CALL_TEST_FUNC (2, op1, op2, vl); + CALL_TEST_FUNC (3, op1, op2, vl); + CALL_TEST_FUNC (4, op1, op2, vl); return 0; } -- 2.34.1 --_000_MW5PR11MB5908365F36DF09600802C372A938AMW5PR11MB5908namp_--