From: "Li, Pan2" <pan2.li@intel.com>
To: "juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai>,
gcc-patches <gcc-patches@gcc.gnu.org>
Cc: "Wang, Yanzhang" <yanzhang.wang@intel.com>,
kito.cheng <kito.cheng@gmail.com>
Subject: RE: [PATCH v1] RISC-V: Fix one incorrect match operand for RVV reduction
Date: Thu, 20 Jul 2023 08:40:24 +0000 [thread overview]
Message-ID: <MW5PR11MB59083906E48AE13329FA0D90A93EA@MW5PR11MB5908.namprd11.prod.outlook.com> (raw)
In-Reply-To: <FB2E8008DEE490FF+2023072016371893794123@rivai.ai>
[-- Attachment #1: Type: text/plain, Size: 4356 bytes --]
Committed, thanks Juzhe.
Pan
From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Thursday, July 20, 2023 4:37 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Li, Pan2 <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng <kito.cheng@gmail.com>
Subject: Re: [PATCH v1] RISC-V: Fix one incorrect match operand for RVV reduction
LGTM. You can commit it.
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: pan2.li<mailto:pan2.li@intel.com>
Date: 2023-07-20 16:35
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; pan2.li<mailto:pan2.li@intel.com>; yanzhang.wang<mailto:yanzhang.wang@intel.com>; kito.cheng<mailto:kito.cheng@gmail.com>
Subject: [PATCH v1] RISC-V: Fix one incorrect match operand for RVV reduction
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
There are 2 of the RVV reduction pattern mask operand takes
vector_merge_operand instead of vector_mask_operand by mistake. This
patch would like to fix this.
Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
gcc/ChangeLog:
* config/riscv/vector.md: Fix incorrect match_operand.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr110299-1.c: Adjust tests.
* gcc.target/riscv/rvv/base/pr110299-2.c: Ditto.
---
gcc/config/riscv/vector.md | 4 ++--
gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c | 4 ++--
gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c | 4 ++--
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index fcff3ee3a17..f745888127c 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7915,7 +7915,7 @@ (define_insn "@pred_widen_reduc_plus<order><VHF:mode><VSF_LMUL1:mode>"
(unspec:VSF_LMUL1
[(unspec:VSF_LMUL1
[(unspec:<VHF:VM>
- [(match_operand:<VHF:VM> 1 "vector_merge_operand" "vmWc1,vmWc1")
+ [(match_operand:<VHF:VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
(match_operand 5 "vector_length_operand" " rK, rK")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
@@ -7937,7 +7937,7 @@ (define_insn "@pred_widen_reduc_plus<order><VSF:mode><VDF_LMUL1:mode>"
(unspec:VDF_LMUL1
[(unspec:VDF_LMUL1
[(unspec:<VSF:VM>
- [(match_operand:<VSF:VM> 1 "vector_merge_operand" "vmWc1,vmWc1")
+ [(match_operand:<VSF:VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
(match_operand 5 "vector_length_operand" " rK, rK")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c
index d83eea925a7..a903dde34d1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c
@@ -3,5 +3,5 @@
#include "pr110299-1.h"
-/* { dg-final { scan-assembler-times {vfwredosum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
-/* { dg-final { scan-assembler-times {vfwredusum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vfwredosum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vfwredusum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c
index cdcde1b89a4..1254ace58eb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c
@@ -4,5 +4,5 @@
#include "pr110299-1.h"
#include "pr110299-2.h"
-/* { dg-final { scan-assembler-times {vfwredosum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 3 } } */
-/* { dg-final { scan-assembler-times {vfwredusum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 3 } } */
+/* { dg-final { scan-assembler-times {vfwredosum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 3 } } */
+/* { dg-final { scan-assembler-times {vfwredusum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 3 } } */
--
2.34.1
prev parent reply other threads:[~2023-07-20 8:40 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-20 8:35 pan2.li
2023-07-20 8:37 ` juzhe.zhong
2023-07-20 8:40 ` Li, Pan2 [this message]
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