From: "Li, Pan2" <pan2.li@intel.com>
To: Kito Cheng <kito.cheng@gmail.com>
Cc: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>,
"juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai>,
"kito.cheng@sifive.com" <kito.cheng@sifive.com>,
"Wang, Yanzhang" <yanzhang.wang@intel.com>
Subject: RE: [PATCH] RISC-V: Support RVV VREINTERPRET from vbool*_t to vuint*m1_t
Date: Wed, 24 May 2023 03:30:06 +0000 [thread overview]
Message-ID: <MW5PR11MB59083A33E488AFB8643C33C1A9419@MW5PR11MB5908.namprd11.prod.outlook.com> (raw)
In-Reply-To: <CA+yXCZCbuSzUSjFXd-f9qPsUO_T9tAAV0zgT+0Wysn79kTmynQ@mail.gmail.com>
Committed, thanks Kito.
Pan
-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com>
Sent: Wednesday, May 24, 2023 11:22 AM
To: Li, Pan2 <pan2.li@intel.com>
Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; kito.cheng@sifive.com; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: [PATCH] RISC-V: Support RVV VREINTERPRET from vbool*_t to vuint*m1_t
ok
On Thu, May 18, 2023 at 2:32 PM Pan Li via Gcc-patches <gcc-patches@gcc.gnu.org> wrote:
>
> From: Pan Li <pan2.li@intel.com>
>
> This patch support the RVV VREINTERPRET from the vbool*_t to the
> vuint*m1_t. Aka:
>
> vuint*m1_t __riscv_vreinterpret_x_x(vbool*_t);
>
> These APIs help the users to convert vector the vbool*_t to the LMUL=1
> unsigned integer vint*_t. According to the RVV intrinsic SPEC as
> below, the reinterpret intrinsics only change the types of the underlying contents.
>
> https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/master/rvv-int
> rinsic-rfc.md#reinterpret-vbool-o-vintm1
>
> For example, given below code.
> vuint8m1_t test_vreinterpret_v_b1_vuint8m1 (vbool1_t src) {
> return __riscv_vreinterpret_v_b1_u8m1 (src); }
>
> It will generate the assembly code similar as below:
> vsetvli a5,zero,e8,m8,ta,ma
> vlm.v v1,0(a1)
> vs1r.v v1,0(a0)
> ret
>
> Please NOTE the test files doesn't cover all the possible combinations
> of the intrinsic APIs introduced by this PATCH due to too many.
> This is the last PATCH for the reinterpret between the signed/unsigned
> and the bool vector types.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
>
> gcc/ChangeLog:
>
> * config/riscv/genrvv-type-indexer.cc (main): Add
> unsigned_eew*_lmul1_interpret for indexer.
> * config/riscv/riscv-vector-builtins-functions.def (vreinterpret):
> Register vuint*m1_t interpret function.
> * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_UNSIGNED_EEW8_LMUL1_INTERPRET_OPS):
> New macro for vuint8m1_t.
> (DEF_RVV_UNSIGNED_EEW16_LMUL1_INTERPRET_OPS): Likewise.
> (DEF_RVV_UNSIGNED_EEW32_LMUL1_INTERPRET_OPS): Likewise.
> (DEF_RVV_UNSIGNED_EEW64_LMUL1_INTERPRET_OPS): Likewise.
> (vbool1_t): Add to unsigned_eew*_interpret_ops.
> (vbool2_t): Likewise.
> (vbool4_t): Likewise.
> (vbool8_t): Likewise.
> (vbool16_t): Likewise.
> (vbool32_t): Likewise.
> (vbool64_t): Likewise.
> * config/riscv/riscv-vector-builtins.cc (DEF_RVV_UNSIGNED_EEW8_LMUL1_INTERPRET_OPS):
> New macro for vuint*m1_t.
> (DEF_RVV_UNSIGNED_EEW16_LMUL1_INTERPRET_OPS): Likewise.
> (DEF_RVV_UNSIGNED_EEW32_LMUL1_INTERPRET_OPS): Likewise.
> (DEF_RVV_UNSIGNED_EEW64_LMUL1_INTERPRET_OPS): Likewise.
> (required_extensions_p): Add vuint*m1_t interpret case.
> * config/riscv/riscv-vector-builtins.def (unsigned_eew8_lmul1_interpret):
> Add vuint*m1_t interpret to base type.
> (unsigned_eew16_lmul1_interpret): Likewise.
> (unsigned_eew32_lmul1_interpret): Likewise.
> (unsigned_eew64_lmul1_interpret): Likewise.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c:
> Enrich test cases.
> ---
> gcc/config/riscv/genrvv-type-indexer.cc | 12 ++++
> .../riscv/riscv-vector-builtins-functions.def | 4 ++
> .../riscv/riscv-vector-builtins-types.def | 64 +++++++++++++++++
> gcc/config/riscv/riscv-vector-builtins.cc | 70 +++++++++++++++++++
> gcc/config/riscv/riscv-vector-builtins.def | 6 ++
> .../rvv/base/misc_vreinterpret_vbool_vint.c | 20 +++++-
> 6 files changed, 174 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/config/riscv/genrvv-type-indexer.cc
> b/gcc/config/riscv/genrvv-type-indexer.cc
> index 5148abdda0f..18e1b375396 100644
> --- a/gcc/config/riscv/genrvv-type-indexer.cc
> +++ b/gcc/config/riscv/genrvv-type-indexer.cc
> @@ -229,6 +229,10 @@ main (int argc, const char **argv)
> fprintf (fp, " /*SIGNED_EEW%d_LMUL1_INTERPRET*/ %s,\n", eew,
> inttype (eew, LMUL1_LOG2, /* unsigned_p
> */false).c_str ());
>
> + for (unsigned eew : EEW_SIZE_LIST)
> + fprintf (fp, " /*UNSIGNED_EEW%d_LMUL1_INTERPRET*/ %s,\n", eew,
> + inttype (eew, LMUL1_LOG2, /* unsigned_p */true).c_str
> + ());
> +
> for (unsigned lmul_log2_offset : {1, 2, 3, 4, 5, 6})
> {
> unsigned multiple_of_lmul = 1 << lmul_log2_offset; @@ -322,6
> +326,10 @@ main (int argc, const char **argv)
> fprintf (fp, " /*SIGNED_EEW%d_LMUL1_INTERPRET*/ INVALID,\n",
> eew);
>
> + for (unsigned eew : EEW_SIZE_LIST)
> + fprintf (fp, " /*UNSIGNED_EEW%d_LMUL1_INTERPRET*/ INVALID,\n",
> + eew);
> +
> for (unsigned lmul_log2_offset : {1, 2, 3, 4, 5, 6})
> {
> unsigned multiple_of_lmul = 1 << lmul_log2_offset; @@
> -387,6 +395,10 @@ main (int argc, const char **argv)
> for (unsigned eew : EEW_SIZE_LIST)
> fprintf (fp, " /*SIGNED_EEW%d_LMUL1_INTERPRET*/
> INVALID,\n", eew);
>
> + for (unsigned eew : EEW_SIZE_LIST)
> + fprintf (fp, " /*UNSIGNED_EEW%d_LMUL1_INTERPRET*/ INVALID,\n",
> + eew);
> +
> for (unsigned lmul_log2_offset : {1, 2, 3, 4, 5, 6})
> {
> unsigned multiple_of_lmul = 1 << lmul_log2_offset; diff
> --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
> b/gcc/config/riscv/riscv-vector-builtins-functions.def
> index 98d59294aae..89aff27bf26 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-functions.def
> +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
> @@ -519,6 +519,10 @@ DEF_RVV_FUNCTION (vreinterpret, misc, none_preds,
> b_v_signed_eew8_lmul1_interpre DEF_RVV_FUNCTION (vreinterpret, misc,
> none_preds, b_v_signed_eew16_lmul1_interpret_ops)
> DEF_RVV_FUNCTION (vreinterpret, misc, none_preds,
> b_v_signed_eew32_lmul1_interpret_ops)
> DEF_RVV_FUNCTION (vreinterpret, misc, none_preds,
> b_v_signed_eew64_lmul1_interpret_ops)
> +DEF_RVV_FUNCTION (vreinterpret, misc, none_preds,
> +b_v_unsigned_eew8_lmul1_interpret_ops)
> +DEF_RVV_FUNCTION (vreinterpret, misc, none_preds,
> +b_v_unsigned_eew16_lmul1_interpret_ops)
> +DEF_RVV_FUNCTION (vreinterpret, misc, none_preds,
> +b_v_unsigned_eew32_lmul1_interpret_ops)
> +DEF_RVV_FUNCTION (vreinterpret, misc, none_preds,
> +b_v_unsigned_eew64_lmul1_interpret_ops)
> DEF_RVV_FUNCTION (vlmul_ext, misc, none_preds,
> all_v_vlmul_ext_x2_ops) DEF_RVV_FUNCTION (vlmul_ext, misc,
> none_preds, all_v_vlmul_ext_x4_ops) DEF_RVV_FUNCTION (vlmul_ext,
> misc, none_preds, all_v_vlmul_ext_x8_ops) diff --git
> a/gcc/config/riscv/riscv-vector-builtins-types.def
> b/gcc/config/riscv/riscv-vector-builtins-types.def
> index 7b917094851..f7f650f7e95 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-types.def
> +++ b/gcc/config/riscv/riscv-vector-builtins-types.def
> @@ -251,6 +251,34 @@ along with GCC; see the file COPYING3. If not see
> #define DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS(TYPE, REQUIRE)
> #endif
>
> +/* Use "DEF_RVV_UNSIGNED_EEW8_LMUL1_INTERPRET_OPS" macro include all types for
> + UINT8M1 vinterpret which will be iterated and registered as intrinsic
> + functions. */
> +#ifndef DEF_RVV_UNSIGNED_EEW8_LMUL1_INTERPRET_OPS
> +#define DEF_RVV_UNSIGNED_EEW8_LMUL1_INTERPRET_OPS(TYPE, REQUIRE)
> +#endif
> +
> +/* Use "DEF_RVV_UNSIGNED_EEW16_LMUL1_INTERPRET_OPS" macro include all types for
> + UINT16M1 vinterpret which will be iterated and registered as intrinsic
> + functions. */
> +#ifndef DEF_RVV_UNSIGNED_EEW16_LMUL1_INTERPRET_OPS
> +#define DEF_RVV_UNSIGNED_EEW16_LMUL1_INTERPRET_OPS(TYPE, REQUIRE)
> +#endif
> +
> +/* Use "DEF_RVV_UNSIGNED_EEW32_LMUL1_INTERPRET_OPS" macro include all types for
> + UINT32M1 vinterpret which will be iterated and registered as intrinsic
> + functions. */
> +#ifndef DEF_RVV_UNSIGNED_EEW32_LMUL1_INTERPRET_OPS
> +#define DEF_RVV_UNSIGNED_EEW32_LMUL1_INTERPRET_OPS(TYPE, REQUIRE)
> +#endif
> +
> +/* Use "DEF_RVV_UNSIGNED_EEW64_LMUL1_INTERPRET_OPS" macro include all types for
> + UINT64M1 vinterpret which will be iterated and registered as intrinsic
> + functions. */
> +#ifndef DEF_RVV_UNSIGNED_EEW64_LMUL1_INTERPRET_OPS
> +#define DEF_RVV_UNSIGNED_EEW64_LMUL1_INTERPRET_OPS(TYPE, REQUIRE)
> +#endif
> +
> /* Use "DEF_RVV_X2_VLMUL_EXT_OPS" macro include all types for X2 VLMUL EXT
> which will be iterated and registered as intrinsic functions. */
> #ifndef DEF_RVV_X2_VLMUL_EXT_OPS @@ -830,6 +858,38 @@
> DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS(vbool16_t, 0)
> DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS(vbool32_t, 0)
> DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS(vbool64_t,
> RVV_REQUIRE_ELEN_64)
>
> +DEF_RVV_UNSIGNED_EEW8_LMUL1_INTERPRET_OPS(vbool1_t, 0)
> +DEF_RVV_UNSIGNED_EEW8_LMUL1_INTERPRET_OPS(vbool2_t, 0)
> +DEF_RVV_UNSIGNED_EEW8_LMUL1_INTERPRET_OPS(vbool4_t, 0)
> +DEF_RVV_UNSIGNED_EEW8_LMUL1_INTERPRET_OPS(vbool8_t, 0)
> +DEF_RVV_UNSIGNED_EEW8_LMUL1_INTERPRET_OPS(vbool16_t, 0)
> +DEF_RVV_UNSIGNED_EEW8_LMUL1_INTERPRET_OPS(vbool32_t, 0)
> +DEF_RVV_UNSIGNED_EEW8_LMUL1_INTERPRET_OPS(vbool64_t,
> +RVV_REQUIRE_ELEN_64)
> +
> +DEF_RVV_UNSIGNED_EEW16_LMUL1_INTERPRET_OPS(vbool1_t, 0)
> +DEF_RVV_UNSIGNED_EEW16_LMUL1_INTERPRET_OPS(vbool2_t, 0)
> +DEF_RVV_UNSIGNED_EEW16_LMUL1_INTERPRET_OPS(vbool4_t, 0)
> +DEF_RVV_UNSIGNED_EEW16_LMUL1_INTERPRET_OPS(vbool8_t, 0)
> +DEF_RVV_UNSIGNED_EEW16_LMUL1_INTERPRET_OPS(vbool16_t, 0)
> +DEF_RVV_UNSIGNED_EEW16_LMUL1_INTERPRET_OPS(vbool32_t, 0)
> +DEF_RVV_UNSIGNED_EEW16_LMUL1_INTERPRET_OPS(vbool64_t,
> +RVV_REQUIRE_ELEN_64)
> +
> +DEF_RVV_UNSIGNED_EEW32_LMUL1_INTERPRET_OPS(vbool1_t, 0)
> +DEF_RVV_UNSIGNED_EEW32_LMUL1_INTERPRET_OPS(vbool2_t, 0)
> +DEF_RVV_UNSIGNED_EEW32_LMUL1_INTERPRET_OPS(vbool4_t, 0)
> +DEF_RVV_UNSIGNED_EEW32_LMUL1_INTERPRET_OPS(vbool8_t, 0)
> +DEF_RVV_UNSIGNED_EEW32_LMUL1_INTERPRET_OPS(vbool16_t, 0)
> +DEF_RVV_UNSIGNED_EEW32_LMUL1_INTERPRET_OPS(vbool32_t, 0)
> +DEF_RVV_UNSIGNED_EEW32_LMUL1_INTERPRET_OPS(vbool64_t,
> +RVV_REQUIRE_ELEN_64)
> +
> +DEF_RVV_UNSIGNED_EEW64_LMUL1_INTERPRET_OPS(vbool1_t, 0)
> +DEF_RVV_UNSIGNED_EEW64_LMUL1_INTERPRET_OPS(vbool2_t, 0)
> +DEF_RVV_UNSIGNED_EEW64_LMUL1_INTERPRET_OPS(vbool4_t, 0)
> +DEF_RVV_UNSIGNED_EEW64_LMUL1_INTERPRET_OPS(vbool8_t, 0)
> +DEF_RVV_UNSIGNED_EEW64_LMUL1_INTERPRET_OPS(vbool16_t, 0)
> +DEF_RVV_UNSIGNED_EEW64_LMUL1_INTERPRET_OPS(vbool32_t, 0)
> +DEF_RVV_UNSIGNED_EEW64_LMUL1_INTERPRET_OPS(vbool64_t,
> +RVV_REQUIRE_ELEN_64)
> +
> DEF_RVV_X2_VLMUL_EXT_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
> DEF_RVV_X2_VLMUL_EXT_OPS (vint8mf4_t, 0) DEF_RVV_X2_VLMUL_EXT_OPS
> (vint8mf2_t, 0) @@ -1228,6 +1288,10 @@ DEF_RVV_TUPLE_OPS
> (vfloat64m4x2_t, RVV_REQUIRE_ELEN_FP_64) #undef
> DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS
> #undef DEF_RVV_SIGNED_EEW32_LMUL1_INTERPRET_OPS
> #undef DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS
> +#undef DEF_RVV_UNSIGNED_EEW8_LMUL1_INTERPRET_OPS
> +#undef DEF_RVV_UNSIGNED_EEW16_LMUL1_INTERPRET_OPS
> +#undef DEF_RVV_UNSIGNED_EEW32_LMUL1_INTERPRET_OPS
> +#undef DEF_RVV_UNSIGNED_EEW64_LMUL1_INTERPRET_OPS
> #undef DEF_RVV_X2_VLMUL_EXT_OPS
> #undef DEF_RVV_X4_VLMUL_EXT_OPS
> #undef DEF_RVV_X8_VLMUL_EXT_OPS
> diff --git a/gcc/config/riscv/riscv-vector-builtins.cc
> b/gcc/config/riscv/riscv-vector-builtins.cc
> index 1614483c06c..ec1c3158ceb 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins.cc
> @@ -401,6 +401,34 @@ static const rvv_type_info
> signed_eew64_lmul1_interpret_ops[] = { #include "riscv-vector-builtins-types.def"
> {NUM_VECTOR_TYPES, 0}};
>
> +/* A list of vuint8m1 interpret will be registered for intrinsic
> +functions. */ static const rvv_type_info unsigned_eew8_lmul1_interpret_ops[] = {
> +#define DEF_RVV_UNSIGNED_EEW8_LMUL1_INTERPRET_OPS(TYPE, REQUIRE) \
> + {VECTOR_TYPE_##TYPE, REQUIRE},
> +#include "riscv-vector-builtins-types.def"
> + {NUM_VECTOR_TYPES, 0}};
> +
> +/* A list of vuint16m1 interpret will be registered for intrinsic
> +functions. */ static const rvv_type_info unsigned_eew16_lmul1_interpret_ops[] = {
> +#define DEF_RVV_UNSIGNED_EEW16_LMUL1_INTERPRET_OPS(TYPE, REQUIRE) \
> + {VECTOR_TYPE_##TYPE, REQUIRE},
> +#include "riscv-vector-builtins-types.def"
> + {NUM_VECTOR_TYPES, 0}};
> +
> +/* A list of vuint32m1 interpret will be registered for intrinsic
> +functions. */ static const rvv_type_info unsigned_eew32_lmul1_interpret_ops[] = {
> +#define DEF_RVV_UNSIGNED_EEW32_LMUL1_INTERPRET_OPS(TYPE, REQUIRE) \
> + {VECTOR_TYPE_##TYPE, REQUIRE},
> +#include "riscv-vector-builtins-types.def"
> + {NUM_VECTOR_TYPES, 0}};
> +
> +/* A list of vuint64m1 interpret will be registered for intrinsic
> +functions. */ static const rvv_type_info unsigned_eew64_lmul1_interpret_ops[] = {
> +#define DEF_RVV_UNSIGNED_EEW64_LMUL1_INTERPRET_OPS(TYPE, REQUIRE) \
> + {VECTOR_TYPE_##TYPE, REQUIRE},
> +#include "riscv-vector-builtins-types.def"
> + {NUM_VECTOR_TYPES, 0}};
> +
> /* A list of x2 vlmul ext will be registered for intrinsic functions.
> */ static const rvv_type_info vlmul_ext_x2_ops[] = { #define
> DEF_RVV_X2_VLMUL_EXT_OPS(TYPE, REQUIRE) {VECTOR_TYPE_##TYPE, REQUIRE},
> @@ -1761,6 +1789,38 @@ static CONSTEXPR const rvv_op_info b_v_signed_eew64_lmul1_interpret_ops
> rvv_arg_type_info (RVV_BASE_signed_eew64_lmul1_interpret),/* Return type */
> v_args /* Args */};
>
> +/* A static operand information for vuint8_t func (vector_type)
> + * function registration. */
> +static CONSTEXPR const rvv_op_info b_v_unsigned_eew8_lmul1_interpret_ops
> + = {unsigned_eew8_lmul1_interpret_ops, /* Types */
> + OP_TYPE_v, /* Suffix */
> + rvv_arg_type_info (RVV_BASE_unsigned_eew8_lmul1_interpret),/* Return type */
> + v_args /* Args */};
> +
> +/* A static operand information for vuint16_t func (vector_type)
> + * function registration. */
> +static CONSTEXPR const rvv_op_info b_v_unsigned_eew16_lmul1_interpret_ops
> + = {unsigned_eew16_lmul1_interpret_ops, /* Types */
> + OP_TYPE_v, /* Suffix */
> + rvv_arg_type_info (RVV_BASE_unsigned_eew16_lmul1_interpret),/* Return type */
> + v_args /* Args */};
> +
> +/* A static operand information for vuint32_t func (vector_type)
> + * function registration. */
> +static CONSTEXPR const rvv_op_info b_v_unsigned_eew32_lmul1_interpret_ops
> + = {unsigned_eew32_lmul1_interpret_ops, /* Types */
> + OP_TYPE_v, /* Suffix */
> + rvv_arg_type_info (RVV_BASE_unsigned_eew32_lmul1_interpret),/* Return type */
> + v_args /* Args */};
> +
> +/* A static operand information for vuint64_t func (vector_type)
> + * function registration. */
> +static CONSTEXPR const rvv_op_info b_v_unsigned_eew64_lmul1_interpret_ops
> + = {unsigned_eew64_lmul1_interpret_ops, /* Types */
> + OP_TYPE_v, /* Suffix */
> + rvv_arg_type_info (RVV_BASE_unsigned_eew64_lmul1_interpret),/* Return type */
> + v_args /* Args */};
> +
> /* A static operand information for vector_type func (vector_type)
> * function registration. */
> static CONSTEXPR const rvv_op_info all_v_vlmul_ext_x2_ops @@ -2451,6
> +2511,8 @@ static CONSTEXPR const function_type_info function_types[] = {
> BOOL16_INTERPRET, BOOL32_INTERPRET, BOOL64_INTERPRET, \
> SIGNED_EEW8_LMUL1_INTERPRET, SIGNED_EEW16_LMUL1_INTERPRET, \
> SIGNED_EEW32_LMUL1_INTERPRET, SIGNED_EEW64_LMUL1_INTERPRET, \
> + UNSIGNED_EEW8_LMUL1_INTERPRET, UNSIGNED_EEW16_LMUL1_INTERPRET, \
> + UNSIGNED_EEW32_LMUL1_INTERPRET, UNSIGNED_EEW64_LMUL1_INTERPRET, \
> X2_VLMUL_EXT, X4_VLMUL_EXT, X8_VLMUL_EXT, X16_VLMUL_EXT, X32_VLMUL_EXT, \
> X64_VLMUL_EXT, TUPLE_SUBPART) \
> { \
> @@ -2499,6 +2561,10 @@ static CONSTEXPR const function_type_info function_types[] = {
> VECTOR_TYPE_##SIGNED_EEW16_LMUL1_INTERPRET, \
> VECTOR_TYPE_##SIGNED_EEW32_LMUL1_INTERPRET, \
> VECTOR_TYPE_##SIGNED_EEW64_LMUL1_INTERPRET, \
> + VECTOR_TYPE_##UNSIGNED_EEW8_LMUL1_INTERPRET, \
> + VECTOR_TYPE_##UNSIGNED_EEW16_LMUL1_INTERPRET, \
> + VECTOR_TYPE_##UNSIGNED_EEW32_LMUL1_INTERPRET, \
> + VECTOR_TYPE_##UNSIGNED_EEW64_LMUL1_INTERPRET, \
> VECTOR_TYPE_##X2_VLMUL_EXT, \
> VECTOR_TYPE_##X4_VLMUL_EXT, \
> VECTOR_TYPE_##X8_VLMUL_EXT, \
> @@ -2811,6 +2877,10 @@ required_extensions_p (enum rvv_base_type type)
> case RVV_BASE_signed_eew16_lmul1_interpret:
> case RVV_BASE_signed_eew32_lmul1_interpret:
> case RVV_BASE_signed_eew64_lmul1_interpret:
> + case RVV_BASE_unsigned_eew8_lmul1_interpret:
> + case RVV_BASE_unsigned_eew16_lmul1_interpret:
> + case RVV_BASE_unsigned_eew32_lmul1_interpret:
> + case RVV_BASE_unsigned_eew64_lmul1_interpret:
> case RVV_BASE_vlmul_ext_x2:
> case RVV_BASE_vlmul_ext_x4:
> case RVV_BASE_vlmul_ext_x8:
> diff --git a/gcc/config/riscv/riscv-vector-builtins.def
> b/gcc/config/riscv/riscv-vector-builtins.def
> index 9137a364f6e..57da2919656 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.def
> +++ b/gcc/config/riscv/riscv-vector-builtins.def
> @@ -83,6 +83,8 @@ along with GCC; see the file COPYING3. If not see
> BOOL16_INTERPRET, BOOL32_INTERPRET, BOOL64_INTERPRET, \
> SIGNED_EEW8_LMUL1_INTERPRET, SIGNED_EEW16_LMUL1_INTERPRET, \
> SIGNED_EEW32_LMUL1_INTERPRET, SIGNED_EEW64_LMUL1_INTERPRET, \
> + UNSIGNED_EEW8_LMUL1_INTERPRET, UNSIGNED_EEW16_LMUL1_INTERPRET, \
> + UNSIGNED_EEW32_LMUL1_INTERPRET, UNSIGNED_EEW64_LMUL1_INTERPRET, \
> X2_VLMUL_EXT, X4_VLMUL_EXT, X8_VLMUL_EXT, X16_VLMUL_EXT, X32_VLMUL_EXT, \
> X64_VLMUL_EXT, TUPLE_SUBPART)
> #endif
> @@ -649,6 +651,10 @@ DEF_RVV_BASE_TYPE (signed_eew8_lmul1_interpret,
> get_vector_type (type_idx)) DEF_RVV_BASE_TYPE
> (signed_eew16_lmul1_interpret, get_vector_type (type_idx))
> DEF_RVV_BASE_TYPE (signed_eew32_lmul1_interpret, get_vector_type
> (type_idx)) DEF_RVV_BASE_TYPE (signed_eew64_lmul1_interpret,
> get_vector_type (type_idx))
> +DEF_RVV_BASE_TYPE (unsigned_eew8_lmul1_interpret, get_vector_type
> +(type_idx)) DEF_RVV_BASE_TYPE (unsigned_eew16_lmul1_interpret,
> +get_vector_type (type_idx)) DEF_RVV_BASE_TYPE
> +(unsigned_eew32_lmul1_interpret, get_vector_type (type_idx))
> +DEF_RVV_BASE_TYPE (unsigned_eew64_lmul1_interpret, get_vector_type
> +(type_idx))
> DEF_RVV_BASE_TYPE (vlmul_ext_x2, get_vector_type (type_idx))
> DEF_RVV_BASE_TYPE (vlmul_ext_x4, get_vector_type (type_idx))
> DEF_RVV_BASE_TYPE (vlmul_ext_x8, get_vector_type (type_idx)) diff
> --git
> a/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint
> .c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint
> .c
> index 9b03726b63a..9563c8d27fa 100644
> ---
> a/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint
> .c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_
> +++ vint.c
> @@ -98,6 +98,22 @@ vint64m1_t test_vreinterpret_v_b1_vint64m1 (vbool1_t src) {
> return __riscv_vreinterpret_v_b1_i64m1 (src); }
>
> -/* { dg-final { scan-assembler-times
> {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 24 } } */
> +vuint8m1_t test_vreinterpret_v_b1_vuint8m1 (vbool1_t src) {
> + return __riscv_vreinterpret_v_b1_u8m1 (src); }
> +
> +vuint16m1_t test_vreinterpret_v_b1_vuint16m1 (vbool1_t src) {
> + return __riscv_vreinterpret_v_b1_u16m1 (src); }
> +
> +vuint32m1_t test_vreinterpret_v_b1_vuint32m1 (vbool1_t src) {
> + return __riscv_vreinterpret_v_b1_u32m1 (src); }
> +
> +vuint64m1_t test_vreinterpret_v_b1_vuint64m1 (vbool1_t src) {
> + return __riscv_vreinterpret_v_b1_u64m1 (src); }
> +
> +/* { dg-final { scan-assembler-times
> +{vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 28 } } */
> /* { dg-final { scan-assembler-times
> {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 20 } } */
> -/* { dg-final { scan-assembler-times
> {vs1r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 4 } } */
> +/* { dg-final { scan-assembler-times
> +{vs1r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 8 } } */
> --
> 2.34.1
>
prev parent reply other threads:[~2023-05-24 3:30 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-18 6:32 pan2.li
2023-05-24 3:21 ` Kito Cheng
2023-05-24 3:30 ` Li, Pan2 [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=MW5PR11MB59083A33E488AFB8643C33C1A9419@MW5PR11MB5908.namprd11.prod.outlook.com \
--to=pan2.li@intel.com \
--cc=gcc-patches@gcc.gnu.org \
--cc=juzhe.zhong@rivai.ai \
--cc=kito.cheng@gmail.com \
--cc=kito.cheng@sifive.com \
--cc=yanzhang.wang@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).