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* [PATCH v1] RISC-V: Fix one bug for floating-point static frm
@ 2023-07-04  5:50 pan2.li
  2023-07-04  5:52 ` juzhe.zhong
  2023-07-04 14:05 ` [PATCH v3] " pan2.li
  0 siblings, 2 replies; 19+ messages in thread
From: pan2.li @ 2023-07-04  5:50 UTC (permalink / raw)
  To: gcc-patches
  Cc: juzhe.zhong, rdapp.gcc, jeffreyalaw, pan2.li, yanzhang.wang, kito.cheng

From: Pan Li <pan2.li@intel.com>

This patch would like to fix one bug to align below items of spec.

1. By default, the RVV floating-point will take dyn mode.
2. DYN is invalid in FRM register for RVV floating-point.

When mode switching the function entry and exit, it will take DYN as
the frm mode.

Signed-off-by: Pan Li <pan2.li@intel.com>

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_emit_mode_set): Avoid emit insn
	when FRM_MODE_DYN.
	(riscv_mode_entry): Take FRM_MODE_DYN as entry mode.
	(riscv_mode_exit): Likewise for exit mode.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/float-point-frm-insert-6.c: New test.
---
 gcc/config/riscv/riscv.cc                     |  6 ++--
 .../riscv/rvv/base/float-point-frm-insert-6.c | 31 +++++++++++++++++++
 2 files changed, 34 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index e4dc8115e69..f5fe910426e 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7670,7 +7670,7 @@ riscv_emit_mode_set (int entity, int mode, int prev_mode,
 	emit_insn (gen_vxrmsi (gen_int_mode (mode, SImode)));
       break;
     case RISCV_FRM:
-      if (mode != FRM_MODE_NONE && mode != prev_mode)
+      if (mode != FRM_MODE_DYN && mode != prev_mode)
 	{
 	  rtx scaler = gen_reg_rtx (SImode);
 	  rtx imm = gen_int_mode (mode, SImode);
@@ -7774,7 +7774,7 @@ riscv_mode_entry (int entity)
     case RISCV_VXRM:
       return VXRM_MODE_NONE;
     case RISCV_FRM:
-      return FRM_MODE_NONE;
+      return FRM_MODE_DYN;
     default:
       gcc_unreachable ();
     }
@@ -7791,7 +7791,7 @@ riscv_mode_exit (int entity)
     case RISCV_VXRM:
       return VXRM_MODE_NONE;
     case RISCV_FRM:
-      return FRM_MODE_NONE;
+      return FRM_MODE_DYN;
     default:
       gcc_unreachable ();
     }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c
new file mode 100644
index 00000000000..6d896e0953e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat32m1_t
+test_riscv_vfadd_vv_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
+  return __riscv_vfadd_vv_f32m1_rm (op1, op2, 7, vl);
+}
+
+vfloat32m1_t
+test_vfadd_vv_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2,
+			 size_t vl) {
+  return __riscv_vfadd_vv_f32m1_m_rm(mask, op1, op2, 7, vl);
+}
+
+vfloat32m1_t
+test_vfadd_vf_f32m1_rm(vfloat32m1_t op1, float32_t op2, size_t vl) {
+  return __riscv_vfadd_vf_f32m1_rm(op1, op2, 7, vl);
+}
+
+vfloat32m1_t
+test_vfadd_vf_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, float32_t op2,
+			 size_t vl) {
+  return __riscv_vfadd_vf_f32m1_m_rm(mask, op1, op2, 7, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */
+/* { dg-final { scan-assembler-not {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} } } */
-- 
2.34.1


^ permalink raw reply	[flat|nested] 19+ messages in thread
end of thread, other threads:[~2023-07-07  0:40 UTC | newest]

Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
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     [not found] <Message-Id: <20230704055053.2308713-1-pan2.li@intel.com>
2023-07-04  8:08 ` [PATCH v2] RISC-V: Fix one bug for floating-point static frm pan2.li
2023-07-04  8:53   ` juzhe.zhong
2023-07-04 12:52   ` Robin Dapp
2023-07-04 13:16     ` Li, Pan2
2023-07-05  7:02 ` [PATCH v4] " pan2.li
2023-07-05  7:10   ` Kito Cheng
2023-07-05  7:11     ` Robin Dapp
2023-07-05  7:13       ` Kito Cheng
2023-07-05  7:15       ` Li, Pan2
2023-07-05  8:03   ` Robin Dapp
2023-07-05  9:51     ` Li, Pan2
2023-07-06  5:26 ` [PATCH v5] " pan2.li
2023-07-06 15:30   ` Robin Dapp
2023-07-07  0:40     ` Li, Pan2
2023-07-04  5:50 [PATCH v1] " pan2.li
2023-07-04  5:52 ` juzhe.zhong
2023-07-04  6:50   ` Li, Pan2
2023-07-04  8:09     ` Li, Pan2
2023-07-04 14:05 ` [PATCH v3] " pan2.li

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