Thanks Juzhe and Jeff for suggestion. The approach like emit_insn_before_noloc will result in below ICE here.

../../../.././gcc/libstdc++-v3/libsupc++/new_opant.cc:42:1: error: flow control insn inside a basic block.
../../../.././gcc/libstdc++-v3/libsupc++/new_opant.cc:42:1: internal compiler error: in rtl_verify_bb_insns, at cfgrtl.cc:2796

Then I tried below approach but also have ICE like below.

../../../.././gcc/libstdc++-v3/libsupc++/eh_personality.cc:805:1: internal compiler error: in insert_insn_on_edge, at cfgrtl.cc:1976.

The insert_insn_end_basic_block have some special handling when end bb is CALL.

Pan

From: 钟居哲 <juzhe.zhong@rivai.ai>
Sent: Thursday, July 27, 2023 6:56 AM
To: Jeff Law <jeffreyalaw@gmail.com>; rdapp.gcc <rdapp.gcc@gmail.com>; kito.cheng <kito.cheng@sifive.com>; Li, Pan2 <pan2.li@intel.com>
Cc: gcc-patches <gcc-patches@gcc.gnu.org>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: Re: [PATCH v7] RISC-V: Support CALL for RVV floating-point dynamic rounding

Thanks Jeff.

Hi, Pan:
Plz try (insert edge and put 'frrm' on that edge) instead of insert end of block to see whether it works
(I have tried onece but I don't remember what happens).

Try that with following codes:
edge eg;
edge_iterator ei;
FOR_EACH_EDGE (eg, ei, bb->succs)
{
  start_sequence ();
   emit_insn (gen_frrmsi (DYNAMIC_FRM_RTL (cfun)));
   rtx_insn *backup_insn = get_insns ();
  end_sequence ();
  insert_insn_on_edge (backup_insn, eg);
}

to see how's going.

Not sure whether it is correct, Jeff could comments on that.

Thanks.
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>

From: Jeff Law<mailto:jeffreyalaw@gmail.com>
Date: 2023-07-27 06:46
To: 钟居哲<mailto:juzhe.zhong@rivai.ai>; rdapp.gcc<mailto:rdapp.gcc@gmail.com>; kito.cheng<mailto:kito.cheng@sifive.com>; pan2.li<mailto:pan2.li@intel.com>
CC: gcc-patches<mailto:gcc-patches@gcc.gnu.org>; yanzhang.wang<mailto:yanzhang.wang@intel.com>
Subject: Re: [PATCH v7] RISC-V: Support CALL for RVV floating-point dynamic rounding


On 7/26/23 16:21, 钟居哲 wrote:
> Hi, Jeff.
>
> insert_insn_end_basic_block is to handle this following case:
>
> bb 1:
> ...
> CALL.---->BB_END of bb
> bb 2:
> vfadd rne
>
> You can see there is no instructions after CALL.
>
> So you we use insert_insn_end_basic_block insert a "frrm" at the end of
> the bb 1.
>
> I know typically it's better to insert a edge between bb 1 and bb 2,
> then put "frrm" in that edgen.
> However, it causes ICE.
We'd need to know the reason for the ICE.

>
> If we really need to follow this approach, it seems that we need to
> modify the "mode_sw" PASS?
> Currently, we are avoiding changing the codes of PASS.
Generally wise, but sometimes we do need to change generic bits.  Let's
dive a bit into this.

We have more freedom here to loosen the profitability constraints since
its a target specific pass, but let's at least understand the what's
going on with the ICE, then make some decisions about the best way forward.

jeff