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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Thanks Juzhe, Just passed the RV64 riscv/rvv.exp but meet some failures in = RV32 the same as upstream. However, this patch may not introduce new failur= es but I am not quite sure if there is risk here. lowlist `find build-gcc-newlib-stage2/gcc/testsuite/ -name *.sum |paste -sd= "," -` =3D=3D=3D gcc: Unexpected fails for rv32imafdcv ilp32f medl= ow =3D=3D=3D FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c executio= n test FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c executio= n test FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c executio= n test FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c executio= n test FAIL: gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c -std=3Dc99 -O= 3 -ftree-vectorize --param riscv-autovec-preference=3Dfixed-vlmax (test for= excess errors) FAIL: gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c -std=3Dc99 -O3 = -ftree-vectorize --param riscv-autovec-preference=3Dfixed-vlmax execution t= est FAIL: gcc.target/riscv/rvv/autovec/vmv-imm-run.c -O3 -ftree-vectorize (test= for excess errors) =3D=3D=3D g++: Unexpected fails for rv32imafdcv ilp32f medl= ow =3D=3D=3D FAIL: g++.target/riscv/rvv/base/bug-14.C (test for excess errors) FAIL: g++.target/riscv/rvv/base/bug-9.C (test for excess errors) =3D=3D=3D=3D=3D=3D=3D=3D=3D Summary of gcc testsuite =3D=3D= =3D=3D=3D=3D=3D=3D=3D | # of unexpected case / # of unique unexpected= case | gcc | g++ | gfortran | rv32imafdcv/ ilp32f/ medlow | 7 / 4 | 2 / 2 | - | For RV32, mostly I take below commands for testing. cd riscv-gnu-toolchain cd gcc && git checkout master && git pull -p && cd - cd spike && git checkout master && git pull -p && cd - cd pk && git checkout master && git pull -p && cd - ./configure --prefix=3D`pwd`/__RISC-V_INSTALL_/ --with-arch=3Drv32imafdcv -= -with-abi=3Dilp32f --with-isa-spec=3D20191213 --with-sim=3Dspike make -j $(nproc) build-sim SIM=3Dspike make report -j $(nproc) RUNTESTFLAGS=3D"rvv.exp" Pan From: juzhe.zhong@rivai.ai Sent: Wednesday, June 14, 2023 10:31 AM To: Li, Pan2 ; gcc-patches Cc: Robin Dapp ; jeffreyalaw ; = Li, Pan2 ; Wang, Yanzhang ; kit= o.cheng Subject: Re: [PATCH v1] RISC-V: Align the predictor style for define_insn_a= nd_split LGTM. ________________________________ juzhe.zhong@rivai.ai From: pan2.li Date: 2023-06-14 10:15 To: gcc-patches CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng Subject: [PATCH v1] RISC-V: Align the predictor style for define_insn_and_s= plit From: Pan Li > This patch is considered as the follow up of the below PATCH. https://gcc.gnu.org/pipermail/gcc-patches/2023-June/621347.html We aligned the predictor style for the define_insn_and_split suggested by Kito. To avoid potential issues before we hit. Signed-off-by: Pan Li > gcc/ChangeLog: * config/riscv/autovec-opt.md: Align the predictor sytle. * config/riscv/autovec.md: Ditto. --- gcc/config/riscv/autovec-opt.md | 20 ++++++++++---------- gcc/config/riscv/autovec.md | 24 ++++++++++++------------ 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt= .md index aef28e445e1..fb1b07205aa 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -37,9 +37,9 @@ (define_insn_and_split "@pred_single_widen_mul" (match_operand: 4 "register_operand" " vr, vr")) (match_operand:VWEXTI 3 "register_operand" " vr, vr")) (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { insn_code icode =3D code_for_pred_vf2 (, mode); @@ -132,9 +132,9 @@ (define_insn_and_split "*not" (bitmanip_bitwise:VB (not:VB (match_operand:VB 2 "register_operand" " vr")) (match_operand:VB 1 "register_operand" " vr")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { insn_code icode =3D code_for_pred_not (, mode); @@ -159,9 +159,9 @@ (define_insn_and_split "*n" (any_bitwise:VB (match_operand:VB 1 "register_operand" " vr") (match_operand:VB 2 "register_operand" " vr"))))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { insn_code icode =3D code_for_pred_n (, mode); @@ -346,9 +346,9 @@ (define_insn_and_split "*vtrunc" (match_operand:VWEXTI 1 "register_operand" " vr,vr= ") (any_extend:VWEXTI (match_operand: 2 "vector_shift_operand" " vr,vk= ")))))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { insn_code icode =3D code_for_pred_narrow (, mode= ); @@ -364,9 +364,9 @@ (define_insn_and_split "*trunc" (any_shiftrt:VWEXTI (match_operand:VWEXTI 1 "register_operand" " vr") (match_operand: 2 "csr_operand" " rK"))))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { operands[2] =3D gen_lowpart (Pmode, operands[2]); diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index eadc2c5b595..c23a625afe1 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -155,9 +155,9 @@ (define_insn_and_split "3" (any_shift:VI (match_operand:VI 1 "register_operand" " vr") (match_operand: 2 "csr_operand" " rK")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { operands[2] =3D gen_lowpart (Pmode, operands[2]); @@ -180,9 +180,9 @@ (define_insn_and_split "v3" (any_shift:VI (match_operand:VI 1 "register_operand" " vr,vr") (match_operand:VI 2 "vector_shift_operand" " vr,vk")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { riscv_vector::emit_vlmax_insn (code_for_pred (, mode), @@ -205,9 +205,9 @@ (define_insn_and_split "3" [(set (match_operand:VB 0 "register_operand" "=3Dvr") (any_bitwise:VB (match_operand:VB 1 "register_operand" " vr") (match_operand:VB 2 "register_operand" " vr")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { insn_code icode =3D code_for_pred (, mode); @@ -227,9 +227,9 @@ (define_insn_and_split "3" (define_insn_and_split "one_cmpl2" [(set (match_operand:VB 0 "register_operand" "=3Dvr") (not:VB (match_operand:VB 1 "register_operand" " vr")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { insn_code icode =3D code_for_pred_not (mode); @@ -366,9 +366,9 @@ (define_insn_and_split "2" [(set (match_operand:VWEXTI 0 "register_operand" "=3D&vr") (any_extend:VWEXTI (match_operand: 1 "register_operand" "vr")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { insn_code icode =3D code_for_pred_vf2 (, mode); @@ -409,9 +409,9 @@ (define_insn_and_split "trunc2" [(set (match_operand: 0 "register_operand" "=3Dvr") (truncate: (match_operand:VWEXTI 1 "register_operand" " vr")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { insn_code icode =3D code_for_pred_trunc (mode); -- 2.34.1 --_000_MW5PR11MB59085BC7ECA580E0B9011EE9A95AAMW5PR11MB5908namp_--