* [PATCH v1] RISC-V: Bugfix vec_extract vls mode iterator restriction mismatch
@ 2024-06-13 8:26 pan2.li
2024-06-13 9:23 ` juzhe.zhong
0 siblings, 1 reply; 3+ messages in thread
From: pan2.li @ 2024-06-13 8:26 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, jeffreyalaw, rdapp.gcc, Pan Li
From: Pan Li <pan2.li@intel.com>
We have vec_extract pattern which takes ZVFHMIN as the mode
iterator of the VLS mode. Aka V_VLS. But it will expand to
pred_extract_first pattern which takes the ZVFH as the mode
iterator of the VLS mode. AKa V_VLSF. The mismatch will
result in one ICE similar as below:
error: unrecognizable insn:
27 | }
| ^
(insn 19 18 20 2 (set (reg:HF 150 [ _13 ])
(unspec:HF [
(vec_select:HF (reg:V4HF 134 [ _1 ])
(parallel [
(const_int 0 [0])
]))
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)) "compress_run-2.c":24:5 -1
(nil))
during RTL pass: vregs
compress_run-2.c:27:1: internal compiler error: in extract_insn, at
recog.cc:2812
0x1a627ef _fatal_insn(char const*, rtx_def const*, char const*, int,
char const*)
../../../gcc/gcc/rtl-error.cc:108
0x1a62834 _fatal_insn_not_found(rtx_def const*, char const*, int, char
const*)
../../../gcc/gcc/rtl-error.cc:116
0x1a0f356 extract_insn(rtx_insn*)
../../../gcc/gcc/recog.cc:2812
0x159ee61 instantiate_virtual_regs_in_insn
../../../gcc/gcc/function.cc:1612
0x15a04aa instantiate_virtual_regs
../../../gcc/gcc/function.cc:1995
0x15a058e execute
../../../gcc/gcc/function.cc:2042
This patch would like to fix this issue by align the mode
iterator restriction to ZVFH.
The below test suites are passed for this patch.
1. The rv64gcv fully regression test.
2. The rv64gcv build with glibc.
PR target/115456
gcc/ChangeLog:
* config/riscv/autovec.md: Take ZVFH mode iterator instead of
the ZVFHMIN for the alignment.
* config/riscv/vector-iterators.md: Add 2 new iterator
V_VLS_ZVFH and VLS_ZVFH.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr115456-1.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/config/riscv/autovec.md | 2 +-
gcc/config/riscv/vector-iterators.md | 4 +++
.../gcc.target/riscv/rvv/base/pr115456-1.c | 31 +++++++++++++++++++
3 files changed, 36 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-1.c
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 0b1e50dd0e9..66d70f678a6 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -1383,7 +1383,7 @@ (define_expand "vec_set<mode>"
(define_expand "vec_extract<mode><vel>"
[(set (match_operand:<VEL> 0 "register_operand")
(vec_select:<VEL>
- (match_operand:V_VLS 1 "register_operand")
+ (match_operand:V_VLS_ZVFH 1 "register_operand")
(parallel
[(match_operand 2 "nonmemory_operand")])))]
"TARGET_VECTOR"
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index 76c27035a73..47392d0da4c 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -1574,10 +1574,14 @@ (define_mode_iterator VB_VLS [VB VLSB])
(define_mode_iterator VLS [VLSI VLSF_ZVFHMIN])
+(define_mode_iterator VLS_ZVFH [VLSI VLSF])
+
(define_mode_iterator V [VI VF_ZVFHMIN])
(define_mode_iterator V_VLS [V VLS])
+(define_mode_iterator V_VLS_ZVFH [V VLS_ZVFH])
+
(define_mode_iterator V_VLSI [VI VLSI])
(define_mode_iterator V_VLSF [VF VLSF])
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-1.c
new file mode 100644
index 00000000000..2c6cc7121b4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-1.c
@@ -0,0 +1,31 @@
+/* Test there is no ICE when compile. */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -ftree-vectorize" } */
+
+#include <assert.h>
+#include <stdint-gcc.h>
+
+typedef _Float16 vnx4f __attribute__ ((vector_size (8)));
+
+vnx4f __attribute__ ((noinline, noclone))
+test_5 (vnx4f x, vnx4f y)
+{
+ return __builtin_shufflevector (x, y, 1, 3, 6, 7);
+}
+
+int
+main (void)
+{
+ vnx4f test_5_x = {0, 1, 3, 4};
+ vnx4f test_5_y = {4, 5, 6, 7};
+ vnx4f test_5_except = {1, 4, 6, 7};
+ vnx4f test_5_real;
+ test_5_real = test_5 (test_5_x, test_5_y);
+
+ for (int i = 0; i < 4; i++)
+ assert (test_5_real[i] == test_5_except[i]);
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times {call\s+__extendhfsf2} 8 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v1] RISC-V: Bugfix vec_extract vls mode iterator restriction mismatch
2024-06-13 8:26 [PATCH v1] RISC-V: Bugfix vec_extract vls mode iterator restriction mismatch pan2.li
@ 2024-06-13 9:23 ` juzhe.zhong
2024-06-13 9:46 ` Li, Pan2
0 siblings, 1 reply; 3+ messages in thread
From: juzhe.zhong @ 2024-06-13 9:23 UTC (permalink / raw)
To: pan2.li, gcc-patches; +Cc: kito.cheng, jeffreyalaw, Robin Dapp, pan2.li
[-- Attachment #1: Type: text/plain, Size: 4723 bytes --]
LGTM
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2024-06-13 16:26
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Bugfix vec_extract vls mode iterator restriction mismatch
From: Pan Li <pan2.li@intel.com>
We have vec_extract pattern which takes ZVFHMIN as the mode
iterator of the VLS mode. Aka V_VLS. But it will expand to
pred_extract_first pattern which takes the ZVFH as the mode
iterator of the VLS mode. AKa V_VLSF. The mismatch will
result in one ICE similar as below:
error: unrecognizable insn:
27 | }
| ^
(insn 19 18 20 2 (set (reg:HF 150 [ _13 ])
(unspec:HF [
(vec_select:HF (reg:V4HF 134 [ _1 ])
(parallel [
(const_int 0 [0])
]))
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)) "compress_run-2.c":24:5 -1
(nil))
during RTL pass: vregs
compress_run-2.c:27:1: internal compiler error: in extract_insn, at
recog.cc:2812
0x1a627ef _fatal_insn(char const*, rtx_def const*, char const*, int,
char const*)
../../../gcc/gcc/rtl-error.cc:108
0x1a62834 _fatal_insn_not_found(rtx_def const*, char const*, int, char
const*)
../../../gcc/gcc/rtl-error.cc:116
0x1a0f356 extract_insn(rtx_insn*)
../../../gcc/gcc/recog.cc:2812
0x159ee61 instantiate_virtual_regs_in_insn
../../../gcc/gcc/function.cc:1612
0x15a04aa instantiate_virtual_regs
../../../gcc/gcc/function.cc:1995
0x15a058e execute
../../../gcc/gcc/function.cc:2042
This patch would like to fix this issue by align the mode
iterator restriction to ZVFH.
The below test suites are passed for this patch.
1. The rv64gcv fully regression test.
2. The rv64gcv build with glibc.
PR target/115456
gcc/ChangeLog:
* config/riscv/autovec.md: Take ZVFH mode iterator instead of
the ZVFHMIN for the alignment.
* config/riscv/vector-iterators.md: Add 2 new iterator
V_VLS_ZVFH and VLS_ZVFH.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr115456-1.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/config/riscv/autovec.md | 2 +-
gcc/config/riscv/vector-iterators.md | 4 +++
.../gcc.target/riscv/rvv/base/pr115456-1.c | 31 +++++++++++++++++++
3 files changed, 36 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-1.c
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 0b1e50dd0e9..66d70f678a6 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -1383,7 +1383,7 @@ (define_expand "vec_set<mode>"
(define_expand "vec_extract<mode><vel>"
[(set (match_operand:<VEL> 0 "register_operand")
(vec_select:<VEL>
- (match_operand:V_VLS 1 "register_operand")
+ (match_operand:V_VLS_ZVFH 1 "register_operand")
(parallel
[(match_operand 2 "nonmemory_operand")])))]
"TARGET_VECTOR"
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index 76c27035a73..47392d0da4c 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -1574,10 +1574,14 @@ (define_mode_iterator VB_VLS [VB VLSB])
(define_mode_iterator VLS [VLSI VLSF_ZVFHMIN])
+(define_mode_iterator VLS_ZVFH [VLSI VLSF])
+
(define_mode_iterator V [VI VF_ZVFHMIN])
(define_mode_iterator V_VLS [V VLS])
+(define_mode_iterator V_VLS_ZVFH [V VLS_ZVFH])
+
(define_mode_iterator V_VLSI [VI VLSI])
(define_mode_iterator V_VLSF [VF VLSF])
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-1.c
new file mode 100644
index 00000000000..2c6cc7121b4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-1.c
@@ -0,0 +1,31 @@
+/* Test there is no ICE when compile. */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -ftree-vectorize" } */
+
+#include <assert.h>
+#include <stdint-gcc.h>
+
+typedef _Float16 vnx4f __attribute__ ((vector_size (8)));
+
+vnx4f __attribute__ ((noinline, noclone))
+test_5 (vnx4f x, vnx4f y)
+{
+ return __builtin_shufflevector (x, y, 1, 3, 6, 7);
+}
+
+int
+main (void)
+{
+ vnx4f test_5_x = {0, 1, 3, 4};
+ vnx4f test_5_y = {4, 5, 6, 7};
+ vnx4f test_5_except = {1, 4, 6, 7};
+ vnx4f test_5_real;
+ test_5_real = test_5 (test_5_x, test_5_y);
+
+ for (int i = 0; i < 4; i++)
+ assert (test_5_real[i] == test_5_except[i]);
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times {call\s+__extendhfsf2} 8 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* RE: [PATCH v1] RISC-V: Bugfix vec_extract vls mode iterator restriction mismatch
2024-06-13 9:23 ` juzhe.zhong
@ 2024-06-13 9:46 ` Li, Pan2
0 siblings, 0 replies; 3+ messages in thread
From: Li, Pan2 @ 2024-06-13 9:46 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches; +Cc: kito.cheng, jeffreyalaw, Robin Dapp
[-- Attachment #1: Type: text/plain, Size: 5450 bytes --]
Committed, thanks Juzhe.
Pan
From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Thursday, June 13, 2024 5:23 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: kito.cheng <kito.cheng@gmail.com>; jeffreyalaw <jeffreyalaw@gmail.com>; Robin Dapp <rdapp.gcc@gmail.com>; Li, Pan2 <pan2.li@intel.com>
Subject: Re: [PATCH v1] RISC-V: Bugfix vec_extract vls mode iterator restriction mismatch
LGTM
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: pan2.li<mailto:pan2.li@intel.com>
Date: 2024-06-13 16:26
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; kito.cheng<mailto:kito.cheng@gmail.com>; jeffreyalaw<mailto:jeffreyalaw@gmail.com>; rdapp.gcc<mailto:rdapp.gcc@gmail.com>; Pan Li<mailto:pan2.li@intel.com>
Subject: [PATCH v1] RISC-V: Bugfix vec_extract vls mode iterator restriction mismatch
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
We have vec_extract pattern which takes ZVFHMIN as the mode
iterator of the VLS mode. Aka V_VLS. But it will expand to
pred_extract_first pattern which takes the ZVFH as the mode
iterator of the VLS mode. AKa V_VLSF. The mismatch will
result in one ICE similar as below:
error: unrecognizable insn:
27 | }
| ^
(insn 19 18 20 2 (set (reg:HF 150 [ _13 ])
(unspec:HF [
(vec_select:HF (reg:V4HF 134 [ _1 ])
(parallel [
(const_int 0 [0])
]))
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)) "compress_run-2.c":24:5 -1
(nil))
during RTL pass: vregs
compress_run-2.c:27:1: internal compiler error: in extract_insn, at
recog.cc:2812
0x1a627ef _fatal_insn(char const*, rtx_def const*, char const*, int,
char const*)
../../../gcc/gcc/rtl-error.cc:108
0x1a62834 _fatal_insn_not_found(rtx_def const*, char const*, int, char
const*)
../../../gcc/gcc/rtl-error.cc:116
0x1a0f356 extract_insn(rtx_insn*)
../../../gcc/gcc/recog.cc:2812
0x159ee61 instantiate_virtual_regs_in_insn
../../../gcc/gcc/function.cc:1612
0x15a04aa instantiate_virtual_regs
../../../gcc/gcc/function.cc:1995
0x15a058e execute
../../../gcc/gcc/function.cc:2042
This patch would like to fix this issue by align the mode
iterator restriction to ZVFH.
The below test suites are passed for this patch.
1. The rv64gcv fully regression test.
2. The rv64gcv build with glibc.
PR target/115456
gcc/ChangeLog:
* config/riscv/autovec.md: Take ZVFH mode iterator instead of
the ZVFHMIN for the alignment.
* config/riscv/vector-iterators.md: Add 2 new iterator
V_VLS_ZVFH and VLS_ZVFH.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr115456-1.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
---
gcc/config/riscv/autovec.md | 2 +-
gcc/config/riscv/vector-iterators.md | 4 +++
.../gcc.target/riscv/rvv/base/pr115456-1.c | 31 +++++++++++++++++++
3 files changed, 36 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-1.c
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 0b1e50dd0e9..66d70f678a6 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -1383,7 +1383,7 @@ (define_expand "vec_set<mode>"
(define_expand "vec_extract<mode><vel>"
[(set (match_operand:<VEL> 0 "register_operand")
(vec_select:<VEL>
- (match_operand:V_VLS 1 "register_operand")
+ (match_operand:V_VLS_ZVFH 1 "register_operand")
(parallel
[(match_operand 2 "nonmemory_operand")])))]
"TARGET_VECTOR"
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index 76c27035a73..47392d0da4c 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -1574,10 +1574,14 @@ (define_mode_iterator VB_VLS [VB VLSB])
(define_mode_iterator VLS [VLSI VLSF_ZVFHMIN])
+(define_mode_iterator VLS_ZVFH [VLSI VLSF])
+
(define_mode_iterator V [VI VF_ZVFHMIN])
(define_mode_iterator V_VLS [V VLS])
+(define_mode_iterator V_VLS_ZVFH [V VLS_ZVFH])
+
(define_mode_iterator V_VLSI [VI VLSI])
(define_mode_iterator V_VLSF [VF VLSF])
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-1.c
new file mode 100644
index 00000000000..2c6cc7121b4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-1.c
@@ -0,0 +1,31 @@
+/* Test there is no ICE when compile. */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -ftree-vectorize" } */
+
+#include <assert.h>
+#include <stdint-gcc.h>
+
+typedef _Float16 vnx4f __attribute__ ((vector_size (8)));
+
+vnx4f __attribute__ ((noinline, noclone))
+test_5 (vnx4f x, vnx4f y)
+{
+ return __builtin_shufflevector (x, y, 1, 3, 6, 7);
+}
+
+int
+main (void)
+{
+ vnx4f test_5_x = {0, 1, 3, 4};
+ vnx4f test_5_y = {4, 5, 6, 7};
+ vnx4f test_5_except = {1, 4, 6, 7};
+ vnx4f test_5_real;
+ test_5_real = test_5 (test_5_x, test_5_y);
+
+ for (int i = 0; i < 4; i++)
+ assert (test_5_real[i] == test_5_except[i]);
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times {call\s+__extendhfsf2} 8 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread
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2024-06-13 8:26 [PATCH v1] RISC-V: Bugfix vec_extract vls mode iterator restriction mismatch pan2.li
2024-06-13 9:23 ` juzhe.zhong
2024-06-13 9:46 ` Li, Pan2
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