* [PATCH v1 1/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 1
@ 2024-07-01 1:35 pan2.li
2024-07-01 1:35 ` [PATCH v1 2/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 2 pan2.li
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: pan2.li @ 2024-07-01 1:35 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, jeffreyalaw, rdapp.gcc, Pan Li
From: Pan Li <pan2.li@intel.com>
This patch would like to add test cases for the unsigned scalar
.SAT_ADD IMM form 1. Aka:
Form 1:
#define DEF_SAT_U_ADD_IMM_FMT_1(T) \
T __attribute__((noinline)) \
sat_u_add_imm_##T##_fmt_1 (T x) \
{ \
return (T)(x + 9) >= x ? (x + 9) : -1; \
}
DEF_SAT_U_ADD_IMM_FMT_1(uint64_t)
The below test is passed for this patch.
* The rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper test macro.
* gcc.target/riscv/sat_u_add_imm-1.c: New test.
* gcc.target/riscv/sat_u_add_imm-2.c: New test.
* gcc.target/riscv/sat_u_add_imm-3.c: New test.
* gcc.target/riscv/sat_u_add_imm-4.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-1.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-2.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-3.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-4.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 10 ++++
.../gcc.target/riscv/sat_u_add_imm-1.c | 19 ++++++++
.../gcc.target/riscv/sat_u_add_imm-2.c | 21 +++++++++
.../gcc.target/riscv/sat_u_add_imm-3.c | 18 ++++++++
.../gcc.target/riscv/sat_u_add_imm-4.c | 17 +++++++
.../gcc.target/riscv/sat_u_add_imm-run-1.c | 46 +++++++++++++++++++
.../gcc.target/riscv/sat_u_add_imm-run-2.c | 46 +++++++++++++++++++
.../gcc.target/riscv/sat_u_add_imm-run-3.c | 46 +++++++++++++++++++
.../gcc.target/riscv/sat_u_add_imm-run-4.c | 46 +++++++++++++++++++
9 files changed, 269 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-4.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index 0c2e44af718..4ec4ec36cc1 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -60,6 +60,16 @@ sat_u_add_##T##_fmt_6 (T x, T y) \
#define RUN_SAT_U_ADD_FMT_5(T, x, y) sat_u_add_##T##_fmt_5(x, y)
#define RUN_SAT_U_ADD_FMT_6(T, x, y) sat_u_add_##T##_fmt_6(x, y)
+#define DEF_SAT_U_ADD_IMM_FMT_1(T, IMM) \
+T __attribute__((noinline)) \
+sat_u_add_imm##IMM##_##T##_fmt_1 (T x) \
+{ \
+ return (T)(x + IMM) >= x ? (x + IMM) : -1; \
+}
+
+#define RUN_SAT_U_ADD_IMM_FMT_1(T, x, IMM, expect) \
+ if (sat_u_add_imm##IMM##_##T##_fmt_1(x) != expect) __builtin_abort ()
+
/******************************************************************************/
/* Saturation Sub (Unsigned and Signed) */
/******************************************************************************/
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-1.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-1.c
new file mode 100644
index 00000000000..14e9b7595a8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm9_uint8_t_fmt_1:
+** addi\s+[atx][0-9]+,\s*a0,\s*9
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_1(uint8_t, 9)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-2.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-2.c
new file mode 100644
index 00000000000..c1a3c6ff21d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-2.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm3_uint16_t_fmt_1:
+** addi\s+[atx][0-9]+,\s*a0,\s*3
+** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48
+** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_1(uint16_t, 3)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-3.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-3.c
new file mode 100644
index 00000000000..21cc903c78e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-3.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm7_uint32_t_fmt_1:
+** addiw\s+[atx][0-9]+,\s*a0,\s*7
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_1(uint32_t, 7)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-4.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-4.c
new file mode 100644
index 00000000000..65693c32d79
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-4.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm8_uint64_t_fmt_1:
+** addi\s+[atx][0-9]+,\s*a0,\s*8
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_1(uint64_t, 8)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-1.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-1.c
new file mode 100644
index 00000000000..0ce546f8f84
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-1.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_1(uint8_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_1(uint8_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_1(uint8_t, 254)
+DEF_SAT_U_ADD_IMM_FMT_1(uint8_t, 255)
+
+#define T uint8_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_1(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 254, 254, },
+ { 1, 254, 255, },
+ { 2, 254, 255, },
+ { 0, 255, 255, },
+ { 1, 255, 255, },
+ { 2, 255, 255, },
+ { 255, 255, 255, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 254, d[3][2]);
+ RUN (T, d[4][0], 254, d[4][2]);
+ RUN (T, d[5][0], 254, d[5][2]);
+
+ RUN (T, d[6][0], 255, d[6][2]);
+ RUN (T, d[7][0], 255, d[7][2]);
+ RUN (T, d[8][0], 255, d[8][2]);
+ RUN (T, d[9][0], 255, d[9][2]);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-2.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-2.c
new file mode 100644
index 00000000000..090c76565ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_1(uint16_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_1(uint16_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_1(uint16_t, 65534)
+DEF_SAT_U_ADD_IMM_FMT_1(uint16_t, 65535)
+
+#define T uint16_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_1(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 65534, 65534, },
+ { 1, 65534, 65535, },
+ { 2, 65534, 65535, },
+ { 0, 65535, 65535, },
+ { 1, 65535, 65535, },
+ { 2, 65535, 65535, },
+ { 65535, 65535, 65535, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 65534, d[3][2]);
+ RUN (T, d[4][0], 65534, d[4][2]);
+ RUN (T, d[5][0], 65534, d[5][2]);
+
+ RUN (T, d[6][0], 65535, d[6][2]);
+ RUN (T, d[7][0], 65535, d[7][2]);
+ RUN (T, d[8][0], 65535, d[8][2]);
+ RUN (T, d[9][0], 65535, d[9][2]);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-3.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-3.c
new file mode 100644
index 00000000000..8dade742625
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-3.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_1(uint32_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_1(uint32_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_1(uint32_t, 4294967294)
+DEF_SAT_U_ADD_IMM_FMT_1(uint32_t, 4294967295)
+
+#define T uint32_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_1(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 4294967294, 4294967294, },
+ { 1, 4294967294, 4294967295, },
+ { 2, 4294967294, 4294967295, },
+ { 0, 4294967295, 4294967295, },
+ { 1, 4294967295, 4294967295, },
+ { 2, 4294967295, 4294967295, },
+ { 4294967295, 4294967295, 4294967295, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 4294967294, d[3][2]);
+ RUN (T, d[4][0], 4294967294, d[4][2]);
+ RUN (T, d[5][0], 4294967294, d[5][2]);
+
+ RUN (T, d[6][0], 4294967295, d[6][2]);
+ RUN (T, d[7][0], 4294967295, d[7][2]);
+ RUN (T, d[8][0], 4294967295, d[8][2]);
+ RUN (T, d[9][0], 4294967295, d[9][2]);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-4.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-4.c
new file mode 100644
index 00000000000..ace2df88e91
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-4.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_1(uint64_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_1(uint64_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_1(uint64_t, 18446744073709551614u)
+DEF_SAT_U_ADD_IMM_FMT_1(uint64_t, 18446744073709551615u)
+
+#define T uint64_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_1(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 18446744073709551614u, 18446744073709551614u, },
+ { 1, 18446744073709551614u, 18446744073709551615u, },
+ { 2, 18446744073709551614u, 18446744073709551615u, },
+ { 0, 18446744073709551615u, 18446744073709551615u, },
+ { 1, 18446744073709551615u, 18446744073709551615u, },
+ { 2, 18446744073709551615u, 18446744073709551615u, },
+ { 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 18446744073709551614u, d[3][2]);
+ RUN (T, d[4][0], 18446744073709551614u, d[4][2]);
+ RUN (T, d[5][0], 18446744073709551614u, d[5][2]);
+
+ RUN (T, d[6][0], 18446744073709551615u, d[6][2]);
+ RUN (T, d[7][0], 18446744073709551615u, d[7][2]);
+ RUN (T, d[8][0], 18446744073709551615u, d[8][2]);
+ RUN (T, d[9][0], 18446744073709551615u, d[9][2]);
+
+ return 0;
+}
--
2.34.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v1 2/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 2
2024-07-01 1:35 [PATCH v1 1/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 1 pan2.li
@ 2024-07-01 1:35 ` pan2.li
2024-07-01 12:22 ` juzhe.zhong
2024-07-01 1:35 ` [PATCH v1 3/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 3 pan2.li
` (2 subsequent siblings)
3 siblings, 1 reply; 9+ messages in thread
From: pan2.li @ 2024-07-01 1:35 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, jeffreyalaw, rdapp.gcc, Pan Li
From: Pan Li <pan2.li@intel.com>
This patch would like to add test cases for the unsigned scalar
.SAT_ADD IMM form 2. Aka:
Form 2:
#define DEF_SAT_U_ADD_IMM_FMT_2(T) \
T __attribute__((noinline)) \
sat_u_add_imm_##T##_fmt_1 (T x) \
{ \
return (T)(x + 9) < x ? -1 : (x + 9); \
}
DEF_SAT_U_ADD_IMM_FMT_2(uint64_t)
The below test is passed for this patch.
* The rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper test macro.
* gcc.target/riscv/sat_u_add_imm-5.c: New test.
* gcc.target/riscv/sat_u_add_imm-6.c: New test.
* gcc.target/riscv/sat_u_add_imm-7.c: New test.
* gcc.target/riscv/sat_u_add_imm-8.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-5.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-6.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-7.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-8.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 10 ++++
.../gcc.target/riscv/sat_u_add_imm-5.c | 19 ++++++++
.../gcc.target/riscv/sat_u_add_imm-6.c | 21 +++++++++
.../gcc.target/riscv/sat_u_add_imm-7.c | 18 ++++++++
.../gcc.target/riscv/sat_u_add_imm-8.c | 17 +++++++
.../gcc.target/riscv/sat_u_add_imm-run-5.c | 46 +++++++++++++++++++
.../gcc.target/riscv/sat_u_add_imm-run-6.c | 46 +++++++++++++++++++
.../gcc.target/riscv/sat_u_add_imm-run-7.c | 46 +++++++++++++++++++
.../gcc.target/riscv/sat_u_add_imm-run-8.c | 46 +++++++++++++++++++
9 files changed, 269 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-8.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-8.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index 4ec4ec36cc1..d94f0fd602c 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -67,9 +67,19 @@ sat_u_add_imm##IMM##_##T##_fmt_1 (T x) \
return (T)(x + IMM) >= x ? (x + IMM) : -1; \
}
+#define DEF_SAT_U_ADD_IMM_FMT_2(T, IMM) \
+T __attribute__((noinline)) \
+sat_u_add_imm##IMM##_##T##_fmt_2 (T x) \
+{ \
+ return (T)(x + IMM) < x ? -1 : (x + IMM); \
+}
+
#define RUN_SAT_U_ADD_IMM_FMT_1(T, x, IMM, expect) \
if (sat_u_add_imm##IMM##_##T##_fmt_1(x) != expect) __builtin_abort ()
+#define RUN_SAT_U_ADD_IMM_FMT_2(T, x, IMM, expect) \
+ if (sat_u_add_imm##IMM##_##T##_fmt_2(x) != expect) __builtin_abort ()
+
/******************************************************************************/
/* Saturation Sub (Unsigned and Signed) */
/******************************************************************************/
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-5.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-5.c
new file mode 100644
index 00000000000..19b502db6c9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-5.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm9_uint8_t_fmt_2:
+** addi\s+[atx][0-9]+,\s*a0,\s*9
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_2(uint8_t, 9)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-6.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-6.c
new file mode 100644
index 00000000000..0317370b67e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-6.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm3_uint16_t_fmt_2:
+** addi\s+[atx][0-9]+,\s*a0,\s*3
+** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48
+** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_2(uint16_t, 3)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-7.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-7.c
new file mode 100644
index 00000000000..044b821f7b5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-7.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm7_uint32_t_fmt_2:
+** addiw\s+[atx][0-9]+,\s*a0,\s*7
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_2(uint32_t, 7)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-8.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-8.c
new file mode 100644
index 00000000000..4eafb83c756
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-8.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm8_uint64_t_fmt_2:
+** addi\s+[atx][0-9]+,\s*a0,\s*8
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_2(uint64_t, 8)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-5.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-5.c
new file mode 100644
index 00000000000..8e8759c9825
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-5.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_2(uint8_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_2(uint8_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_2(uint8_t, 254)
+DEF_SAT_U_ADD_IMM_FMT_2(uint8_t, 255)
+
+#define T uint8_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_2(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 254, 254, },
+ { 1, 254, 255, },
+ { 2, 254, 255, },
+ { 0, 255, 255, },
+ { 1, 255, 255, },
+ { 2, 255, 255, },
+ { 255, 255, 255, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 254, d[3][2]);
+ RUN (T, d[4][0], 254, d[4][2]);
+ RUN (T, d[5][0], 254, d[5][2]);
+
+ RUN (T, d[6][0], 255, d[6][2]);
+ RUN (T, d[7][0], 255, d[7][2]);
+ RUN (T, d[8][0], 255, d[8][2]);
+ RUN (T, d[9][0], 255, d[9][2]);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-6.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-6.c
new file mode 100644
index 00000000000..7b6bd731234
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-6.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_2(uint16_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_2(uint16_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_2(uint16_t, 65534)
+DEF_SAT_U_ADD_IMM_FMT_2(uint16_t, 65535)
+
+#define T uint16_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_2(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 65534, 65534, },
+ { 1, 65534, 65535, },
+ { 2, 65534, 65535, },
+ { 0, 65535, 65535, },
+ { 1, 65535, 65535, },
+ { 2, 65535, 65535, },
+ { 65535, 65535, 65535, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 65534, d[3][2]);
+ RUN (T, d[4][0], 65534, d[4][2]);
+ RUN (T, d[5][0], 65534, d[5][2]);
+
+ RUN (T, d[6][0], 65535, d[6][2]);
+ RUN (T, d[7][0], 65535, d[7][2]);
+ RUN (T, d[8][0], 65535, d[8][2]);
+ RUN (T, d[9][0], 65535, d[9][2]);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-7.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-7.c
new file mode 100644
index 00000000000..80241527ee9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-7.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_2(uint32_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_2(uint32_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_2(uint32_t, 4294967294)
+DEF_SAT_U_ADD_IMM_FMT_2(uint32_t, 4294967295)
+
+#define T uint32_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_2(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 4294967294, 4294967294, },
+ { 1, 4294967294, 4294967295, },
+ { 2, 4294967294, 4294967295, },
+ { 0, 4294967295, 4294967295, },
+ { 1, 4294967295, 4294967295, },
+ { 2, 4294967295, 4294967295, },
+ { 4294967295, 4294967295, 4294967295, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 4294967294, d[3][2]);
+ RUN (T, d[4][0], 4294967294, d[4][2]);
+ RUN (T, d[5][0], 4294967294, d[5][2]);
+
+ RUN (T, d[6][0], 4294967295, d[6][2]);
+ RUN (T, d[7][0], 4294967295, d[7][2]);
+ RUN (T, d[8][0], 4294967295, d[8][2]);
+ RUN (T, d[9][0], 4294967295, d[9][2]);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-8.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-8.c
new file mode 100644
index 00000000000..4a76dbb6dde
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-8.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_2(uint64_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_2(uint64_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_2(uint64_t, 18446744073709551614u)
+DEF_SAT_U_ADD_IMM_FMT_2(uint64_t, 18446744073709551615u)
+
+#define T uint64_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_2(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 18446744073709551614u, 18446744073709551614u, },
+ { 1, 18446744073709551614u, 18446744073709551615u, },
+ { 2, 18446744073709551614u, 18446744073709551615u, },
+ { 0, 18446744073709551615u, 18446744073709551615u, },
+ { 1, 18446744073709551615u, 18446744073709551615u, },
+ { 2, 18446744073709551615u, 18446744073709551615u, },
+ { 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 18446744073709551614u, d[3][2]);
+ RUN (T, d[4][0], 18446744073709551614u, d[4][2]);
+ RUN (T, d[5][0], 18446744073709551614u, d[5][2]);
+
+ RUN (T, d[6][0], 18446744073709551615u, d[6][2]);
+ RUN (T, d[7][0], 18446744073709551615u, d[7][2]);
+ RUN (T, d[8][0], 18446744073709551615u, d[8][2]);
+ RUN (T, d[9][0], 18446744073709551615u, d[9][2]);
+
+ return 0;
+}
--
2.34.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v1 3/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 3
2024-07-01 1:35 [PATCH v1 1/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 1 pan2.li
2024-07-01 1:35 ` [PATCH v1 2/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 2 pan2.li
@ 2024-07-01 1:35 ` pan2.li
2024-07-01 12:22 ` juzhe.zhong
2024-07-01 1:35 ` [PATCH v1 4/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 4 pan2.li
2024-07-01 12:22 ` [PATCH v1 1/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 1 juzhe.zhong
3 siblings, 1 reply; 9+ messages in thread
From: pan2.li @ 2024-07-01 1:35 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, jeffreyalaw, rdapp.gcc, Pan Li
From: Pan Li <pan2.li@intel.com>
This patch would like to add test cases for the unsigned scalar
.SAT_ADD IMM form 3. Aka:
Form 3:
#define DEF_SAT_U_ADD_IMM_FMT_3(T) \
T __attribute__((noinline)) \
sat_u_add_imm_##T##_fmt_3 (T x) \
{ \
T ret; \
return __builtin_add_overflow (x, 8, &ret) ? -1 : ret; \
}
DEF_SAT_U_ADD_IMM_FMT_3(uint64_t)
The below test is passed for this patch.
* The rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper test macro.
* gcc.target/riscv/sat_u_add_imm-10.c: New test.
* gcc.target/riscv/sat_u_add_imm-11.c: New test.
* gcc.target/riscv/sat_u_add_imm-12.c: New test.
* gcc.target/riscv/sat_u_add_imm-9.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-10.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-11.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-12.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-9.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 11 +++++
.../gcc.target/riscv/sat_u_add_imm-10.c | 21 +++++++++
.../gcc.target/riscv/sat_u_add_imm-11.c | 18 ++++++++
.../gcc.target/riscv/sat_u_add_imm-12.c | 17 +++++++
.../gcc.target/riscv/sat_u_add_imm-9.c | 19 ++++++++
.../gcc.target/riscv/sat_u_add_imm-run-10.c | 46 +++++++++++++++++++
.../gcc.target/riscv/sat_u_add_imm-run-11.c | 46 +++++++++++++++++++
.../gcc.target/riscv/sat_u_add_imm-run-12.c | 46 +++++++++++++++++++
.../gcc.target/riscv/sat_u_add_imm-run-9.c | 46 +++++++++++++++++++
9 files changed, 270 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-11.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-12.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-9.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-11.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-12.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-9.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index d94f0fd602c..83b294db476 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -74,12 +74,23 @@ sat_u_add_imm##IMM##_##T##_fmt_2 (T x) \
return (T)(x + IMM) < x ? -1 : (x + IMM); \
}
+#define DEF_SAT_U_ADD_IMM_FMT_3(T, IMM) \
+T __attribute__((noinline)) \
+sat_u_add_imm##IMM##_##T##_fmt_3 (T x) \
+{ \
+ T ret; \
+ return __builtin_add_overflow (x, IMM, &ret) ? -1 : ret; \
+}
+
#define RUN_SAT_U_ADD_IMM_FMT_1(T, x, IMM, expect) \
if (sat_u_add_imm##IMM##_##T##_fmt_1(x) != expect) __builtin_abort ()
#define RUN_SAT_U_ADD_IMM_FMT_2(T, x, IMM, expect) \
if (sat_u_add_imm##IMM##_##T##_fmt_2(x) != expect) __builtin_abort ()
+#define RUN_SAT_U_ADD_IMM_FMT_3(T, x, IMM, expect) \
+ if (sat_u_add_imm##IMM##_##T##_fmt_3(x) != expect) __builtin_abort ()
+
/******************************************************************************/
/* Saturation Sub (Unsigned and Signed) */
/******************************************************************************/
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-10.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-10.c
new file mode 100644
index 00000000000..24cdd267cca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-10.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm3_uint16_t_fmt_3:
+** addi\s+[atx][0-9]+,\s*a0,\s*3
+** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48
+** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_3(uint16_t, 3)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-11.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-11.c
new file mode 100644
index 00000000000..f30e2405a0d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-11.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm7_uint32_t_fmt_3:
+** addiw\s+[atx][0-9]+,\s*a0,\s*7
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_3(uint32_t, 7)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-12.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-12.c
new file mode 100644
index 00000000000..561c127f5fa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-12.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm8_uint64_t_fmt_3:
+** addi\s+[atx][0-9]+,\s*a0,\s*8
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_3(uint64_t, 8)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-9.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-9.c
new file mode 100644
index 00000000000..5fcd6d71a26
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-9.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm9_uint8_t_fmt_3:
+** addi\s+[atx][0-9]+,\s*a0,\s*9
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_3(uint8_t, 9)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-10.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-10.c
new file mode 100644
index 00000000000..64924a665a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-10.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_3(uint16_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_3(uint16_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_3(uint16_t, 65534)
+DEF_SAT_U_ADD_IMM_FMT_3(uint16_t, 65535)
+
+#define T uint16_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_3(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 65534, 65534, },
+ { 1, 65534, 65535, },
+ { 2, 65534, 65535, },
+ { 0, 65535, 65535, },
+ { 1, 65535, 65535, },
+ { 2, 65535, 65535, },
+ { 65535, 65535, 65535, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 65534, d[3][2]);
+ RUN (T, d[4][0], 65534, d[4][2]);
+ RUN (T, d[5][0], 65534, d[5][2]);
+
+ RUN (T, d[6][0], 65535, d[6][2]);
+ RUN (T, d[7][0], 65535, d[7][2]);
+ RUN (T, d[8][0], 65535, d[8][2]);
+ RUN (T, d[9][0], 65535, d[9][2]);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-11.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-11.c
new file mode 100644
index 00000000000..04f32172065
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-11.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_3(uint32_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_3(uint32_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_3(uint32_t, 4294967294)
+DEF_SAT_U_ADD_IMM_FMT_3(uint32_t, 4294967295)
+
+#define T uint32_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_3(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 4294967294, 4294967294, },
+ { 1, 4294967294, 4294967295, },
+ { 2, 4294967294, 4294967295, },
+ { 0, 4294967295, 4294967295, },
+ { 1, 4294967295, 4294967295, },
+ { 2, 4294967295, 4294967295, },
+ { 4294967295, 4294967295, 4294967295, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 4294967294, d[3][2]);
+ RUN (T, d[4][0], 4294967294, d[4][2]);
+ RUN (T, d[5][0], 4294967294, d[5][2]);
+
+ RUN (T, d[6][0], 4294967295, d[6][2]);
+ RUN (T, d[7][0], 4294967295, d[7][2]);
+ RUN (T, d[8][0], 4294967295, d[8][2]);
+ RUN (T, d[9][0], 4294967295, d[9][2]);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-12.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-12.c
new file mode 100644
index 00000000000..8ef6c14a367
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-12.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_3(uint64_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_3(uint64_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_3(uint64_t, 18446744073709551614u)
+DEF_SAT_U_ADD_IMM_FMT_3(uint64_t, 18446744073709551615u)
+
+#define T uint64_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_3(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 18446744073709551614u, 18446744073709551614u, },
+ { 1, 18446744073709551614u, 18446744073709551615u, },
+ { 2, 18446744073709551614u, 18446744073709551615u, },
+ { 0, 18446744073709551615u, 18446744073709551615u, },
+ { 1, 18446744073709551615u, 18446744073709551615u, },
+ { 2, 18446744073709551615u, 18446744073709551615u, },
+ { 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 18446744073709551614u, d[3][2]);
+ RUN (T, d[4][0], 18446744073709551614u, d[4][2]);
+ RUN (T, d[5][0], 18446744073709551614u, d[5][2]);
+
+ RUN (T, d[6][0], 18446744073709551615u, d[6][2]);
+ RUN (T, d[7][0], 18446744073709551615u, d[7][2]);
+ RUN (T, d[8][0], 18446744073709551615u, d[8][2]);
+ RUN (T, d[9][0], 18446744073709551615u, d[9][2]);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-9.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-9.c
new file mode 100644
index 00000000000..88673610454
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-9.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_3(uint8_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_3(uint8_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_3(uint8_t, 254)
+DEF_SAT_U_ADD_IMM_FMT_3(uint8_t, 255)
+
+#define T uint8_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_3(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 254, 254, },
+ { 1, 254, 255, },
+ { 2, 254, 255, },
+ { 0, 255, 255, },
+ { 1, 255, 255, },
+ { 2, 255, 255, },
+ { 255, 255, 255, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 254, d[3][2]);
+ RUN (T, d[4][0], 254, d[4][2]);
+ RUN (T, d[5][0], 254, d[5][2]);
+
+ RUN (T, d[6][0], 255, d[6][2]);
+ RUN (T, d[7][0], 255, d[7][2]);
+ RUN (T, d[8][0], 255, d[8][2]);
+ RUN (T, d[9][0], 255, d[9][2]);
+
+ return 0;
+}
--
2.34.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v1 4/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 4
2024-07-01 1:35 [PATCH v1 1/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 1 pan2.li
2024-07-01 1:35 ` [PATCH v1 2/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 2 pan2.li
2024-07-01 1:35 ` [PATCH v1 3/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 3 pan2.li
@ 2024-07-01 1:35 ` pan2.li
2024-07-01 12:22 ` juzhe.zhong
2024-07-01 12:22 ` [PATCH v1 1/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 1 juzhe.zhong
3 siblings, 1 reply; 9+ messages in thread
From: pan2.li @ 2024-07-01 1:35 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, jeffreyalaw, rdapp.gcc, Pan Li
From: Pan Li <pan2.li@intel.com>
This patch would like to add test cases for the unsigned scalar
.SAT_ADD IMM form 4. Aka:
Form 4:
#define DEF_SAT_U_ADD_IMM_FMT_4(T) \
T __attribute__((noinline)) \
sat_u_add_imm_##T##_fmt_4 (T x) \
{ \
T ret; \
return __builtin_add_overflow (x, 9, &ret) == 0 ? ret : -1; \
}
DEF_SAT_U_ADD_IMM_FMT_4(uint64_t)
The below test is passed for this patch.
* The rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper test macro.
* gcc.target/riscv/sat_u_add_imm-13.c: New test.
* gcc.target/riscv/sat_u_add_imm-14.c: New test.
* gcc.target/riscv/sat_u_add_imm-15.c: New test.
* gcc.target/riscv/sat_u_add_imm-16.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-13.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-14.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-15.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-16.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 11 +++++
.../gcc.target/riscv/sat_u_add_imm-13.c | 19 ++++++++
.../gcc.target/riscv/sat_u_add_imm-14.c | 21 +++++++++
.../gcc.target/riscv/sat_u_add_imm-15.c | 18 ++++++++
.../gcc.target/riscv/sat_u_add_imm-16.c | 17 +++++++
.../gcc.target/riscv/sat_u_add_imm-run-13.c | 46 +++++++++++++++++++
.../gcc.target/riscv/sat_u_add_imm-run-14.c | 46 +++++++++++++++++++
.../gcc.target/riscv/sat_u_add_imm-run-15.c | 46 +++++++++++++++++++
.../gcc.target/riscv/sat_u_add_imm-run-16.c | 46 +++++++++++++++++++
9 files changed, 270 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-13.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-14.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-15.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-16.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-13.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-14.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-15.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-16.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index 83b294db476..75442c94dc1 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -82,6 +82,14 @@ sat_u_add_imm##IMM##_##T##_fmt_3 (T x) \
return __builtin_add_overflow (x, IMM, &ret) ? -1 : ret; \
}
+#define DEF_SAT_U_ADD_IMM_FMT_4(T, IMM) \
+T __attribute__((noinline)) \
+sat_u_add_imm##IMM##_##T##_fmt_4 (T x) \
+{ \
+ T ret; \
+ return __builtin_add_overflow (x, IMM, &ret) == 0 ? ret : -1; \
+}
+
#define RUN_SAT_U_ADD_IMM_FMT_1(T, x, IMM, expect) \
if (sat_u_add_imm##IMM##_##T##_fmt_1(x) != expect) __builtin_abort ()
@@ -91,6 +99,9 @@ sat_u_add_imm##IMM##_##T##_fmt_3 (T x) \
#define RUN_SAT_U_ADD_IMM_FMT_3(T, x, IMM, expect) \
if (sat_u_add_imm##IMM##_##T##_fmt_3(x) != expect) __builtin_abort ()
+#define RUN_SAT_U_ADD_IMM_FMT_4(T, x, IMM, expect) \
+ if (sat_u_add_imm##IMM##_##T##_fmt_4(x) != expect) __builtin_abort ()
+
/******************************************************************************/
/* Saturation Sub (Unsigned and Signed) */
/******************************************************************************/
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-13.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-13.c
new file mode 100644
index 00000000000..a3b2679233c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-13.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm9_uint8_t_fmt_4:
+** addi\s+[atx][0-9]+,\s*a0,\s*9
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_4(uint8_t, 9)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-14.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-14.c
new file mode 100644
index 00000000000..968534b74da
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-14.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm3_uint16_t_fmt_4:
+** addi\s+[atx][0-9]+,\s*a0,\s*3
+** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48
+** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_4(uint16_t, 3)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-15.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-15.c
new file mode 100644
index 00000000000..3918d215658
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-15.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm7_uint32_t_fmt_4:
+** addiw\s+[atx][0-9]+,\s*a0,\s*7
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_4(uint32_t, 7)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-16.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-16.c
new file mode 100644
index 00000000000..307b81589ee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-16.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm8_uint64_t_fmt_4:
+** addi\s+[atx][0-9]+,\s*a0,\s*8
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_4(uint64_t, 8)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-13.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-13.c
new file mode 100644
index 00000000000..872923ec5b9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-13.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_4(uint8_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_4(uint8_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_4(uint8_t, 254)
+DEF_SAT_U_ADD_IMM_FMT_4(uint8_t, 255)
+
+#define T uint8_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_4(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 254, 254, },
+ { 1, 254, 255, },
+ { 2, 254, 255, },
+ { 0, 255, 255, },
+ { 1, 255, 255, },
+ { 2, 255, 255, },
+ { 255, 255, 255, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 254, d[3][2]);
+ RUN (T, d[4][0], 254, d[4][2]);
+ RUN (T, d[5][0], 254, d[5][2]);
+
+ RUN (T, d[6][0], 255, d[6][2]);
+ RUN (T, d[7][0], 255, d[7][2]);
+ RUN (T, d[8][0], 255, d[8][2]);
+ RUN (T, d[9][0], 255, d[9][2]);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-14.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-14.c
new file mode 100644
index 00000000000..0b75206bede
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-14.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_4(uint16_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_4(uint16_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_4(uint16_t, 65534)
+DEF_SAT_U_ADD_IMM_FMT_4(uint16_t, 65535)
+
+#define T uint16_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_4(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 65534, 65534, },
+ { 1, 65534, 65535, },
+ { 2, 65534, 65535, },
+ { 0, 65535, 65535, },
+ { 1, 65535, 65535, },
+ { 2, 65535, 65535, },
+ { 65535, 65535, 65535, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 65534, d[3][2]);
+ RUN (T, d[4][0], 65534, d[4][2]);
+ RUN (T, d[5][0], 65534, d[5][2]);
+
+ RUN (T, d[6][0], 65535, d[6][2]);
+ RUN (T, d[7][0], 65535, d[7][2]);
+ RUN (T, d[8][0], 65535, d[8][2]);
+ RUN (T, d[9][0], 65535, d[9][2]);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-15.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-15.c
new file mode 100644
index 00000000000..e548d0c06b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-15.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_4(uint32_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_4(uint32_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_4(uint32_t, 4294967294)
+DEF_SAT_U_ADD_IMM_FMT_4(uint32_t, 4294967295)
+
+#define T uint32_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_4(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 4294967294, 4294967294, },
+ { 1, 4294967294, 4294967295, },
+ { 2, 4294967294, 4294967295, },
+ { 0, 4294967295, 4294967295, },
+ { 1, 4294967295, 4294967295, },
+ { 2, 4294967295, 4294967295, },
+ { 4294967295, 4294967295, 4294967295, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 4294967294, d[3][2]);
+ RUN (T, d[4][0], 4294967294, d[4][2]);
+ RUN (T, d[5][0], 4294967294, d[5][2]);
+
+ RUN (T, d[6][0], 4294967295, d[6][2]);
+ RUN (T, d[7][0], 4294967295, d[7][2]);
+ RUN (T, d[8][0], 4294967295, d[8][2]);
+ RUN (T, d[9][0], 4294967295, d[9][2]);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-16.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-16.c
new file mode 100644
index 00000000000..4335d827d13
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-16.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_4(uint64_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_4(uint64_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_4(uint64_t, 18446744073709551614u)
+DEF_SAT_U_ADD_IMM_FMT_4(uint64_t, 18446744073709551615u)
+
+#define T uint64_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_4(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 18446744073709551614u, 18446744073709551614u, },
+ { 1, 18446744073709551614u, 18446744073709551615u, },
+ { 2, 18446744073709551614u, 18446744073709551615u, },
+ { 0, 18446744073709551615u, 18446744073709551615u, },
+ { 1, 18446744073709551615u, 18446744073709551615u, },
+ { 2, 18446744073709551615u, 18446744073709551615u, },
+ { 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 18446744073709551614u, d[3][2]);
+ RUN (T, d[4][0], 18446744073709551614u, d[4][2]);
+ RUN (T, d[5][0], 18446744073709551614u, d[5][2]);
+
+ RUN (T, d[6][0], 18446744073709551615u, d[6][2]);
+ RUN (T, d[7][0], 18446744073709551615u, d[7][2]);
+ RUN (T, d[8][0], 18446744073709551615u, d[8][2]);
+ RUN (T, d[9][0], 18446744073709551615u, d[9][2]);
+
+ return 0;
+}
--
2.34.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v1 3/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 3
2024-07-01 1:35 ` [PATCH v1 3/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 3 pan2.li
@ 2024-07-01 12:22 ` juzhe.zhong
0 siblings, 0 replies; 9+ messages in thread
From: juzhe.zhong @ 2024-07-01 12:22 UTC (permalink / raw)
To: pan2.li, gcc-patches; +Cc: kito.cheng, jeffreyalaw, Robin Dapp, pan2.li
[-- Attachment #1: Type: text/plain, Size: 14453 bytes --]
LGTM
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2024-07-01 09:35
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 3/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 3
From: Pan Li <pan2.li@intel.com>
This patch would like to add test cases for the unsigned scalar
.SAT_ADD IMM form 3. Aka:
Form 3:
#define DEF_SAT_U_ADD_IMM_FMT_3(T) \
T __attribute__((noinline)) \
sat_u_add_imm_##T##_fmt_3 (T x) \
{ \
T ret; \
return __builtin_add_overflow (x, 8, &ret) ? -1 : ret; \
}
DEF_SAT_U_ADD_IMM_FMT_3(uint64_t)
The below test is passed for this patch.
* The rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper test macro.
* gcc.target/riscv/sat_u_add_imm-10.c: New test.
* gcc.target/riscv/sat_u_add_imm-11.c: New test.
* gcc.target/riscv/sat_u_add_imm-12.c: New test.
* gcc.target/riscv/sat_u_add_imm-9.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-10.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-11.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-12.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-9.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 11 +++++
.../gcc.target/riscv/sat_u_add_imm-10.c | 21 +++++++++
.../gcc.target/riscv/sat_u_add_imm-11.c | 18 ++++++++
.../gcc.target/riscv/sat_u_add_imm-12.c | 17 +++++++
.../gcc.target/riscv/sat_u_add_imm-9.c | 19 ++++++++
.../gcc.target/riscv/sat_u_add_imm-run-10.c | 46 +++++++++++++++++++
.../gcc.target/riscv/sat_u_add_imm-run-11.c | 46 +++++++++++++++++++
.../gcc.target/riscv/sat_u_add_imm-run-12.c | 46 +++++++++++++++++++
.../gcc.target/riscv/sat_u_add_imm-run-9.c | 46 +++++++++++++++++++
9 files changed, 270 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-11.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-12.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-9.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-11.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-12.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-9.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index d94f0fd602c..83b294db476 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -74,12 +74,23 @@ sat_u_add_imm##IMM##_##T##_fmt_2 (T x) \
return (T)(x + IMM) < x ? -1 : (x + IMM); \
}
+#define DEF_SAT_U_ADD_IMM_FMT_3(T, IMM) \
+T __attribute__((noinline)) \
+sat_u_add_imm##IMM##_##T##_fmt_3 (T x) \
+{ \
+ T ret; \
+ return __builtin_add_overflow (x, IMM, &ret) ? -1 : ret; \
+}
+
#define RUN_SAT_U_ADD_IMM_FMT_1(T, x, IMM, expect) \
if (sat_u_add_imm##IMM##_##T##_fmt_1(x) != expect) __builtin_abort ()
#define RUN_SAT_U_ADD_IMM_FMT_2(T, x, IMM, expect) \
if (sat_u_add_imm##IMM##_##T##_fmt_2(x) != expect) __builtin_abort ()
+#define RUN_SAT_U_ADD_IMM_FMT_3(T, x, IMM, expect) \
+ if (sat_u_add_imm##IMM##_##T##_fmt_3(x) != expect) __builtin_abort ()
+
/******************************************************************************/
/* Saturation Sub (Unsigned and Signed) */
/******************************************************************************/
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-10.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-10.c
new file mode 100644
index 00000000000..24cdd267cca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-10.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm3_uint16_t_fmt_3:
+** addi\s+[atx][0-9]+,\s*a0,\s*3
+** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48
+** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_3(uint16_t, 3)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-11.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-11.c
new file mode 100644
index 00000000000..f30e2405a0d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-11.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm7_uint32_t_fmt_3:
+** addiw\s+[atx][0-9]+,\s*a0,\s*7
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_3(uint32_t, 7)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-12.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-12.c
new file mode 100644
index 00000000000..561c127f5fa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-12.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm8_uint64_t_fmt_3:
+** addi\s+[atx][0-9]+,\s*a0,\s*8
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_3(uint64_t, 8)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-9.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-9.c
new file mode 100644
index 00000000000..5fcd6d71a26
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-9.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm9_uint8_t_fmt_3:
+** addi\s+[atx][0-9]+,\s*a0,\s*9
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_3(uint8_t, 9)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-10.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-10.c
new file mode 100644
index 00000000000..64924a665a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-10.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_3(uint16_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_3(uint16_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_3(uint16_t, 65534)
+DEF_SAT_U_ADD_IMM_FMT_3(uint16_t, 65535)
+
+#define T uint16_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_3(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 65534, 65534, },
+ { 1, 65534, 65535, },
+ { 2, 65534, 65535, },
+ { 0, 65535, 65535, },
+ { 1, 65535, 65535, },
+ { 2, 65535, 65535, },
+ { 65535, 65535, 65535, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 65534, d[3][2]);
+ RUN (T, d[4][0], 65534, d[4][2]);
+ RUN (T, d[5][0], 65534, d[5][2]);
+
+ RUN (T, d[6][0], 65535, d[6][2]);
+ RUN (T, d[7][0], 65535, d[7][2]);
+ RUN (T, d[8][0], 65535, d[8][2]);
+ RUN (T, d[9][0], 65535, d[9][2]);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-11.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-11.c
new file mode 100644
index 00000000000..04f32172065
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-11.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_3(uint32_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_3(uint32_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_3(uint32_t, 4294967294)
+DEF_SAT_U_ADD_IMM_FMT_3(uint32_t, 4294967295)
+
+#define T uint32_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_3(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 4294967294, 4294967294, },
+ { 1, 4294967294, 4294967295, },
+ { 2, 4294967294, 4294967295, },
+ { 0, 4294967295, 4294967295, },
+ { 1, 4294967295, 4294967295, },
+ { 2, 4294967295, 4294967295, },
+ { 4294967295, 4294967295, 4294967295, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 4294967294, d[3][2]);
+ RUN (T, d[4][0], 4294967294, d[4][2]);
+ RUN (T, d[5][0], 4294967294, d[5][2]);
+
+ RUN (T, d[6][0], 4294967295, d[6][2]);
+ RUN (T, d[7][0], 4294967295, d[7][2]);
+ RUN (T, d[8][0], 4294967295, d[8][2]);
+ RUN (T, d[9][0], 4294967295, d[9][2]);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-12.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-12.c
new file mode 100644
index 00000000000..8ef6c14a367
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-12.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_3(uint64_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_3(uint64_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_3(uint64_t, 18446744073709551614u)
+DEF_SAT_U_ADD_IMM_FMT_3(uint64_t, 18446744073709551615u)
+
+#define T uint64_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_3(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 18446744073709551614u, 18446744073709551614u, },
+ { 1, 18446744073709551614u, 18446744073709551615u, },
+ { 2, 18446744073709551614u, 18446744073709551615u, },
+ { 0, 18446744073709551615u, 18446744073709551615u, },
+ { 1, 18446744073709551615u, 18446744073709551615u, },
+ { 2, 18446744073709551615u, 18446744073709551615u, },
+ { 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 18446744073709551614u, d[3][2]);
+ RUN (T, d[4][0], 18446744073709551614u, d[4][2]);
+ RUN (T, d[5][0], 18446744073709551614u, d[5][2]);
+
+ RUN (T, d[6][0], 18446744073709551615u, d[6][2]);
+ RUN (T, d[7][0], 18446744073709551615u, d[7][2]);
+ RUN (T, d[8][0], 18446744073709551615u, d[8][2]);
+ RUN (T, d[9][0], 18446744073709551615u, d[9][2]);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-9.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-9.c
new file mode 100644
index 00000000000..88673610454
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-9.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_3(uint8_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_3(uint8_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_3(uint8_t, 254)
+DEF_SAT_U_ADD_IMM_FMT_3(uint8_t, 255)
+
+#define T uint8_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_3(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 254, 254, },
+ { 1, 254, 255, },
+ { 2, 254, 255, },
+ { 0, 255, 255, },
+ { 1, 255, 255, },
+ { 2, 255, 255, },
+ { 255, 255, 255, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 254, d[3][2]);
+ RUN (T, d[4][0], 254, d[4][2]);
+ RUN (T, d[5][0], 254, d[5][2]);
+
+ RUN (T, d[6][0], 255, d[6][2]);
+ RUN (T, d[7][0], 255, d[7][2]);
+ RUN (T, d[8][0], 255, d[8][2]);
+ RUN (T, d[9][0], 255, d[9][2]);
+
+ return 0;
+}
--
2.34.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v1 1/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 1
2024-07-01 1:35 [PATCH v1 1/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 1 pan2.li
` (2 preceding siblings ...)
2024-07-01 1:35 ` [PATCH v1 4/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 4 pan2.li
@ 2024-07-01 12:22 ` juzhe.zhong
2024-07-01 12:34 ` Li, Pan2
3 siblings, 1 reply; 9+ messages in thread
From: juzhe.zhong @ 2024-07-01 12:22 UTC (permalink / raw)
To: pan2.li, gcc-patches; +Cc: kito.cheng, jeffreyalaw, Robin Dapp, pan2.li
[-- Attachment #1: Type: text/plain, Size: 13967 bytes --]
LGTM
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2024-07-01 09:35
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 1/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 1
From: Pan Li <pan2.li@intel.com>
This patch would like to add test cases for the unsigned scalar
.SAT_ADD IMM form 1. Aka:
Form 1:
#define DEF_SAT_U_ADD_IMM_FMT_1(T) \
T __attribute__((noinline)) \
sat_u_add_imm_##T##_fmt_1 (T x) \
{ \
return (T)(x + 9) >= x ? (x + 9) : -1; \
}
DEF_SAT_U_ADD_IMM_FMT_1(uint64_t)
The below test is passed for this patch.
* The rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper test macro.
* gcc.target/riscv/sat_u_add_imm-1.c: New test.
* gcc.target/riscv/sat_u_add_imm-2.c: New test.
* gcc.target/riscv/sat_u_add_imm-3.c: New test.
* gcc.target/riscv/sat_u_add_imm-4.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-1.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-2.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-3.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-4.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 10 ++++
.../gcc.target/riscv/sat_u_add_imm-1.c | 19 ++++++++
.../gcc.target/riscv/sat_u_add_imm-2.c | 21 +++++++++
.../gcc.target/riscv/sat_u_add_imm-3.c | 18 ++++++++
.../gcc.target/riscv/sat_u_add_imm-4.c | 17 +++++++
.../gcc.target/riscv/sat_u_add_imm-run-1.c | 46 +++++++++++++++++++
.../gcc.target/riscv/sat_u_add_imm-run-2.c | 46 +++++++++++++++++++
.../gcc.target/riscv/sat_u_add_imm-run-3.c | 46 +++++++++++++++++++
.../gcc.target/riscv/sat_u_add_imm-run-4.c | 46 +++++++++++++++++++
9 files changed, 269 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-4.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index 0c2e44af718..4ec4ec36cc1 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -60,6 +60,16 @@ sat_u_add_##T##_fmt_6 (T x, T y) \
#define RUN_SAT_U_ADD_FMT_5(T, x, y) sat_u_add_##T##_fmt_5(x, y)
#define RUN_SAT_U_ADD_FMT_6(T, x, y) sat_u_add_##T##_fmt_6(x, y)
+#define DEF_SAT_U_ADD_IMM_FMT_1(T, IMM) \
+T __attribute__((noinline)) \
+sat_u_add_imm##IMM##_##T##_fmt_1 (T x) \
+{ \
+ return (T)(x + IMM) >= x ? (x + IMM) : -1; \
+}
+
+#define RUN_SAT_U_ADD_IMM_FMT_1(T, x, IMM, expect) \
+ if (sat_u_add_imm##IMM##_##T##_fmt_1(x) != expect) __builtin_abort ()
+
/******************************************************************************/
/* Saturation Sub (Unsigned and Signed) */
/******************************************************************************/
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-1.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-1.c
new file mode 100644
index 00000000000..14e9b7595a8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm9_uint8_t_fmt_1:
+** addi\s+[atx][0-9]+,\s*a0,\s*9
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_1(uint8_t, 9)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-2.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-2.c
new file mode 100644
index 00000000000..c1a3c6ff21d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-2.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm3_uint16_t_fmt_1:
+** addi\s+[atx][0-9]+,\s*a0,\s*3
+** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48
+** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_1(uint16_t, 3)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-3.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-3.c
new file mode 100644
index 00000000000..21cc903c78e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-3.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm7_uint32_t_fmt_1:
+** addiw\s+[atx][0-9]+,\s*a0,\s*7
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_1(uint32_t, 7)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-4.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-4.c
new file mode 100644
index 00000000000..65693c32d79
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-4.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm8_uint64_t_fmt_1:
+** addi\s+[atx][0-9]+,\s*a0,\s*8
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_1(uint64_t, 8)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-1.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-1.c
new file mode 100644
index 00000000000..0ce546f8f84
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-1.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_1(uint8_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_1(uint8_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_1(uint8_t, 254)
+DEF_SAT_U_ADD_IMM_FMT_1(uint8_t, 255)
+
+#define T uint8_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_1(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 254, 254, },
+ { 1, 254, 255, },
+ { 2, 254, 255, },
+ { 0, 255, 255, },
+ { 1, 255, 255, },
+ { 2, 255, 255, },
+ { 255, 255, 255, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 254, d[3][2]);
+ RUN (T, d[4][0], 254, d[4][2]);
+ RUN (T, d[5][0], 254, d[5][2]);
+
+ RUN (T, d[6][0], 255, d[6][2]);
+ RUN (T, d[7][0], 255, d[7][2]);
+ RUN (T, d[8][0], 255, d[8][2]);
+ RUN (T, d[9][0], 255, d[9][2]);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-2.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-2.c
new file mode 100644
index 00000000000..090c76565ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_1(uint16_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_1(uint16_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_1(uint16_t, 65534)
+DEF_SAT_U_ADD_IMM_FMT_1(uint16_t, 65535)
+
+#define T uint16_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_1(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 65534, 65534, },
+ { 1, 65534, 65535, },
+ { 2, 65534, 65535, },
+ { 0, 65535, 65535, },
+ { 1, 65535, 65535, },
+ { 2, 65535, 65535, },
+ { 65535, 65535, 65535, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 65534, d[3][2]);
+ RUN (T, d[4][0], 65534, d[4][2]);
+ RUN (T, d[5][0], 65534, d[5][2]);
+
+ RUN (T, d[6][0], 65535, d[6][2]);
+ RUN (T, d[7][0], 65535, d[7][2]);
+ RUN (T, d[8][0], 65535, d[8][2]);
+ RUN (T, d[9][0], 65535, d[9][2]);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-3.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-3.c
new file mode 100644
index 00000000000..8dade742625
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-3.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_1(uint32_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_1(uint32_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_1(uint32_t, 4294967294)
+DEF_SAT_U_ADD_IMM_FMT_1(uint32_t, 4294967295)
+
+#define T uint32_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_1(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 4294967294, 4294967294, },
+ { 1, 4294967294, 4294967295, },
+ { 2, 4294967294, 4294967295, },
+ { 0, 4294967295, 4294967295, },
+ { 1, 4294967295, 4294967295, },
+ { 2, 4294967295, 4294967295, },
+ { 4294967295, 4294967295, 4294967295, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 4294967294, d[3][2]);
+ RUN (T, d[4][0], 4294967294, d[4][2]);
+ RUN (T, d[5][0], 4294967294, d[5][2]);
+
+ RUN (T, d[6][0], 4294967295, d[6][2]);
+ RUN (T, d[7][0], 4294967295, d[7][2]);
+ RUN (T, d[8][0], 4294967295, d[8][2]);
+ RUN (T, d[9][0], 4294967295, d[9][2]);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-4.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-4.c
new file mode 100644
index 00000000000..ace2df88e91
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-4.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_1(uint64_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_1(uint64_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_1(uint64_t, 18446744073709551614u)
+DEF_SAT_U_ADD_IMM_FMT_1(uint64_t, 18446744073709551615u)
+
+#define T uint64_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_1(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 18446744073709551614u, 18446744073709551614u, },
+ { 1, 18446744073709551614u, 18446744073709551615u, },
+ { 2, 18446744073709551614u, 18446744073709551615u, },
+ { 0, 18446744073709551615u, 18446744073709551615u, },
+ { 1, 18446744073709551615u, 18446744073709551615u, },
+ { 2, 18446744073709551615u, 18446744073709551615u, },
+ { 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 18446744073709551614u, d[3][2]);
+ RUN (T, d[4][0], 18446744073709551614u, d[4][2]);
+ RUN (T, d[5][0], 18446744073709551614u, d[5][2]);
+
+ RUN (T, d[6][0], 18446744073709551615u, d[6][2]);
+ RUN (T, d[7][0], 18446744073709551615u, d[7][2]);
+ RUN (T, d[8][0], 18446744073709551615u, d[8][2]);
+ RUN (T, d[9][0], 18446744073709551615u, d[9][2]);
+
+ return 0;
+}
--
2.34.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v1 2/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 2
2024-07-01 1:35 ` [PATCH v1 2/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 2 pan2.li
@ 2024-07-01 12:22 ` juzhe.zhong
0 siblings, 0 replies; 9+ messages in thread
From: juzhe.zhong @ 2024-07-01 12:22 UTC (permalink / raw)
To: pan2.li, gcc-patches; +Cc: kito.cheng, jeffreyalaw, Robin Dapp, pan2.li
[-- Attachment #1: Type: text/plain, Size: 14010 bytes --]
LGTM
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2024-07-01 09:35
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 2/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 2
From: Pan Li <pan2.li@intel.com>
This patch would like to add test cases for the unsigned scalar
.SAT_ADD IMM form 2. Aka:
Form 2:
#define DEF_SAT_U_ADD_IMM_FMT_2(T) \
T __attribute__((noinline)) \
sat_u_add_imm_##T##_fmt_1 (T x) \
{ \
return (T)(x + 9) < x ? -1 : (x + 9); \
}
DEF_SAT_U_ADD_IMM_FMT_2(uint64_t)
The below test is passed for this patch.
* The rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper test macro.
* gcc.target/riscv/sat_u_add_imm-5.c: New test.
* gcc.target/riscv/sat_u_add_imm-6.c: New test.
* gcc.target/riscv/sat_u_add_imm-7.c: New test.
* gcc.target/riscv/sat_u_add_imm-8.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-5.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-6.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-7.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-8.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 10 ++++
.../gcc.target/riscv/sat_u_add_imm-5.c | 19 ++++++++
.../gcc.target/riscv/sat_u_add_imm-6.c | 21 +++++++++
.../gcc.target/riscv/sat_u_add_imm-7.c | 18 ++++++++
.../gcc.target/riscv/sat_u_add_imm-8.c | 17 +++++++
.../gcc.target/riscv/sat_u_add_imm-run-5.c | 46 +++++++++++++++++++
.../gcc.target/riscv/sat_u_add_imm-run-6.c | 46 +++++++++++++++++++
.../gcc.target/riscv/sat_u_add_imm-run-7.c | 46 +++++++++++++++++++
.../gcc.target/riscv/sat_u_add_imm-run-8.c | 46 +++++++++++++++++++
9 files changed, 269 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-8.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-8.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index 4ec4ec36cc1..d94f0fd602c 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -67,9 +67,19 @@ sat_u_add_imm##IMM##_##T##_fmt_1 (T x) \
return (T)(x + IMM) >= x ? (x + IMM) : -1; \
}
+#define DEF_SAT_U_ADD_IMM_FMT_2(T, IMM) \
+T __attribute__((noinline)) \
+sat_u_add_imm##IMM##_##T##_fmt_2 (T x) \
+{ \
+ return (T)(x + IMM) < x ? -1 : (x + IMM); \
+}
+
#define RUN_SAT_U_ADD_IMM_FMT_1(T, x, IMM, expect) \
if (sat_u_add_imm##IMM##_##T##_fmt_1(x) != expect) __builtin_abort ()
+#define RUN_SAT_U_ADD_IMM_FMT_2(T, x, IMM, expect) \
+ if (sat_u_add_imm##IMM##_##T##_fmt_2(x) != expect) __builtin_abort ()
+
/******************************************************************************/
/* Saturation Sub (Unsigned and Signed) */
/******************************************************************************/
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-5.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-5.c
new file mode 100644
index 00000000000..19b502db6c9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-5.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm9_uint8_t_fmt_2:
+** addi\s+[atx][0-9]+,\s*a0,\s*9
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_2(uint8_t, 9)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-6.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-6.c
new file mode 100644
index 00000000000..0317370b67e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-6.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm3_uint16_t_fmt_2:
+** addi\s+[atx][0-9]+,\s*a0,\s*3
+** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48
+** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_2(uint16_t, 3)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-7.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-7.c
new file mode 100644
index 00000000000..044b821f7b5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-7.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm7_uint32_t_fmt_2:
+** addiw\s+[atx][0-9]+,\s*a0,\s*7
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_2(uint32_t, 7)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-8.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-8.c
new file mode 100644
index 00000000000..4eafb83c756
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-8.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm8_uint64_t_fmt_2:
+** addi\s+[atx][0-9]+,\s*a0,\s*8
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_2(uint64_t, 8)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-5.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-5.c
new file mode 100644
index 00000000000..8e8759c9825
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-5.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_2(uint8_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_2(uint8_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_2(uint8_t, 254)
+DEF_SAT_U_ADD_IMM_FMT_2(uint8_t, 255)
+
+#define T uint8_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_2(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 254, 254, },
+ { 1, 254, 255, },
+ { 2, 254, 255, },
+ { 0, 255, 255, },
+ { 1, 255, 255, },
+ { 2, 255, 255, },
+ { 255, 255, 255, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 254, d[3][2]);
+ RUN (T, d[4][0], 254, d[4][2]);
+ RUN (T, d[5][0], 254, d[5][2]);
+
+ RUN (T, d[6][0], 255, d[6][2]);
+ RUN (T, d[7][0], 255, d[7][2]);
+ RUN (T, d[8][0], 255, d[8][2]);
+ RUN (T, d[9][0], 255, d[9][2]);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-6.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-6.c
new file mode 100644
index 00000000000..7b6bd731234
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-6.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_2(uint16_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_2(uint16_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_2(uint16_t, 65534)
+DEF_SAT_U_ADD_IMM_FMT_2(uint16_t, 65535)
+
+#define T uint16_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_2(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 65534, 65534, },
+ { 1, 65534, 65535, },
+ { 2, 65534, 65535, },
+ { 0, 65535, 65535, },
+ { 1, 65535, 65535, },
+ { 2, 65535, 65535, },
+ { 65535, 65535, 65535, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 65534, d[3][2]);
+ RUN (T, d[4][0], 65534, d[4][2]);
+ RUN (T, d[5][0], 65534, d[5][2]);
+
+ RUN (T, d[6][0], 65535, d[6][2]);
+ RUN (T, d[7][0], 65535, d[7][2]);
+ RUN (T, d[8][0], 65535, d[8][2]);
+ RUN (T, d[9][0], 65535, d[9][2]);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-7.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-7.c
new file mode 100644
index 00000000000..80241527ee9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-7.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_2(uint32_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_2(uint32_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_2(uint32_t, 4294967294)
+DEF_SAT_U_ADD_IMM_FMT_2(uint32_t, 4294967295)
+
+#define T uint32_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_2(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 4294967294, 4294967294, },
+ { 1, 4294967294, 4294967295, },
+ { 2, 4294967294, 4294967295, },
+ { 0, 4294967295, 4294967295, },
+ { 1, 4294967295, 4294967295, },
+ { 2, 4294967295, 4294967295, },
+ { 4294967295, 4294967295, 4294967295, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 4294967294, d[3][2]);
+ RUN (T, d[4][0], 4294967294, d[4][2]);
+ RUN (T, d[5][0], 4294967294, d[5][2]);
+
+ RUN (T, d[6][0], 4294967295, d[6][2]);
+ RUN (T, d[7][0], 4294967295, d[7][2]);
+ RUN (T, d[8][0], 4294967295, d[8][2]);
+ RUN (T, d[9][0], 4294967295, d[9][2]);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-8.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-8.c
new file mode 100644
index 00000000000..4a76dbb6dde
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-8.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_2(uint64_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_2(uint64_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_2(uint64_t, 18446744073709551614u)
+DEF_SAT_U_ADD_IMM_FMT_2(uint64_t, 18446744073709551615u)
+
+#define T uint64_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_2(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 18446744073709551614u, 18446744073709551614u, },
+ { 1, 18446744073709551614u, 18446744073709551615u, },
+ { 2, 18446744073709551614u, 18446744073709551615u, },
+ { 0, 18446744073709551615u, 18446744073709551615u, },
+ { 1, 18446744073709551615u, 18446744073709551615u, },
+ { 2, 18446744073709551615u, 18446744073709551615u, },
+ { 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 18446744073709551614u, d[3][2]);
+ RUN (T, d[4][0], 18446744073709551614u, d[4][2]);
+ RUN (T, d[5][0], 18446744073709551614u, d[5][2]);
+
+ RUN (T, d[6][0], 18446744073709551615u, d[6][2]);
+ RUN (T, d[7][0], 18446744073709551615u, d[7][2]);
+ RUN (T, d[8][0], 18446744073709551615u, d[8][2]);
+ RUN (T, d[9][0], 18446744073709551615u, d[9][2]);
+
+ return 0;
+}
--
2.34.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v1 4/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 4
2024-07-01 1:35 ` [PATCH v1 4/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 4 pan2.li
@ 2024-07-01 12:22 ` juzhe.zhong
0 siblings, 0 replies; 9+ messages in thread
From: juzhe.zhong @ 2024-07-01 12:22 UTC (permalink / raw)
To: pan2.li, gcc-patches; +Cc: kito.cheng, jeffreyalaw, Robin Dapp, pan2.li
[-- Attachment #1: Type: text/plain, Size: 14632 bytes --]
LGTM
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2024-07-01 09:35
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 4/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 4
From: Pan Li <pan2.li@intel.com>
This patch would like to add test cases for the unsigned scalar
.SAT_ADD IMM form 4. Aka:
Form 4:
#define DEF_SAT_U_ADD_IMM_FMT_4(T) \
T __attribute__((noinline)) \
sat_u_add_imm_##T##_fmt_4 (T x) \
{ \
T ret; \
return __builtin_add_overflow (x, 9, &ret) == 0 ? ret : -1; \
}
DEF_SAT_U_ADD_IMM_FMT_4(uint64_t)
The below test is passed for this patch.
* The rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper test macro.
* gcc.target/riscv/sat_u_add_imm-13.c: New test.
* gcc.target/riscv/sat_u_add_imm-14.c: New test.
* gcc.target/riscv/sat_u_add_imm-15.c: New test.
* gcc.target/riscv/sat_u_add_imm-16.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-13.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-14.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-15.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-16.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 11 +++++
.../gcc.target/riscv/sat_u_add_imm-13.c | 19 ++++++++
.../gcc.target/riscv/sat_u_add_imm-14.c | 21 +++++++++
.../gcc.target/riscv/sat_u_add_imm-15.c | 18 ++++++++
.../gcc.target/riscv/sat_u_add_imm-16.c | 17 +++++++
.../gcc.target/riscv/sat_u_add_imm-run-13.c | 46 +++++++++++++++++++
.../gcc.target/riscv/sat_u_add_imm-run-14.c | 46 +++++++++++++++++++
.../gcc.target/riscv/sat_u_add_imm-run-15.c | 46 +++++++++++++++++++
.../gcc.target/riscv/sat_u_add_imm-run-16.c | 46 +++++++++++++++++++
9 files changed, 270 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-13.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-14.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-15.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-16.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-13.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-14.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-15.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-16.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index 83b294db476..75442c94dc1 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -82,6 +82,14 @@ sat_u_add_imm##IMM##_##T##_fmt_3 (T x) \
return __builtin_add_overflow (x, IMM, &ret) ? -1 : ret; \
}
+#define DEF_SAT_U_ADD_IMM_FMT_4(T, IMM) \
+T __attribute__((noinline)) \
+sat_u_add_imm##IMM##_##T##_fmt_4 (T x) \
+{ \
+ T ret; \
+ return __builtin_add_overflow (x, IMM, &ret) == 0 ? ret : -1; \
+}
+
#define RUN_SAT_U_ADD_IMM_FMT_1(T, x, IMM, expect) \
if (sat_u_add_imm##IMM##_##T##_fmt_1(x) != expect) __builtin_abort ()
@@ -91,6 +99,9 @@ sat_u_add_imm##IMM##_##T##_fmt_3 (T x) \
#define RUN_SAT_U_ADD_IMM_FMT_3(T, x, IMM, expect) \
if (sat_u_add_imm##IMM##_##T##_fmt_3(x) != expect) __builtin_abort ()
+#define RUN_SAT_U_ADD_IMM_FMT_4(T, x, IMM, expect) \
+ if (sat_u_add_imm##IMM##_##T##_fmt_4(x) != expect) __builtin_abort ()
+
/******************************************************************************/
/* Saturation Sub (Unsigned and Signed) */
/******************************************************************************/
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-13.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-13.c
new file mode 100644
index 00000000000..a3b2679233c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-13.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm9_uint8_t_fmt_4:
+** addi\s+[atx][0-9]+,\s*a0,\s*9
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_4(uint8_t, 9)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-14.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-14.c
new file mode 100644
index 00000000000..968534b74da
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-14.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm3_uint16_t_fmt_4:
+** addi\s+[atx][0-9]+,\s*a0,\s*3
+** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48
+** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_4(uint16_t, 3)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-15.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-15.c
new file mode 100644
index 00000000000..3918d215658
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-15.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm7_uint32_t_fmt_4:
+** addiw\s+[atx][0-9]+,\s*a0,\s*7
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_4(uint32_t, 7)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-16.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-16.c
new file mode 100644
index 00000000000..307b81589ee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-16.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm8_uint64_t_fmt_4:
+** addi\s+[atx][0-9]+,\s*a0,\s*8
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_4(uint64_t, 8)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-13.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-13.c
new file mode 100644
index 00000000000..872923ec5b9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-13.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_4(uint8_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_4(uint8_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_4(uint8_t, 254)
+DEF_SAT_U_ADD_IMM_FMT_4(uint8_t, 255)
+
+#define T uint8_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_4(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 254, 254, },
+ { 1, 254, 255, },
+ { 2, 254, 255, },
+ { 0, 255, 255, },
+ { 1, 255, 255, },
+ { 2, 255, 255, },
+ { 255, 255, 255, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 254, d[3][2]);
+ RUN (T, d[4][0], 254, d[4][2]);
+ RUN (T, d[5][0], 254, d[5][2]);
+
+ RUN (T, d[6][0], 255, d[6][2]);
+ RUN (T, d[7][0], 255, d[7][2]);
+ RUN (T, d[8][0], 255, d[8][2]);
+ RUN (T, d[9][0], 255, d[9][2]);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-14.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-14.c
new file mode 100644
index 00000000000..0b75206bede
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-14.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_4(uint16_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_4(uint16_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_4(uint16_t, 65534)
+DEF_SAT_U_ADD_IMM_FMT_4(uint16_t, 65535)
+
+#define T uint16_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_4(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 65534, 65534, },
+ { 1, 65534, 65535, },
+ { 2, 65534, 65535, },
+ { 0, 65535, 65535, },
+ { 1, 65535, 65535, },
+ { 2, 65535, 65535, },
+ { 65535, 65535, 65535, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 65534, d[3][2]);
+ RUN (T, d[4][0], 65534, d[4][2]);
+ RUN (T, d[5][0], 65534, d[5][2]);
+
+ RUN (T, d[6][0], 65535, d[6][2]);
+ RUN (T, d[7][0], 65535, d[7][2]);
+ RUN (T, d[8][0], 65535, d[8][2]);
+ RUN (T, d[9][0], 65535, d[9][2]);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-15.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-15.c
new file mode 100644
index 00000000000..e548d0c06b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-15.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_4(uint32_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_4(uint32_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_4(uint32_t, 4294967294)
+DEF_SAT_U_ADD_IMM_FMT_4(uint32_t, 4294967295)
+
+#define T uint32_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_4(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 4294967294, 4294967294, },
+ { 1, 4294967294, 4294967295, },
+ { 2, 4294967294, 4294967295, },
+ { 0, 4294967295, 4294967295, },
+ { 1, 4294967295, 4294967295, },
+ { 2, 4294967295, 4294967295, },
+ { 4294967295, 4294967295, 4294967295, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 4294967294, d[3][2]);
+ RUN (T, d[4][0], 4294967294, d[4][2]);
+ RUN (T, d[5][0], 4294967294, d[5][2]);
+
+ RUN (T, d[6][0], 4294967295, d[6][2]);
+ RUN (T, d[7][0], 4294967295, d[7][2]);
+ RUN (T, d[8][0], 4294967295, d[8][2]);
+ RUN (T, d[9][0], 4294967295, d[9][2]);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-16.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-16.c
new file mode 100644
index 00000000000..4335d827d13
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-16.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_4(uint64_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_4(uint64_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_4(uint64_t, 18446744073709551614u)
+DEF_SAT_U_ADD_IMM_FMT_4(uint64_t, 18446744073709551615u)
+
+#define T uint64_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_4(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 18446744073709551614u, 18446744073709551614u, },
+ { 1, 18446744073709551614u, 18446744073709551615u, },
+ { 2, 18446744073709551614u, 18446744073709551615u, },
+ { 0, 18446744073709551615u, 18446744073709551615u, },
+ { 1, 18446744073709551615u, 18446744073709551615u, },
+ { 2, 18446744073709551615u, 18446744073709551615u, },
+ { 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 18446744073709551614u, d[3][2]);
+ RUN (T, d[4][0], 18446744073709551614u, d[4][2]);
+ RUN (T, d[5][0], 18446744073709551614u, d[5][2]);
+
+ RUN (T, d[6][0], 18446744073709551615u, d[6][2]);
+ RUN (T, d[7][0], 18446744073709551615u, d[7][2]);
+ RUN (T, d[8][0], 18446744073709551615u, d[8][2]);
+ RUN (T, d[9][0], 18446744073709551615u, d[9][2]);
+
+ return 0;
+}
--
2.34.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* RE: [PATCH v1 1/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 1
2024-07-01 12:22 ` [PATCH v1 1/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 1 juzhe.zhong
@ 2024-07-01 12:34 ` Li, Pan2
0 siblings, 0 replies; 9+ messages in thread
From: Li, Pan2 @ 2024-07-01 12:34 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches; +Cc: kito.cheng, jeffreyalaw, Robin Dapp
[-- Attachment #1: Type: text/plain, Size: 14705 bytes --]
Committed the series, thanks Juzhe.
Pan
From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Monday, July 1, 2024 8:23 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: kito.cheng <kito.cheng@gmail.com>; jeffreyalaw <jeffreyalaw@gmail.com>; Robin Dapp <rdapp.gcc@gmail.com>; Li, Pan2 <pan2.li@intel.com>
Subject: Re: [PATCH v1 1/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 1
LGTM
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: pan2.li<mailto:pan2.li@intel.com>
Date: 2024-07-01 09:35
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; kito.cheng<mailto:kito.cheng@gmail.com>; jeffreyalaw<mailto:jeffreyalaw@gmail.com>; rdapp.gcc<mailto:rdapp.gcc@gmail.com>; Pan Li<mailto:pan2.li@intel.com>
Subject: [PATCH v1 1/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 1
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
This patch would like to add test cases for the unsigned scalar
.SAT_ADD IMM form 1. Aka:
Form 1:
#define DEF_SAT_U_ADD_IMM_FMT_1(T) \
T __attribute__((noinline)) \
sat_u_add_imm_##T##_fmt_1 (T x) \
{ \
return (T)(x + 9) >= x ? (x + 9) : -1; \
}
DEF_SAT_U_ADD_IMM_FMT_1(uint64_t)
The below test is passed for this patch.
* The rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper test macro.
* gcc.target/riscv/sat_u_add_imm-1.c: New test.
* gcc.target/riscv/sat_u_add_imm-2.c: New test.
* gcc.target/riscv/sat_u_add_imm-3.c: New test.
* gcc.target/riscv/sat_u_add_imm-4.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-1.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-2.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-3.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-4.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 10 ++++
.../gcc.target/riscv/sat_u_add_imm-1.c | 19 ++++++++
.../gcc.target/riscv/sat_u_add_imm-2.c | 21 +++++++++
.../gcc.target/riscv/sat_u_add_imm-3.c | 18 ++++++++
.../gcc.target/riscv/sat_u_add_imm-4.c | 17 +++++++
.../gcc.target/riscv/sat_u_add_imm-run-1.c | 46 +++++++++++++++++++
.../gcc.target/riscv/sat_u_add_imm-run-2.c | 46 +++++++++++++++++++
.../gcc.target/riscv/sat_u_add_imm-run-3.c | 46 +++++++++++++++++++
.../gcc.target/riscv/sat_u_add_imm-run-4.c | 46 +++++++++++++++++++
9 files changed, 269 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-4.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index 0c2e44af718..4ec4ec36cc1 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -60,6 +60,16 @@ sat_u_add_##T##_fmt_6 (T x, T y) \
#define RUN_SAT_U_ADD_FMT_5(T, x, y) sat_u_add_##T##_fmt_5(x, y)
#define RUN_SAT_U_ADD_FMT_6(T, x, y) sat_u_add_##T##_fmt_6(x, y)
+#define DEF_SAT_U_ADD_IMM_FMT_1(T, IMM) \
+T __attribute__((noinline)) \
+sat_u_add_imm##IMM##_##T##_fmt_1 (T x) \
+{ \
+ return (T)(x + IMM) >= x ? (x + IMM) : -1; \
+}
+
+#define RUN_SAT_U_ADD_IMM_FMT_1(T, x, IMM, expect) \
+ if (sat_u_add_imm##IMM##_##T##_fmt_1(x) != expect) __builtin_abort ()
+
/******************************************************************************/
/* Saturation Sub (Unsigned and Signed) */
/******************************************************************************/
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-1.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-1.c
new file mode 100644
index 00000000000..14e9b7595a8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm9_uint8_t_fmt_1:
+** addi\s+[atx][0-9]+,\s*a0,\s*9
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_1(uint8_t, 9)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-2.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-2.c
new file mode 100644
index 00000000000..c1a3c6ff21d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-2.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm3_uint16_t_fmt_1:
+** addi\s+[atx][0-9]+,\s*a0,\s*3
+** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48
+** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_1(uint16_t, 3)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-3.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-3.c
new file mode 100644
index 00000000000..21cc903c78e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-3.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm7_uint32_t_fmt_1:
+** addiw\s+[atx][0-9]+,\s*a0,\s*7
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_1(uint32_t, 7)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-4.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-4.c
new file mode 100644
index 00000000000..65693c32d79
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-4.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm8_uint64_t_fmt_1:
+** addi\s+[atx][0-9]+,\s*a0,\s*8
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_1(uint64_t, 8)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-1.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-1.c
new file mode 100644
index 00000000000..0ce546f8f84
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-1.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_1(uint8_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_1(uint8_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_1(uint8_t, 254)
+DEF_SAT_U_ADD_IMM_FMT_1(uint8_t, 255)
+
+#define T uint8_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_1(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 254, 254, },
+ { 1, 254, 255, },
+ { 2, 254, 255, },
+ { 0, 255, 255, },
+ { 1, 255, 255, },
+ { 2, 255, 255, },
+ { 255, 255, 255, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 254, d[3][2]);
+ RUN (T, d[4][0], 254, d[4][2]);
+ RUN (T, d[5][0], 254, d[5][2]);
+
+ RUN (T, d[6][0], 255, d[6][2]);
+ RUN (T, d[7][0], 255, d[7][2]);
+ RUN (T, d[8][0], 255, d[8][2]);
+ RUN (T, d[9][0], 255, d[9][2]);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-2.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-2.c
new file mode 100644
index 00000000000..090c76565ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_1(uint16_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_1(uint16_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_1(uint16_t, 65534)
+DEF_SAT_U_ADD_IMM_FMT_1(uint16_t, 65535)
+
+#define T uint16_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_1(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 65534, 65534, },
+ { 1, 65534, 65535, },
+ { 2, 65534, 65535, },
+ { 0, 65535, 65535, },
+ { 1, 65535, 65535, },
+ { 2, 65535, 65535, },
+ { 65535, 65535, 65535, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 65534, d[3][2]);
+ RUN (T, d[4][0], 65534, d[4][2]);
+ RUN (T, d[5][0], 65534, d[5][2]);
+
+ RUN (T, d[6][0], 65535, d[6][2]);
+ RUN (T, d[7][0], 65535, d[7][2]);
+ RUN (T, d[8][0], 65535, d[8][2]);
+ RUN (T, d[9][0], 65535, d[9][2]);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-3.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-3.c
new file mode 100644
index 00000000000..8dade742625
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-3.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_1(uint32_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_1(uint32_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_1(uint32_t, 4294967294)
+DEF_SAT_U_ADD_IMM_FMT_1(uint32_t, 4294967295)
+
+#define T uint32_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_1(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 4294967294, 4294967294, },
+ { 1, 4294967294, 4294967295, },
+ { 2, 4294967294, 4294967295, },
+ { 0, 4294967295, 4294967295, },
+ { 1, 4294967295, 4294967295, },
+ { 2, 4294967295, 4294967295, },
+ { 4294967295, 4294967295, 4294967295, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 4294967294, d[3][2]);
+ RUN (T, d[4][0], 4294967294, d[4][2]);
+ RUN (T, d[5][0], 4294967294, d[5][2]);
+
+ RUN (T, d[6][0], 4294967295, d[6][2]);
+ RUN (T, d[7][0], 4294967295, d[7][2]);
+ RUN (T, d[8][0], 4294967295, d[8][2]);
+ RUN (T, d[9][0], 4294967295, d[9][2]);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-4.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-4.c
new file mode 100644
index 00000000000..ace2df88e91
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-4.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_1(uint64_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_1(uint64_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_1(uint64_t, 18446744073709551614u)
+DEF_SAT_U_ADD_IMM_FMT_1(uint64_t, 18446744073709551615u)
+
+#define T uint64_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_1(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 18446744073709551614u, 18446744073709551614u, },
+ { 1, 18446744073709551614u, 18446744073709551615u, },
+ { 2, 18446744073709551614u, 18446744073709551615u, },
+ { 0, 18446744073709551615u, 18446744073709551615u, },
+ { 1, 18446744073709551615u, 18446744073709551615u, },
+ { 2, 18446744073709551615u, 18446744073709551615u, },
+ { 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 18446744073709551614u, d[3][2]);
+ RUN (T, d[4][0], 18446744073709551614u, d[4][2]);
+ RUN (T, d[5][0], 18446744073709551614u, d[5][2]);
+
+ RUN (T, d[6][0], 18446744073709551615u, d[6][2]);
+ RUN (T, d[7][0], 18446744073709551615u, d[7][2]);
+ RUN (T, d[8][0], 18446744073709551615u, d[8][2]);
+ RUN (T, d[9][0], 18446744073709551615u, d[9][2]);
+
+ return 0;
+}
--
2.34.1
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2024-07-01 1:35 [PATCH v1 1/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 1 pan2.li
2024-07-01 1:35 ` [PATCH v1 2/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 2 pan2.li
2024-07-01 12:22 ` juzhe.zhong
2024-07-01 1:35 ` [PATCH v1 3/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 3 pan2.li
2024-07-01 12:22 ` juzhe.zhong
2024-07-01 1:35 ` [PATCH v1 4/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 4 pan2.li
2024-07-01 12:22 ` juzhe.zhong
2024-07-01 12:22 ` [PATCH v1 1/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 1 juzhe.zhong
2024-07-01 12:34 ` Li, Pan2
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