From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by sourceware.org (Postfix) with ESMTPS id 20F453858CDB for ; Fri, 3 Mar 2023 02:34:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 20F453858CDB Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677810867; x=1709346867; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=QJzq6cSUjcjGresgJVyl81prTUHYQiGaf55ZpMhyY4s=; b=OYeYunE5HYscutq6eBHF/PhhL68QqyU3mXJWx688HRZ05FFWyvVEFmeJ pRQI5ZQz/++kN6q1rOoCfcVW/O3I/Frx8UdBWDREKmYgOHQbC7rnmzqiZ 6f2ceU/9xQdf8RrsSnXJmC08K1PNJN7OtQuNkaNOgKL6ts1Nt+eY0b7wd QGsg2YCbM2R2USFVg5QeYCDyGsPxVacyuHerPa3bk8aF+5oJr0og2SP98 cukH0e1fsY/uK369zdG+YTwBnlA2Ca7V7Y0hrWUBOEhMGjxjfTGsTYeZs aabYpjmVNKOZBShcHkAA5xzuST+O+TkPSjyOzHR0vfdfMg/ubGNL+ABC1 Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10637"; a="314588549" X-IronPort-AV: E=Sophos;i="5.98,229,1673942400"; d="scan'208";a="314588549" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Mar 2023 18:34:25 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10637"; a="785099809" X-IronPort-AV: E=Sophos;i="5.98,229,1673942400"; d="scan'208";a="785099809" Received: from fmsmsx602.amr.corp.intel.com ([10.18.126.82]) by fmsmga002.fm.intel.com with ESMTP; 02 Mar 2023 18:34:25 -0800 Received: from fmsmsx610.amr.corp.intel.com (10.18.126.90) by fmsmsx602.amr.corp.intel.com (10.18.126.82) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 2 Mar 2023 18:34:25 -0800 Received: from fmsedg601.ED.cps.intel.com (10.1.192.135) by fmsmsx610.amr.corp.intel.com (10.18.126.90) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21 via Frontend Transport; Thu, 2 Mar 2023 18:34:25 -0800 Received: from NAM02-SN1-obe.outbound.protection.outlook.com (104.47.57.48) by edgegateway.intel.com (192.55.55.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.21; Thu, 2 Mar 2023 18:34:24 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=WO6SBDDpv2wi+2VpIueylT7Q+hkAths0/g+gDkF8MmXzXca1sleuKBlqN+D5riCGZEyJDxny5nXzfHFT3USzN8SExB7W0WNndm1R0YpGZJaHbIivYQx5jtS//7G0FojpKty1hZ7ucIzmmK11sa5Vl84bMqib2rmGl6sGipKXdDVKOpkjDP8uaq03RQBIsToalUvViAnVd7Bf4Vg/qFtRFO8Hwvm7iPdWF0LVaaqanxQ8FqphnBbycvbUBT+yPCxpJf6U3+sinGHAdqgJgRxWQssen3N0CsYhYMOYrktB8cNillFQHmvSXADI7+bQDL7rrxvbll4EQ76OcDnj5xkuNA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=3ZVbhdC9IT45V99RZb0yTZ1xj349O03mh/pYXAPgTMo=; b=nLc4OSJmZJz4k6bXnMtJKBg2eoFJfChkU/0H7Q19cozRe9O5lkwS9JOEQraHhShJUUZC6JR/AzaTOvXRseZsvq5Tz52+JixyqX+RTBC8qWrWFFXrVKsAsReZOVT1cSXKPTjev8iuZa+NF5H0gZdn1Wbtd9/olYe3PubFdkRNF3NZpDjTLYa31Hd/q6i5xmg4/HMKoFyj5xMDNz5NJvflwdhNkbJkUj5+xYiVkIhRawf0oW/pp9RlbeuRGRWZTrEnOJmpom9r29+kThOWFDg4M+1hJWQkaDNV7PEb9Fk13RVJTZRXMMZUUuneF12OZX9UeXXbcnR+VxNmSbl7IeU6cw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Received: from MW5PR11MB5908.namprd11.prod.outlook.com (2603:10b6:303:194::10) by SA0PR11MB4639.namprd11.prod.outlook.com (2603:10b6:806:70::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6156.18; Fri, 3 Mar 2023 02:34:22 +0000 Received: from MW5PR11MB5908.namprd11.prod.outlook.com ([fe80::7ad:494f:ca70:719]) by MW5PR11MB5908.namprd11.prod.outlook.com ([fe80::7ad:494f:ca70:719%8]) with mapi id 15.20.6134.030; Fri, 3 Mar 2023 02:34:22 +0000 From: "Li, Pan2" To: Richard Sandiford CC: "gcc-patches@gcc.gnu.org" , "juzhe.zhong@rivai.ai" , "kito.cheng@sifive.com" , "rguenther@suse.de" Subject: RE: [PATCH v2] RISC-V: Bugfix for rvv bool mode precision adjustment Thread-Topic: [PATCH v2] RISC-V: Bugfix for rvv bool mode precision adjustment Thread-Index: AQHZTMulGilusx36E0e85FwsUTAq167nS4sngABBVkCAAEjMuYAAgWpQ Date: Fri, 3 Mar 2023 02:34:21 +0000 Message-ID: References: <20230302055538.730932-1-pan2.li@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: MW5PR11MB5908:EE_|SA0PR11MB4639:EE_ x-ms-office365-filtering-correlation-id: c9aaca42-cb72-446e-7b2f-08db1b8fcc00 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: yHRi8uNSK9iNBbelo1FQjkhP2Cj+ssUJdsw2vmiFO8vMDvHSRl9qJTw0v3fZNSoostHUE/K0JGqPBZC+ReQmj9pPxWVa0ujJbCrAnMVZSa7WGp5Rc6tcrUM3Fg1jb+NPixJ7XpUPL3OOCLsHgQtfUaPA1DfvR1uWci/22Vb5d+MC6tHZLVRY9ekQUN0GF+68fKSp+O1pM7IKroe/rxpmhbBymVusifBeNWl8R7G12gICBOo7W+HLmMER2e+PnQB2lft1GMfKHm0uQKX6x8poi5Pu2hDBehNEeYowm1Qlc2XkV3VDDSS/m+gprIC3nl+aDSfSn/CfsJ0552CtM7JlOUdyTLBmhxqZqEieqhugs2vTEfyx6rmMFGfJ3iz4bcxuOtUi48h3eLQUZgZrLvRuJv5BAMxIRvqEJp2yqPo7PfLZwIOt/rmbG7BV+tWdBOgaldZHUFyCTqqwq0dLkqjGwmAeeP3EP8J4V82TSO+OdAaR3bkgErOdw3WzZQf+6l2WJpsD+wwV9T0UZ2r29Iqh10aX4eB48fuqY6IahP02De3VSwXi0gfsE0+dsrt6YP8hJP/Q93mFbNggPng1M0JpKJVR+/mz3JbUR4qVlaV/6N80/EA9o30JpJROW1ZO/YnUj6voOJzZDYnJhuGcZw/xazEi7yqKIJWaKcWIxnAAOOIZ0HALMoWPXnoJM2sKIsY/ x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MW5PR11MB5908.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230025)(39860400002)(376002)(366004)(346002)(396003)(136003)(451199018)(84970400001)(83380400001)(66446008)(38100700002)(64756008)(33656002)(4326008)(52536014)(122000001)(5660300002)(8936002)(86362001)(82960400001)(478600001)(55016003)(38070700005)(6916009)(26005)(966005)(9686003)(186003)(53546011)(71200400001)(6506007)(66556008)(2906002)(66476007)(8676002)(7696005)(30864003)(316002)(66946007)(76116006)(41300700001)(54906003)(579004)(559001);DIR:OUT;SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?OGQQXP+lGbrWn5iireJm/Eb68jbYDT3+TaAVBBzH3l0kJyqu4VoWIuT6llvZ?= =?us-ascii?Q?aFHJYof6PnAu6AFpySqKVUkSxCgcVWSV94szFQQG2ggP/HljkhBVuuZ1igg8?= =?us-ascii?Q?kpv8lmgKoV1LFw4PTTQxvNByqA+ai6MQrKh6jexRtutzgCZYo0AYxe4tpO5H?= =?us-ascii?Q?hkhu6GNOgXcSMtDHYA8CDDHBC8vM4OAV/+6uiF2dMSKBG8WtxTDU9LC9kxmT?= =?us-ascii?Q?cVrdk2rxj/GhdKCwu8bAmq0mXc6QKOLGEjz0ZgHvoltkBm3PwhZYVi9uYk6T?= =?us-ascii?Q?TROUiqTT4TLxSDVFjAUSNc7TvA9bRf5GufgDKzz+jp6VfD9QBbAlVP+HGs1Y?= =?us-ascii?Q?LO9vocBzJGOpx4shWP8l+vKcVASTkjFCoq/4zSg+4rb6R+IyUxqeJmdnW0bK?= =?us-ascii?Q?fCDzrG49AOYYTY3Bz912VXHVFmaxF8QHCaxxBrndO0u2ZCrhzMZtHbmYBnMK?= =?us-ascii?Q?LojnX7hA53gSSb8grDsUob3x8qykOnoN1X7+2uWwQ/BBI53SjfAqmyUpLJzq?= =?us-ascii?Q?Fa3k2ETaRxs6fQqguWwF5k76M72hnZdvn61zQGJy7kha5zGxwsq7ikkIxJZS?= =?us-ascii?Q?rvO4lQsbC43nKYZRJiRkLqOR6zzS0NbZUB0c4ka0y9gneW3AkrIifPx2N5SP?= =?us-ascii?Q?yIMdhPlGUi7twTm3tGjmy/jYJqB8xQ7iA29yxxZggReoU6vTOcJbR2baAApb?= =?us-ascii?Q?LqmVccg+s1nRdtHCqz44OZ+d7PYBjOhYdHRZzHtPJ/X22B/f52ndqmvlsMcM?= =?us-ascii?Q?fUruZvpC6+vsxs2zl+/iopYgNow+AZAwpmuMSbG9d7aNTGtM7CGh2TB7Vvyt?= =?us-ascii?Q?NPAnBwIyN56NzFMX5P76wnDOmbaiZwDL3QsH9WbBqfgMRdiXUIjDluqyl1mH?= =?us-ascii?Q?tZPxRbha95wLoSRIyHfkw4seoBKNUfxt7jdsOjFcQVhB2O2xEmlZcLht4sBK?= =?us-ascii?Q?PY2m41dQoWNGPAG0A6l4V8dz2szFcm+0UEz0z6GW1QxX3z9UpuvBt6c1U7m0?= =?us-ascii?Q?WsXPeEojMmD1xrDBQ0GAi63XJXlnc5IqqGMniXKrSLJQnOApsvIFaNl5d3qF?= =?us-ascii?Q?TKUZozmZRCiQsADeYELK5PMXjI2DcTX+lR5Be+DWYIfnKtAH/EVdn6Wi8YjZ?= =?us-ascii?Q?XlJmurNtu7cr7kb8G6nZ2QoGLOGApE9/Fn+kkPAf80o+3ISbsEpCagWjD4vX?= =?us-ascii?Q?8dGouRxaiRFEAyLfKbvc4TdMzWfNZt7ZQbq11CWnLQfcBxt37BnmWtK8OqUS?= =?us-ascii?Q?x13GMGlGdRIybUJ8xKlk7KZjthrd9qLd6HsM7vorNjh0sj2k4aKiQ8pD+HTk?= =?us-ascii?Q?Rbb60AIx8YN7vC15jPAuer9BvoMLjNsQ+8CiQReq4kY7nMyq6H1Oh5Wz2Aid?= =?us-ascii?Q?QTI9RET8G0SF8XwMhOkDKzXCW5HN7MbfAPSX3JcHnyIrA5rXRbB4Fika3z1s?= =?us-ascii?Q?GXBIh645MpZRaZIXwp3Q0W+0GoC/V7K+jSl/WRUOe+PT3QhwnIZVTAdk5b5/?= =?us-ascii?Q?ZI2WMCqW5udSA4SBrghZtH+jD/PQo+CM0wlohztCev08c8ZdtKr5SQ5qlVTX?= =?us-ascii?Q?TuLMSqh4lvQt92Sd7GM=3D?= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MW5PR11MB5908.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: c9aaca42-cb72-446e-7b2f-08db1b8fcc00 X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Mar 2023 02:34:21.9757 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: NM4MjfCCAMHar+P0G0XFC/aumEHE7FpP4YcuQwXPGeRW3YpYOa8+QANNpRZeMyO7vE1u7WLqZOipZ1frMdGf7A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR11MB4639 X-OriginatorOrg: intel.com X-Spam-Status: No, score=-9.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,SCC_10_SHORT_WORD_LINES,SCC_20_SHORT_WORD_LINES,SCC_35_SHORT_WORD_LINES,SCC_5_SHORT_WORD_LINES,SPF_HELO_PASS,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Got it. Thank you and very appreciate for your help and patient. Updated th= e PATCH to below link. https://gcc.gnu.org/pipermail/gcc-patches/2023-March/613257.html Pan -----Original Message----- From: Richard Sandiford =20 Sent: Friday, March 3, 2023 1:55 AM To: Li, Pan2 Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; kito.cheng@sifive.com; r= guenther@suse.de Subject: Re: [PATCH v2] RISC-V: Bugfix for rvv bool mode precision adjustme= nt "Li, Pan2" writes: > Oops, looks I missed that part for assertion. Thank you for coaching. > Added and tested the below changes at the end of emit_mode_adjustments al= ready but looks we may have other problems about the size, the precision an= d the C types. > > Looks like I need to hold this PATCH for a while until we have a conclusi= on. Feel free to let me know if there is mistake or misleading. > > +=20 > + for_all_modes (c, m) > + printf (" gcc_checking_assert (!mode_size[E_%smode].is_constant()" > + " || mode_size[E_%smode].coeffs[0] !=3D -1);\n", m->name,=20 > + m->name); > + Using: gcc_assert (maybe_ne (mode_size[E_%smode], -1)); would be simpler. We might as well make it a full assert (rather than a ch= ecking assert) because this code isn't executed very often. Thanks, Richard > > Thank you and have a nice day! > > Pan > > > -----Original Message----- > From: Richard Sandiford > Sent: Thursday, March 2, 2023 5:44 PM > To: Li, Pan2 > Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai;=20 > kito.cheng@sifive.com; rguenther@suse.de > Subject: Re: [PATCH v2] RISC-V: Bugfix for rvv bool mode precision=20 > adjustment > > pan2.li@intel.com writes: >> From: Pan Li >> >> Fix the bug of the rvv bool mode precision with the adjustment. >> The bits size of vbool*_t will be adjusted to >> [1, 2, 4, 8, 16, 32, 64] according to the rvv spec 1.0 isa. The >> adjusted mode precison of vbool*_t will help underlying pass to >> make the right decision for both the correctness and optimization. >> >> Given below sample code: >> void test_1(int8_t * restrict in, int8_t * restrict out) >> { >> vbool8_t v2 =3D *(vbool8_t*)in; >> vbool16_t v5 =3D *(vbool16_t*)in; >> *(vbool16_t*)(out + 200) =3D v5; >> *(vbool8_t*)(out + 100) =3D v2; >> } >> >> Before the precision adjustment: >> addi a4,a1,100 >> vsetvli a5,zero,e8,m1,ta,ma >> addi a1,a1,200 >> vlm.v v24,0(a0) >> vsm.v v24,0(a4) >> // Need one vsetvli and vlm.v for correctness here. >> vsm.v v24,0(a1) >> >> After the precision adjustment: >> csrr t0,vlenb >> slli t1,t0,1 >> csrr a3,vlenb >> sub sp,sp,t1 >> slli a4,a3,1 >> add a4,a4,sp >> sub a3,a4,a3 >> vsetvli a5,zero,e8,m1,ta,ma >> addi a2,a1,200 >> vlm.v v24,0(a0) >> vsm.v v24,0(a3) >> addi a1,a1,100 >> vsetvli a4,zero,e8,mf2,ta,ma >> csrr t0,vlenb >> vlm.v v25,0(a3) >> vsm.v v25,0(a2) >> slli t1,t0,1 >> vsetvli a5,zero,e8,m1,ta,ma >> vsm.v v24,0(a1) >> add sp,sp,t1 >> jr ra >> >> However, there may be some optimization opportunates after >> the mode precision adjustment. It can be token care of in >> the RISC-V backend in the underlying separted PR(s). >> >> PR 108185 >> PR 108654 >> >> gcc/ChangeLog: >> >> * config/riscv/riscv-modes.def (ADJUST_PRECISION): >> * config/riscv/riscv.cc (riscv_v_adjust_precision): >> * config/riscv/riscv.h (riscv_v_adjust_precision): >> * genmodes.cc (ADJUST_PRECISION): >> (emit_mode_adjustments): >> >> gcc/testsuite/ChangeLog: >> >> * gcc.target/riscv/pr108185-1.c: New test. >> * gcc.target/riscv/pr108185-2.c: New test. >> * gcc.target/riscv/pr108185-3.c: New test. >> * gcc.target/riscv/pr108185-4.c: New test. >> * gcc.target/riscv/pr108185-5.c: New test. >> * gcc.target/riscv/pr108185-6.c: New test. >> * gcc.target/riscv/pr108185-7.c: New test. >> * gcc.target/riscv/pr108185-8.c: New test. >> >> Signed-off-by: Pan Li >> --- >> gcc/config/riscv/riscv-modes.def | 8 +++ >> gcc/config/riscv/riscv.cc | 12 ++++ >> gcc/config/riscv/riscv.h | 1 + >> gcc/genmodes.cc | 20 +++++- >> gcc/testsuite/gcc.target/riscv/pr108185-1.c | 68 ++++++++++++++++++=20 >> gcc/testsuite/gcc.target/riscv/pr108185-2.c | 68 ++++++++++++++++++=20 >> gcc/testsuite/gcc.target/riscv/pr108185-3.c | 68 ++++++++++++++++++=20 >> gcc/testsuite/gcc.target/riscv/pr108185-4.c | 68 ++++++++++++++++++=20 >> gcc/testsuite/gcc.target/riscv/pr108185-5.c | 68 ++++++++++++++++++=20 >> gcc/testsuite/gcc.target/riscv/pr108185-6.c | 68 ++++++++++++++++++=20 >> gcc/testsuite/gcc.target/riscv/pr108185-7.c | 68 ++++++++++++++++++=20 >> gcc/testsuite/gcc.target/riscv/pr108185-8.c | 77=20 >> +++++++++++++++++++++ >> 12 files changed, 592 insertions(+), 2 deletions(-) create mode >> 100644 gcc/testsuite/gcc.target/riscv/pr108185-1.c >> create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-2.c >> create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-3.c >> create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-4.c >> create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-5.c >> create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-6.c >> create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-7.c >> create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-8.c >> >> diff --git a/gcc/config/riscv/riscv-modes.def >> b/gcc/config/riscv/riscv-modes.def >> index d5305efa8a6..110bddce851 100644 >> --- a/gcc/config/riscv/riscv-modes.def >> +++ b/gcc/config/riscv/riscv-modes.def >> @@ -72,6 +72,14 @@ ADJUST_BYTESIZE (VNx16BI, riscv_vector_chunks *=20 >> riscv_bytes_per_vector_chunk); ADJUST_BYTESIZE (VNx32BI,=20 >> riscv_vector_chunks * riscv_bytes_per_vector_chunk); ADJUST_BYTESIZE=20 >> (VNx64BI, riscv_v_adjust_nunits (VNx64BImode, 8)); >> =20 >> +ADJUST_PRECISION (VNx1BI, riscv_v_adjust_precision (VNx1BImode, 1));=20 >> +ADJUST_PRECISION (VNx2BI, riscv_v_adjust_precision (VNx2BImode, 2));=20 >> +ADJUST_PRECISION (VNx4BI, riscv_v_adjust_precision (VNx4BImode, 4));=20 >> +ADJUST_PRECISION (VNx8BI, riscv_v_adjust_precision (VNx8BImode, 8));=20 >> +ADJUST_PRECISION (VNx16BI, riscv_v_adjust_precision (VNx16BImode,=20 >> +16)); ADJUST_PRECISION (VNx32BI, riscv_v_adjust_precision=20 >> +(VNx32BImode, 32)); ADJUST_PRECISION (VNx64BI,=20 >> +riscv_v_adjust_precision (VNx64BImode, 64)); >> + >> /* >> | Mode | MIN_VLEN=3D32 | MIN_VLEN=3D32 | MIN_VLEN=3D64 | MIN_= VLEN=3D64 | >> | | LMUL | SEW/LMUL | LMUL | SEW/LMUL = | >> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc=20 >> index f11b7949a49..ac5c2527fde 100644 >> --- a/gcc/config/riscv/riscv.cc >> +++ b/gcc/config/riscv/riscv.cc >> @@ -1003,6 +1003,18 @@ riscv_v_adjust_nunits (machine_mode mode, int sca= le) >> return scale; >> } >> =20 >> +/* Call from ADJUST_PRECISION in riscv-modes.def. Return the correct >> + PRECISION size for corresponding machine_mode. */ >> + >> +poly_int64 >> +riscv_v_adjust_precision (machine_mode mode, int scale) { >> + if (riscv_v_ext_vector_mode_p (mode)) >> + return riscv_vector_chunks * scale; >> + >> + return scale; >> +} >> + >> /* Return true if X is a valid address for machine mode MODE. If it is= , >> fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in >> effect. */ >> diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h=20 >> index 5bc7f2f467d..15b9317a8ce 100644 >> --- a/gcc/config/riscv/riscv.h >> +++ b/gcc/config/riscv/riscv.h >> @@ -1025,6 +1025,7 @@ extern unsigned riscv_stack_boundary; extern=20 >> unsigned riscv_bytes_per_vector_chunk; extern poly_uint16=20 >> riscv_vector_chunks; extern poly_int64 riscv_v_adjust_nunits (enum=20 >> machine_mode, int); >> +extern poly_int64 riscv_v_adjust_precision (enum machine_mode, int); >> /* The number of bits and bytes in a RVV vector. */ #define=20 >> BITS_PER_RISCV_VECTOR (poly_uint16 (riscv_vector_chunks *=20 >> riscv_bytes_per_vector_chunk * 8)) #define BYTES_PER_RISCV_VECTOR >> (poly_uint16 (riscv_vector_chunks * riscv_bytes_per_vector_chunk))=20 >> diff --git a/gcc/genmodes.cc b/gcc/genmodes.cc index >> 2d418f09aab..3452d8fb878 100644 >> --- a/gcc/genmodes.cc >> +++ b/gcc/genmodes.cc >> @@ -114,6 +114,7 @@ static struct mode_adjust *adj_alignment; static=20 >> struct mode_adjust *adj_format; static struct mode_adjust *adj_ibit;=20 >> static struct mode_adjust *adj_fbit; >> +static struct mode_adjust *adj_precision; >> =20 >> /* Mode class operations. */ >> static enum mode_class >> @@ -819,6 +820,7 @@ make_vector_mode (enum mode_class bclass, >> #define ADJUST_NUNITS(M, X) _ADD_ADJUST (nunits, M, X, RANDOM, RANDO= M) >> #define ADJUST_BYTESIZE(M, X) _ADD_ADJUST (bytesize, M, X, RANDOM, >> RANDOM) #define ADJUST_ALIGNMENT(M, X) _ADD_ADJUST (alignment, M, X,=20 >> RANDOM, RANDOM) >> +#define ADJUST_PRECISION(M, X) _ADD_ADJUST (precision, M, X, RANDOM, >> +RANDOM) >> #define ADJUST_FLOAT_FORMAT(M, X) _ADD_ADJUST (format, M, X, FLOAT, = FLOAT) >> #define ADJUST_IBIT(M, X) _ADD_ADJUST (ibit, M, X, ACCUM, UACCUM)=20 >> #define ADJUST_FBIT(M, X) _ADD_ADJUST (fbit, M, X, FRACT, UACCUM) @@ >> -1829,8 +1831,9 @@ emit_mode_adjustments (void) >> " (mode_precision[E_%smode], mode_nunits[E_%smode]);\n", >> m->name, m->name); >> printf (" mode_precision[E_%smode] =3D ps * old_factor;\n", m-= >name); >> - printf (" mode_size[E_%smode] =3D exact_div (mode_precision[E_= %smode]," >> - " BITS_PER_UNIT);\n", m->name, m->name); >> + printf (" if (!multiple_p (mode_precision[E_%smode]," >> + " BITS_PER_UNIT, &mode_size[E_%smode]))\n", m->name, m->name); >> + printf (" mode_size[E_%smode] =3D -1;\n", m->name); > > Following up from what I said yesterday, I think we need to insert code t= o assert that, once all mode adjustments are complete, no mode_size is stil= l -1. This would go at the end of emit_mode_adjustments. > I guess for now it could be restricted to the modes in adj_nunits (if tha= t's simpler). > > Thanks, > Richard > >> printf (" mode_nunits[E_%smode] =3D ps;\n", m->name); >> printf (" adjust_mode_mask (E_%smode);\n", m->name); >> printf (" }\n"); >> @@ -1963,6 +1966,19 @@ emit_mode_adjustments (void) >> printf ("\n /* %s:%d */\n REAL_MODE_FORMAT (E_%smode) =3D %s;\n", >> a->file, a->line, a->mode->name, a->adjustment); >> =20 >> + /* Adjust precision to the actual bits size. */ >> + for (a =3D adj_precision; a; a =3D a->next) >> + switch (a->mode->cl) >> + { >> + case MODE_VECTOR_BOOL: >> + printf ("\n /* %s:%d. */\n ps =3D %s;\n", a->file, a->line, >> + a->adjustment); >> + printf (" mode_precision[E_%smode] =3D ps;\n", a->mode->name); >> + break; >> + default: >> + break; >> + } >> + >> puts ("}"); >> } >> =20 >> diff --git a/gcc/testsuite/gcc.target/riscv/pr108185-1.c >> b/gcc/testsuite/gcc.target/riscv/pr108185-1.c >> new file mode 100644 >> index 00000000000..e70960c5b6d >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/riscv/pr108185-1.c >> @@ -0,0 +1,68 @@ >> +/* { dg-do compile } */ >> +/* { dg-options "-march=3Drv64gcv -mabi=3Dlp64 -O3" } */ >> + >> +#include "riscv_vector.h" >> + >> +void >> +test_vbool1_then_vbool2(int8_t * restrict in, int8_t * restrict out) { >> + vbool1_t v1 =3D *(vbool1_t*)in; >> + vbool2_t v2 =3D *(vbool2_t*)in; >> + >> + *(vbool1_t*)(out + 100) =3D v1; >> + *(vbool2_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool1_then_vbool4(int8_t * restrict in, int8_t * restrict out) { >> + vbool1_t v1 =3D *(vbool1_t*)in; >> + vbool4_t v2 =3D *(vbool4_t*)in; >> + >> + *(vbool1_t*)(out + 100) =3D v1; >> + *(vbool4_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool1_then_vbool8(int8_t * restrict in, int8_t * restrict out) { >> + vbool1_t v1 =3D *(vbool1_t*)in; >> + vbool8_t v2 =3D *(vbool8_t*)in; >> + >> + *(vbool1_t*)(out + 100) =3D v1; >> + *(vbool8_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool1_then_vbool16(int8_t * restrict in, int8_t * restrict out) { >> + vbool1_t v1 =3D *(vbool1_t*)in; >> + vbool16_t v2 =3D *(vbool16_t*)in; >> + >> + *(vbool1_t*)(out + 100) =3D v1; >> + *(vbool16_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool1_then_vbool32(int8_t * restrict in, int8_t * restrict out) { >> + vbool1_t v1 =3D *(vbool1_t*)in; >> + vbool32_t v2 =3D *(vbool32_t*)in; >> + >> + *(vbool1_t*)(out + 100) =3D v1; >> + *(vbool32_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool1_then_vbool64(int8_t * restrict in, int8_t * restrict out) { >> + vbool1_t v1 =3D *(vbool1_t*)in; >> + vbool64_t v2 =3D *(vbool64_t*)in; >> + >> + *(vbool1_t*)(out + 100) =3D v1; >> + *(vbool64_t*)(out + 200) =3D v2; >> +} >> + >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m8,\s*ta,\s*ma} 6 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m4,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m2,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 18 } } */ >> diff --git a/gcc/testsuite/gcc.target/riscv/pr108185-2.c >> b/gcc/testsuite/gcc.target/riscv/pr108185-2.c >> new file mode 100644 >> index 00000000000..dcc7a644a88 >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/riscv/pr108185-2.c >> @@ -0,0 +1,68 @@ >> +/* { dg-do compile } */ >> +/* { dg-options "-march=3Drv64gcv -mabi=3Dlp64 -O3" } */ >> + >> +#include "riscv_vector.h" >> + >> +void >> +test_vbool2_then_vbool1(int8_t * restrict in, int8_t * restrict out) { >> + vbool2_t v1 =3D *(vbool2_t*)in; >> + vbool1_t v2 =3D *(vbool1_t*)in; >> + >> + *(vbool2_t*)(out + 100) =3D v1; >> + *(vbool1_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool2_then_vbool4(int8_t * restrict in, int8_t * restrict out) { >> + vbool2_t v1 =3D *(vbool2_t*)in; >> + vbool4_t v2 =3D *(vbool4_t*)in; >> + >> + *(vbool2_t*)(out + 100) =3D v1; >> + *(vbool4_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool2_then_vbool8(int8_t * restrict in, int8_t * restrict out) { >> + vbool2_t v1 =3D *(vbool2_t*)in; >> + vbool8_t v2 =3D *(vbool8_t*)in; >> + >> + *(vbool2_t*)(out + 100) =3D v1; >> + *(vbool8_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool2_then_vbool16(int8_t * restrict in, int8_t * restrict out) { >> + vbool2_t v1 =3D *(vbool2_t*)in; >> + vbool16_t v2 =3D *(vbool16_t*)in; >> + >> + *(vbool2_t*)(out + 100) =3D v1; >> + *(vbool16_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool2_then_vbool32(int8_t * restrict in, int8_t * restrict out) { >> + vbool2_t v1 =3D *(vbool2_t*)in; >> + vbool32_t v2 =3D *(vbool32_t*)in; >> + >> + *(vbool2_t*)(out + 100) =3D v1; >> + *(vbool32_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool2_then_vbool64(int8_t * restrict in, int8_t * restrict out) { >> + vbool2_t v1 =3D *(vbool2_t*)in; >> + vbool64_t v2 =3D *(vbool64_t*)in; >> + >> + *(vbool2_t*)(out + 100) =3D v1; >> + *(vbool64_t*)(out + 200) =3D v2; >> +} >> + >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m4,\s*ta,\s*ma} 6 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m2,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m8,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 17 } } */ >> diff --git a/gcc/testsuite/gcc.target/riscv/pr108185-3.c >> b/gcc/testsuite/gcc.target/riscv/pr108185-3.c >> new file mode 100644 >> index 00000000000..3af0513e006 >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/riscv/pr108185-3.c >> @@ -0,0 +1,68 @@ >> +/* { dg-do compile } */ >> +/* { dg-options "-march=3Drv64gcv -mabi=3Dlp64 -O3" } */ >> + >> +#include "riscv_vector.h" >> + >> +void >> +test_vbool4_then_vbool1(int8_t * restrict in, int8_t * restrict out) { >> + vbool4_t v1 =3D *(vbool4_t*)in; >> + vbool1_t v2 =3D *(vbool1_t*)in; >> + >> + *(vbool4_t*)(out + 100) =3D v1; >> + *(vbool1_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool4_then_vbool2(int8_t * restrict in, int8_t * restrict out) { >> + vbool4_t v1 =3D *(vbool4_t*)in; >> + vbool2_t v2 =3D *(vbool2_t*)in; >> + >> + *(vbool4_t*)(out + 100) =3D v1; >> + *(vbool2_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool4_then_vbool8(int8_t * restrict in, int8_t * restrict out) { >> + vbool4_t v1 =3D *(vbool4_t*)in; >> + vbool8_t v2 =3D *(vbool8_t*)in; >> + >> + *(vbool4_t*)(out + 100) =3D v1; >> + *(vbool8_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool4_then_vbool16(int8_t * restrict in, int8_t * restrict out) { >> + vbool4_t v1 =3D *(vbool4_t*)in; >> + vbool16_t v2 =3D *(vbool16_t*)in; >> + >> + *(vbool4_t*)(out + 100) =3D v1; >> + *(vbool16_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool4_then_vbool32(int8_t * restrict in, int8_t * restrict out) { >> + vbool4_t v1 =3D *(vbool4_t*)in; >> + vbool32_t v2 =3D *(vbool32_t*)in; >> + >> + *(vbool4_t*)(out + 100) =3D v1; >> + *(vbool32_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool4_then_vbool64(int8_t * restrict in, int8_t * restrict out) { >> + vbool4_t v1 =3D *(vbool4_t*)in; >> + vbool64_t v2 =3D *(vbool64_t*)in; >> + >> + *(vbool4_t*)(out + 100) =3D v1; >> + *(vbool64_t*)(out + 200) =3D v2; >> +} >> + >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m2,\s*ta,\s*ma} 6 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m8,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m4,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 16 } } */ >> diff --git a/gcc/testsuite/gcc.target/riscv/pr108185-4.c >> b/gcc/testsuite/gcc.target/riscv/pr108185-4.c >> new file mode 100644 >> index 00000000000..ea3c360d756 >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/riscv/pr108185-4.c >> @@ -0,0 +1,68 @@ >> +/* { dg-do compile } */ >> +/* { dg-options "-march=3Drv64gcv -mabi=3Dlp64 -O3" } */ >> + >> +#include "riscv_vector.h" >> + >> +void >> +test_vbool8_then_vbool1(int8_t * restrict in, int8_t * restrict out) { >> + vbool8_t v1 =3D *(vbool8_t*)in; >> + vbool1_t v2 =3D *(vbool1_t*)in; >> + >> + *(vbool8_t*)(out + 100) =3D v1; >> + *(vbool1_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool8_then_vbool2(int8_t * restrict in, int8_t * restrict out) { >> + vbool8_t v1 =3D *(vbool8_t*)in; >> + vbool2_t v2 =3D *(vbool2_t*)in; >> + >> + *(vbool8_t*)(out + 100) =3D v1; >> + *(vbool2_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool8_then_vbool4(int8_t * restrict in, int8_t * restrict out) { >> + vbool8_t v1 =3D *(vbool8_t*)in; >> + vbool4_t v2 =3D *(vbool4_t*)in; >> + >> + *(vbool8_t*)(out + 100) =3D v1; >> + *(vbool4_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool8_then_vbool16(int8_t * restrict in, int8_t * restrict out) { >> + vbool8_t v1 =3D *(vbool8_t*)in; >> + vbool16_t v2 =3D *(vbool16_t*)in; >> + >> + *(vbool8_t*)(out + 100) =3D v1; >> + *(vbool16_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool8_then_vbool32(int8_t * restrict in, int8_t * restrict out) { >> + vbool8_t v1 =3D *(vbool8_t*)in; >> + vbool32_t v2 =3D *(vbool32_t*)in; >> + >> + *(vbool8_t*)(out + 100) =3D v1; >> + *(vbool32_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool8_then_vbool64(int8_t * restrict in, int8_t * restrict out) { >> + vbool8_t v1 =3D *(vbool8_t*)in; >> + vbool64_t v2 =3D *(vbool64_t*)in; >> + >> + *(vbool8_t*)(out + 100) =3D v1; >> + *(vbool64_t*)(out + 200) =3D v2; >> +} >> + >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma} 6 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m2,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m8,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m4,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 15 } } */ >> diff --git a/gcc/testsuite/gcc.target/riscv/pr108185-5.c >> b/gcc/testsuite/gcc.target/riscv/pr108185-5.c >> new file mode 100644 >> index 00000000000..9fc659d2402 >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/riscv/pr108185-5.c >> @@ -0,0 +1,68 @@ >> +/* { dg-do compile } */ >> +/* { dg-options "-march=3Drv64gcv -mabi=3Dlp64 -O3" } */ >> + >> +#include "riscv_vector.h" >> + >> +void >> +test_vbool16_then_vbool1(int8_t * restrict in, int8_t * restrict out) { >> + vbool16_t v1 =3D *(vbool16_t*)in; >> + vbool1_t v2 =3D *(vbool1_t*)in; >> + >> + *(vbool16_t*)(out + 100) =3D v1; >> + *(vbool1_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool16_then_vbool2(int8_t * restrict in, int8_t * restrict out) { >> + vbool16_t v1 =3D *(vbool16_t*)in; >> + vbool2_t v2 =3D *(vbool2_t*)in; >> + >> + *(vbool16_t*)(out + 100) =3D v1; >> + *(vbool2_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool16_then_vbool4(int8_t * restrict in, int8_t * restrict out) { >> + vbool16_t v1 =3D *(vbool16_t*)in; >> + vbool4_t v2 =3D *(vbool4_t*)in; >> + >> + *(vbool16_t*)(out + 100) =3D v1; >> + *(vbool4_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool16_then_vbool8(int8_t * restrict in, int8_t * restrict out) { >> + vbool16_t v1 =3D *(vbool16_t*)in; >> + vbool8_t v2 =3D *(vbool8_t*)in; >> + >> + *(vbool16_t*)(out + 100) =3D v1; >> + *(vbool8_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool16_then_vbool32(int8_t * restrict in, int8_t * restrict out) = { >> + vbool16_t v1 =3D *(vbool16_t*)in; >> + vbool32_t v2 =3D *(vbool32_t*)in; >> + >> + *(vbool16_t*)(out + 100) =3D v1; >> + *(vbool32_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool16_then_vbool64(int8_t * restrict in, int8_t * restrict out) = { >> + vbool16_t v1 =3D *(vbool16_t*)in; >> + vbool64_t v2 =3D *(vbool64_t*)in; >> + >> + *(vbool16_t*)(out + 100) =3D v1; >> + *(vbool64_t*)(out + 200) =3D v2; >> +} >> + >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 6 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m2,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m8,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m4,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 14 } } */ >> diff --git a/gcc/testsuite/gcc.target/riscv/pr108185-6.c >> b/gcc/testsuite/gcc.target/riscv/pr108185-6.c >> new file mode 100644 >> index 00000000000..98275e5267d >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/riscv/pr108185-6.c >> @@ -0,0 +1,68 @@ >> +/* { dg-do compile } */ >> +/* { dg-options "-march=3Drv64gcv -mabi=3Dlp64 -O3" } */ >> + >> +#include "riscv_vector.h" >> + >> +void >> +test_vbool32_then_vbool1(int8_t * restrict in, int8_t * restrict out) { >> + vbool32_t v1 =3D *(vbool32_t*)in; >> + vbool1_t v2 =3D *(vbool1_t*)in; >> + >> + *(vbool32_t*)(out + 100) =3D v1; >> + *(vbool1_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool32_then_vbool2(int8_t * restrict in, int8_t * restrict out) { >> + vbool32_t v1 =3D *(vbool32_t*)in; >> + vbool2_t v2 =3D *(vbool2_t*)in; >> + >> + *(vbool32_t*)(out + 100) =3D v1; >> + *(vbool2_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool32_then_vbool4(int8_t * restrict in, int8_t * restrict out) { >> + vbool32_t v1 =3D *(vbool32_t*)in; >> + vbool4_t v2 =3D *(vbool4_t*)in; >> + >> + *(vbool32_t*)(out + 100) =3D v1; >> + *(vbool4_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool32_then_vbool8(int8_t * restrict in, int8_t * restrict out) { >> + vbool32_t v1 =3D *(vbool32_t*)in; >> + vbool8_t v2 =3D *(vbool8_t*)in; >> + >> + *(vbool32_t*)(out + 100) =3D v1; >> + *(vbool8_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool32_then_vbool16(int8_t * restrict in, int8_t * restrict out) = { >> + vbool32_t v1 =3D *(vbool32_t*)in; >> + vbool16_t v2 =3D *(vbool16_t*)in; >> + >> + *(vbool32_t*)(out + 100) =3D v1; >> + *(vbool16_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool32_then_vbool64(int8_t * restrict in, int8_t * restrict out) = { >> + vbool32_t v1 =3D *(vbool32_t*)in; >> + vbool64_t v2 =3D *(vbool64_t*)in; >> + >> + *(vbool32_t*)(out + 100) =3D v1; >> + *(vbool64_t*)(out + 200) =3D v2; >> +} >> + >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 6 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m8,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m4,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m2,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 13 } } */ >> diff --git a/gcc/testsuite/gcc.target/riscv/pr108185-7.c >> b/gcc/testsuite/gcc.target/riscv/pr108185-7.c >> new file mode 100644 >> index 00000000000..8f6f0b11f09 >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/riscv/pr108185-7.c >> @@ -0,0 +1,68 @@ >> +/* { dg-do compile } */ >> +/* { dg-options "-march=3Drv64gcv -mabi=3Dlp64 -O3" } */ >> + >> +#include "riscv_vector.h" >> + >> +void >> +test_vbool64_then_vbool1(int8_t * restrict in, int8_t * restrict out) { >> + vbool64_t v1 =3D *(vbool64_t*)in; >> + vbool1_t v2 =3D *(vbool1_t*)in; >> + >> + *(vbool64_t*)(out + 100) =3D v1; >> + *(vbool1_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool64_then_vbool2(int8_t * restrict in, int8_t * restrict out) { >> + vbool64_t v1 =3D *(vbool64_t*)in; >> + vbool2_t v2 =3D *(vbool2_t*)in; >> + >> + *(vbool64_t*)(out + 100) =3D v1; >> + *(vbool2_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool64_then_vbool4(int8_t * restrict in, int8_t * restrict out) { >> + vbool64_t v1 =3D *(vbool64_t*)in; >> + vbool4_t v2 =3D *(vbool4_t*)in; >> + >> + *(vbool64_t*)(out + 100) =3D v1; >> + *(vbool4_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool64_then_vbool8(int8_t * restrict in, int8_t * restrict out) { >> + vbool64_t v1 =3D *(vbool64_t*)in; >> + vbool8_t v2 =3D *(vbool8_t*)in; >> + >> + *(vbool64_t*)(out + 100) =3D v1; >> + *(vbool8_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool64_then_vbool16(int8_t * restrict in, int8_t * restrict out) = { >> + vbool64_t v1 =3D *(vbool64_t*)in; >> + vbool16_t v2 =3D *(vbool16_t*)in; >> + >> + *(vbool64_t*)(out + 100) =3D v1; >> + *(vbool16_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool64_then_vbool32(int8_t * restrict in, int8_t * restrict out) = { >> + vbool64_t v1 =3D *(vbool64_t*)in; >> + vbool32_t v2 =3D *(vbool32_t*)in; >> + >> + *(vbool64_t*)(out + 100) =3D v1; >> + *(vbool32_t*)(out + 200) =3D v2; >> +} >> + >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 6 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m8,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m4,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m2,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */ >> diff --git a/gcc/testsuite/gcc.target/riscv/pr108185-8.c >> b/gcc/testsuite/gcc.target/riscv/pr108185-8.c >> new file mode 100644 >> index 00000000000..d96959dd064 >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/riscv/pr108185-8.c >> @@ -0,0 +1,77 @@ >> +/* { dg-do compile } */ >> +/* { dg-options "-march=3Drv64gcv -mabi=3Dlp64 -O3" } */ >> + >> +#include "riscv_vector.h" >> + >> +void >> +test_vbool1_then_vbool1(int8_t * restrict in, int8_t * restrict out) { >> + vbool1_t v1 =3D *(vbool1_t*)in; >> + vbool1_t v2 =3D *(vbool1_t*)in; >> + >> + *(vbool1_t*)(out + 100) =3D v1; >> + *(vbool1_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool2_then_vbool2(int8_t * restrict in, int8_t * restrict out) { >> + vbool2_t v1 =3D *(vbool2_t*)in; >> + vbool2_t v2 =3D *(vbool2_t*)in; >> + >> + *(vbool2_t*)(out + 100) =3D v1; >> + *(vbool2_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool4_then_vbool4(int8_t * restrict in, int8_t * restrict out) { >> + vbool4_t v1 =3D *(vbool4_t*)in; >> + vbool4_t v2 =3D *(vbool4_t*)in; >> + >> + *(vbool4_t*)(out + 100) =3D v1; >> + *(vbool4_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool8_then_vbool8(int8_t * restrict in, int8_t * restrict out) { >> + vbool8_t v1 =3D *(vbool8_t*)in; >> + vbool8_t v2 =3D *(vbool8_t*)in; >> + >> + *(vbool8_t*)(out + 100) =3D v1; >> + *(vbool8_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool16_then_vbool16(int8_t * restrict in, int8_t * restrict out) = { >> + vbool16_t v1 =3D *(vbool16_t*)in; >> + vbool16_t v2 =3D *(vbool16_t*)in; >> + >> + *(vbool16_t*)(out + 100) =3D v1; >> + *(vbool16_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool32_then_vbool32(int8_t * restrict in, int8_t * restrict out) = { >> + vbool32_t v1 =3D *(vbool32_t*)in; >> + vbool32_t v2 =3D *(vbool32_t*)in; >> + >> + *(vbool32_t*)(out + 100) =3D v1; >> + *(vbool32_t*)(out + 200) =3D v2; >> +} >> + >> +void >> +test_vbool64_then_vbool64(int8_t * restrict in, int8_t * restrict out) = { >> + vbool64_t v1 =3D *(vbool64_t*)in; >> + vbool64_t v2 =3D *(vbool64_t*)in; >> + >> + *(vbool64_t*)(out + 100) =3D v1; >> + *(vbool64_t*)(out + 200) =3D v2; >> +} >> + >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m8,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m4,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m2,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 7 } } */ >> +/* { dg-final { scan-assembler-times=20 >> +{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 14 } } */