RE: [PATCH V2] RISC-V: Enable len_mask{load, store} and remove len_{load, store}

["Li, Pan2" <pan2.li@intel.com>]

Committed, thanks Jeff.

Pan

-----Original Message-----
From: Gcc-patches <gcc-patches-bounces+pan2.li=intel.com@gcc.gnu.org> On Behalf Of Jeff Law via Gcc-patches
Sent: Sunday, June 25, 2023 8:53 PM
To: Juzhe-Zhong <juzhe.zhong@rivai.ai>; gcc-patches@gcc.gnu.org
Cc: kito.cheng@gmail.com; kito.cheng@sifive.com; palmer@dabbelt.com; palmer@rivosinc.com; rdapp.gcc@gmail.com
Subject: Re: [PATCH V2] RISC-V: Enable len_mask{load, store} and remove len_{load, store}



On 6/25/23 02:39, Juzhe-Zhong wrote:
> This patch enable len_mask_{load,store} to support flow-control in RVV auto-vectorization.
> 
> Consider this following case:
> void
> f (int32_t *__restrict a,
>     int32_t *__restrict b,
>     int32_t *__restrict cond,
>     int n)
> {
>    for (int i = 0; i < n; i++)
>      if (cond[i])
>        a[i] = b[i];
> }
> 
> Before this patch:
> <source>:9:21: missed: couldn't vectorize loop
> <source>:9:21: missed: not vectorized: control flow in loop.
> 
> After this patch:
> f:
>          ble     a3,zero,.L5
> .L3:
>          vsetvli a5,a3,e32,m1,ta,ma
>          vle32.v v0,0(a2)
>          vsetvli a6,zero,e32,m1,ta,ma
>          slli    a4,a5,2
>          vmsne.vi        v0,v0,0
>          sub     a3,a3,a5
>          vsetvli zero,a5,e32,m1,ta,ma
>          vle32.v v1,0(a1),v0.t
>          vse32.v v1,0(a0),v0.t
>          add     a2,a2,a4
>          add     a1,a1,a4
>          add     a0,a0,a4
>          bne     a3,zero,.L3
> .L5:
>          ret
> 
> 
> gcc/ChangeLog:
> 
>          * config/riscv/autovec.md (len_load_<mode>): Remove.
>          (len_maskload<mode><vm>): Remove.
>          (len_store_<mode>): New pattern.
>          (len_maskstore<mode><vm>): New pattern.
>          * config/riscv/predicates.md (autovec_length_operand): New predicate.
>          * config/riscv/riscv-protos.h (enum insn_type): New enum.
>          (expand_load_store): New function.
>          * config/riscv/riscv-v.cc (emit_vlmax_masked_insn): Ditto.
>          (emit_nonvlmax_masked_insn): Ditto.
>          (expand_load_store): Ditto.
>          * config/riscv/riscv-vector-builtins.cc (function_expander::use_contiguous_store_insn): Add avl_type operand into pred_store.
>          * config/riscv/vector.md: Ditto.
OK
jeff