From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.93]) by sourceware.org (Postfix) with ESMTPS id E65F43858D37 for ; Mon, 23 Oct 2023 02:44:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E65F43858D37 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org E65F43858D37 Authentication-Results: server2.sourceware.org; arc=pass smtp.remote-ip=192.55.52.93 ARC-Seal: i=2; a=rsa-sha256; d=sourceware.org; s=key; t=1698029053; cv=pass; b=Lup3G/WTWrD6a8Lg3qDwQu6n9kemN7PGbXN8f9d1/6qsma2hIhoTxrhvLulAFfzgJJCi5yS5qPSSFuhGK6QocQDQZjmkPAMYLePZ0mtdS6Vo7zOUFRAf5ydb4yKdzXgBWcvYYagjctI8IGUqh5BeZvFPIwAqgyFk/Suf4IqsTA4= ARC-Message-Signature: i=2; a=rsa-sha256; d=sourceware.org; s=key; t=1698029053; c=relaxed/simple; bh=ZU6GMH1jyoCPatV+pWRtu3aB+IPF3z4qlokLBzLLhqA=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=VSss/AF5+LB0M/dfQknaJ6QAt/PWHRM/nYwx6/DKoIAlQYd/I3adKr9VPaN7OrKWO/I8P5yapuAOnA4NMH+lkV3wLnrpI9kGT2KJOBBTLTTnMgBllB8W9nbQbP/HIeHNd/nQIMqXXZgzupadQkoodyvdMgEES81sJIhdVzheKKs= ARC-Authentication-Results: i=2; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698029046; x=1729565046; h=from:to:cc:subject:date:message-id:references: in-reply-to:mime-version; bh=ZU6GMH1jyoCPatV+pWRtu3aB+IPF3z4qlokLBzLLhqA=; b=D1PAEe5jalLjsiuqtfDQELnGL75emzc4wP9eOMiH4diNFxtHDoJvGr0y gn4J9tVLSXr4vMq4zvR5uruoKtY4XzoUJhdiIkmeisrw/JUlgGmcw4DGg 5TfKSUzpMO28pOfUVJbrgDaPi4LqYQ6uFVdu++U8iv2WWyZ4cjiFSrh3L 6iNuTQ+TjpUBDcekHFQOwizmHjYnOE8HhUVupZJRCMtuTjmF0yoOg/md/ /6C4EHNL7kYMvy1FSZF28LnuwKjdotdxgu5AKlAK6Sxxx9UzKtXPkA6uS 3p/EzUrwnVOTE/d/1SrG27vLbcH07YW9/IGg7o0p6WZkwFpbA8qRr2SCR Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="383954676" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208,217";a="383954676" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2023 19:44:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="881610420" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208,217";a="881610420" Received: from orsmsx601.amr.corp.intel.com ([10.22.229.14]) by orsmga004.jf.intel.com with ESMTP/TLS/AES256-GCM-SHA384; 22 Oct 2023 19:44:04 -0700 Received: from orsmsx611.amr.corp.intel.com (10.22.229.24) by ORSMSX601.amr.corp.intel.com (10.22.229.14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32; Sun, 22 Oct 2023 19:44:03 -0700 Received: from orsmsx603.amr.corp.intel.com (10.22.229.16) by ORSMSX611.amr.corp.intel.com (10.22.229.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32; Sun, 22 Oct 2023 19:44:03 -0700 Received: from ORSEDG602.ED.cps.intel.com (10.7.248.7) by orsmsx603.amr.corp.intel.com (10.22.229.16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32 via Frontend Transport; Sun, 22 Oct 2023 19:44:02 -0700 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (104.47.55.168) by edgegateway.intel.com (134.134.137.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.32; Sun, 22 Oct 2023 19:44:02 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=HHOyi6I+02qzhabp/qSJWyIFrhLvnq/S7Lypt5okDCOjocHTqj1aHAELBrccqAGt+Gs2O1S1YhvG9Dazw8sqV4WHEJDXcAbmpAuG+jWje7R2L7NvmQYDfPBFvh9bb7kRezvqrh1XuwKx6BEiJxfZhO6EXBAljhdRZ6IgOkbg74Qucf6z13XevBAPW+nLSZtTXv0MCFZVR38ti/QUkQzjTbHiR6yLR5NRTRZiIg2ZPql3iIVtm7vRx2eSwwhVnSC9/NKthoE60CLXOsBu885cBbhVre68XqBTvAfdVqVWLZI593mSXbek+4jaAmHHmEx7GzG8n7eV7ip+jPNyQ8Aagg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=a39XCCoiEEOkfv/uqWf7Txdjg6tvXbLDWyESLoKb5Zs=; b=K2g1nWAC7yBgJQgob8UwehVEGo+Z+e9nqdqo2kx0YXlN6Z6vEtQ6QDendN3BXqT2UhnLqcNpEoF2HiJqPhAj/i73K5nHRqGdmeiAGDjXu594+5/wioat7mJ9dmTetnIzfymR2Nsko8ss+gSeW/EZeG4Bphd+ExqLpvjwwAn2ixVGn58mPfi55nk7OJ2ngsyrT+ObpmGUT2bBC/agMdgUuT0iY0bGJyS/KiC3pJkcRE6+kTc+zWDGNMhjcFsyjhHL320sFkoUKXMBPyDWFhZEPyfMvZ8AcP4CkvMQFntpZ2YP4NQ413D45wA8ncvwKJHkhHvMbzXgFfnHhiS8+SPmYA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Received: from MW5PR11MB5908.namprd11.prod.outlook.com (2603:10b6:303:194::10) by CYYPR11MB8431.namprd11.prod.outlook.com (2603:10b6:930:c7::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6907.26; Mon, 23 Oct 2023 02:43:58 +0000 Received: from MW5PR11MB5908.namprd11.prod.outlook.com ([fe80::4317:53a0:2638:358c]) by MW5PR11MB5908.namprd11.prod.outlook.com ([fe80::4317:53a0:2638:358c%5]) with mapi id 15.20.6907.032; Mon, 23 Oct 2023 02:43:57 +0000 From: "Li, Pan2" To: "juzhe.zhong@rivai.ai" , gcc-patches CC: "Wang, Yanzhang" , kito.cheng Subject: RE: [PATCH v1] RISC-V: Remove unnecessary asm check for rounding autovec Thread-Topic: [PATCH v1] RISC-V: Remove unnecessary asm check for rounding autovec Thread-Index: AQHaBVoj9ao1IOiQR0uSOXSxRyOz6rBWqlkbgAAAV/A= Date: Mon, 23 Oct 2023 02:43:57 +0000 Message-ID: References: <20231023023904.1881908-1-pan2.li@intel.com> <25F1F47949575B4E+202310231040414113620@rivai.ai> In-Reply-To: <25F1F47949575B4E+202310231040414113620@rivai.ai> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: MW5PR11MB5908:EE_|CYYPR11MB8431:EE_ x-ms-office365-filtering-correlation-id: 54ce4eec-cc31-405a-27d2-08dbd371e793 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: xGRz5SD0sizkLjfP5zvEd6BjVoSluI+k8KaaujU5sD5pgLdKgNDyTKRgcygiiqp0Tgm4xP6HdXwxP+onVVWFDrCwpMVjKK5jMAlJQ+iJstYoCGdnjrdqtGQWuKWmw5ChQX2+xZGwTlWgyq2Y2qswxmL6xwInxgfqvhPIcoa8B/lWfSW8UPdfOsrRXifddLfNjlc1NVVRhzU2A2Ao6rndLt3jNe53TqDsiTDdVG3MI/WKXZeAxKaF6JlYT/gdmltjLyxvgkO3ZBPCzdiN5JFwzTv9xYSw7y56bMLv1R+pwF996U2S7OkOULX274CagrCsoIqreov1NncQJHp/xhKxUlcFoKp1rLChMlulc4i17cg/6+bQovEgghpF3nN2I+FcI6LPxucINCdzzlLu902SKLA2S41rQkOw/eK2l+m6PoKJys7Ee5s+LWdO8VO9lQ3Ljxe4Ag38TZsy4XQP/jMGAlLblGqjzi2zIPV6EVwqYGM5CZVJQIlmCr7qRJHL3o2VaptpEMtBqKwWRqrxH+OSLtKnda5lTJ78guMkOQRcDwC0Sw5Lpst1kpTBIcMFH9itwFXGJtiJXuj56dSYTxnrwEXPfsGNOok3rUxGotZtXPWQYeHlCnW/VagmIpMYVnRVmSufBibcHb505xS6weemXA== x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MW5PR11MB5908.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(39860400002)(346002)(396003)(376002)(366004)(136003)(230922051799003)(64100799003)(186009)(1800799009)(451199024)(38070700009)(84970400001)(7696005)(4326008)(55016003)(86362001)(38100700002)(30864003)(82960400001)(41300700001)(4001150100001)(5660300002)(2906002)(6506007)(122000001)(52536014)(9686003)(53546011)(26005)(83380400001)(8936002)(33656002)(71200400001)(8676002)(66946007)(478600001)(76116006)(110136005)(66446008)(66476007)(66556008)(316002)(54906003)(64756008)(579004)(559001);DIR:OUT;SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?C0XTbPvS4sOcecuqDY3thJdykwBS/fBgy5bOaXMbPWPvCiYQe2DyNIe981oO?= =?us-ascii?Q?2c/6cmbHcgXNzwcBgdTNmKWhx7Ym7T2t/94cNiPV6QAP0CL6blGWpKoPcNQk?= =?us-ascii?Q?pBqe3BeE/kwnAds1Tyw5qNWM+DE5GLYRfGIHRarnROWe1uq268R20IAYmB1M?= =?us-ascii?Q?IZYz8LAlHE5YhUPHMhs0ZM3q51vWVizqLtfC0ipFBaSzxbBdDBRQmJAqePQO?= =?us-ascii?Q?9PWAZBQ/pLx5vA+Q+j92f3/cn+hHhPMp0W9o5wUsXuSZWBiuHST4INLVR/LX?= =?us-ascii?Q?h7aj4u+fAifgNZRHUvEiSaHOBme+oJ7zUm+iKVGa2E7m4u3RHTzu4PF/B7fR?= =?us-ascii?Q?uvZCFR50s15hBQG8VhpW/vZf041vAt2A0d2YQA0fxkwITzo4TzXFJ2VJw1S/?= =?us-ascii?Q?j30Hl9eSxwPqhDjYEeZ/VAWybcKxQ/HAfqRbPVLKir3d8EGIjTppTKJM909m?= =?us-ascii?Q?WLiaFTlOBRj0F1XSC5k/+f685vYD+06pYLHx0nYS+Wsim2AKhoXJmfsqph/6?= =?us-ascii?Q?B8BVk04xpHVjgS4mtY7HiHcGiyInCatthDyxZ1TbTEnvkfPm50DOYQ9SPYa7?= =?us-ascii?Q?8jZ6WMZr++JGCOLvyg/XP/7V9gJ9BKvCrbNJqXhVicbLg3DvjCIReCDqeEJm?= =?us-ascii?Q?WULPzXnOqyRqBznYHHkvIxD4PnwpbQa/HUmHu7iXis7UqJMUGCxVY6VrErC+?= =?us-ascii?Q?GcB7bwfWtugeTDAIrpjSBsryagE3gsVBjwcb690MBNn/EOu69oEGKTfG+QYD?= =?us-ascii?Q?L8lRzs0+PW+9gtnowNqlNC/uzNIAy2+EzacEeEXXeMgJxWnfqcgweGqZhWGd?= =?us-ascii?Q?1JQTkV+qR9QetSVJl2v+x8du8r1U0//hSt22ZI2XCO50/3pMAYHEzsV/68R7?= =?us-ascii?Q?dUVzt4txxLDSCkE6KdXOCFBFrFkbPmF1FMfL2erIYQwoFH5LZ4egr/QfnJ34?= =?us-ascii?Q?9yRTV3bVDcB68GGEetwmOlqUvFFBp3rGZ1KGpZUFX+kBZpdPz0Tva2cbt71c?= =?us-ascii?Q?3mEKfnVHENRj9v+TuigcPEGNXhN63eItJzYxjKAiqG/KrOP1u3EyvjYQYe2n?= =?us-ascii?Q?szROqYMNwR9wTqRG+Pgab+prfLHm2OjgUGiMx29sVwU1ap+AeXhLN0SaRPch?= =?us-ascii?Q?cDaPd00yuOEnS7pS2OLjKy+5AJKy52x+wCf4rWXlPEhR0VpAk9dNMqBEGgFq?= =?us-ascii?Q?ZrV37ZkCAT0HT59kyMTE4q2pEnbQmAp1Gxi+mIXn9/FhIh/SeErcFxuUdJlv?= =?us-ascii?Q?iPslMSJrCvgf2UPwTKMiPmlu9Ykh3V0Jo9QjuQ0Clr9IQdqB/UVTgvGpGgtZ?= =?us-ascii?Q?SwdV6mtWqdsHA06FBANp+hBkxqxpJokkKeHBHqO1FNP5/rsW4aT2RnGyH5WD?= =?us-ascii?Q?PSc+A24b3kou8+weTYy9xke9vazW9kaAj14e+iBKEVg8QWANuTvfV7nXLWfB?= =?us-ascii?Q?mx+Ew2CE0mnBUQakXm9NunVTFwfklws8r/liVGwIyMjeNS2ppqKYTqpDWYE9?= =?us-ascii?Q?EwroFz+aBulblcYROfMSvQxlMYhG38XlH43wbAv1U8ne4lXDuBdVKvOaY5go?= =?us-ascii?Q?zXOSqg3Dm1iYUm93kgM=3D?= Content-Type: multipart/alternative; boundary="_000_MW5PR11MB59087CD0579B26EC1C698325A9D8AMW5PR11MB5908namp_" MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MW5PR11MB5908.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 54ce4eec-cc31-405a-27d2-08dbd371e793 X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Oct 2023 02:43:57.2925 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: cdIjvoDJ47zh/FS6er4XdrHoTx7NeCUujrK7qeimXrwIZ9b1GY1uOcInZx61dEfYiGjCmeoKEcJtlTMKS4jHdg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR11MB8431 X-OriginatorOrg: intel.com X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,HTML_MESSAGE,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --_000_MW5PR11MB59087CD0579B26EC1C698325A9D8AMW5PR11MB5908namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Committed, thanks Juzhe. Pan From: juzhe.zhong@rivai.ai Sent: Monday, October 23, 2023 10:41 AM To: Li, Pan2 ; gcc-patches Cc: Li, Pan2 ; Wang, Yanzhang ;= kito.cheng Subject: Re: [PATCH v1] RISC-V: Remove unnecessary asm check for rounding a= utovec LGTM. Thanks. ________________________________ juzhe.zhong@rivai.ai From: pan2.li Date: 2023-10-23 10:39 To: gcc-patches CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng Subject: [PATCH v1] RISC-V: Remove unnecessary asm check for rounding autov= ec From: Pan Li > The vsetvl asm check is unnecessary for the rounding function autovec. These rounding test cases should focus on the rounding insn sequence. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/unop/bswap16-0.c: Remove the vsetvl check. * gcc.target/riscv/rvv/autovec/unop/math-ceil-0.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-ceil-1.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-ceil-2.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-ceil-3.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-floor-0.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-floor-1.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-floor-2.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-floor-3.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-iceil-0.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-ifloor-0.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-irint-0.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-iround-0.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-lceil-0.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-lceil-1.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-lfloor-0.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-lfloor-1.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-llceil-0.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-llfloor-0.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-llrint-0.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-llround-0.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-lrint-0.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-lrint-1.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-lround-0.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-lround-1.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-nearbyint-0.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-nearbyint-1.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-nearbyint-2.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-nearbyint-3.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-rint-0.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-rint-1.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-rint-2.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-rint-3.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-round-0.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-round-1.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-round-2.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-round-3.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-roundeven-0.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-roundeven-1.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-roundeven-2.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-roundeven-3.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-trunc-0.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-trunc-1.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-trunc-2.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-trunc-3.c: Ditto. Signed-off-by: Pan Li > --- gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/bswap16-0.c | 1 - gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ceil-0.c | 1 - gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ceil-1.c | 1 - gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ceil-2.c | 1 - gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ceil-3.c | 1 - gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-floor-0.c | 1 - gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-floor-1.c | 1 - gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-floor-2.c | 1 - gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-floor-3.c | 1 - gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-iceil-0.c | 1 - gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ifloor-0.c | 1 - gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-irint-0.c | 1 - gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-iround-0.c | 1 - gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lceil-0.c | 1 - gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lceil-1.c | 1 - gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lfloor-0.c | 1 - gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lfloor-1.c | 1 - gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llceil-0.c | 1 - gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llfloor-0.c | 1 - gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llrint-0.c | 1 - gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llround-0.c | 1 - gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lrint-0.c | 1 - gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lrint-1.c | 1 - gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lround-0.c | 1 - gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lround-1.c | 1 - .../gcc.target/riscv/rvv/autovec/unop/math-nearbyint-0.c | 1 - .../gcc.target/riscv/rvv/autovec/unop/math-nearbyint-1.c | 1 - .../gcc.target/riscv/rvv/autovec/unop/math-nearbyint-2.c | 1 - .../gcc.target/riscv/rvv/autovec/unop/math-nearbyint-3.c | 1 - gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-0.c | 1 - gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-1.c | 1 - gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-2.c | 1 - gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-3.c | 1 - gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-round-0.c | 1 - gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-round-1.c | 1 - gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-round-2.c | 1 - gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-round-3.c | 1 - .../gcc.target/riscv/rvv/autovec/unop/math-roundeven-0.c | 1 - .../gcc.target/riscv/rvv/autovec/unop/math-roundeven-1.c | 1 - .../gcc.target/riscv/rvv/autovec/unop/math-roundeven-2.c | 1 - .../gcc.target/riscv/rvv/autovec/unop/math-roundeven-3.c | 1 - gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-0.c | 1 - gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-1.c | 1 - gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-2.c | 1 - gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-3.c | 1 - 45 files changed, 45 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/bswap16-0.c b/= gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/bswap16-0.c index 10d235a8edf..605b3565b6b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/bswap16-0.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/bswap16-0.c @@ -8,7 +8,6 @@ /* ** test_uint16_t___builtin_bswap16: ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma ** vsrl\.vi\s+v[0-9]+,\s*v[0-9],\s*8+ ** vsll\.vi\s+v[0-9]+,\s*v[0-9],\s*8+ ** vor\.vv\s+v[0-9]+,\s*v[0-9],\s*v[0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ceil-0.c = b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ceil-0.c index 1c53d9b67d3..5660d980030 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ceil-0.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ceil-0.c @@ -10,7 +10,6 @@ ** ... ** fsrmi\s+3 ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*mu ** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ ** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ ** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ceil-1.c = b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ceil-1.c index a6d0ac3fc83..62a089b5927 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ceil-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ceil-1.c @@ -10,7 +10,6 @@ ** ... ** fsrmi\s+3 ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*mu ** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ ** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ ** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ceil-2.c = b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ceil-2.c index d196fc678c4..1f57e08d151 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ceil-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ceil-2.c @@ -10,7 +10,6 @@ ** ... ** fsrmi\s+3 ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*mu ** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ ** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ ** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ceil-3.c = b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ceil-3.c index cd3df49de6d..e74d2303483 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ceil-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ceil-3.c @@ -10,7 +10,6 @@ ** ... ** fsrmi\s+3 ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*mu ** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ ** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ ** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-floor-0.c= b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-floor-0.c index 33b169395bf..06af0f15e02 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-floor-0.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-floor-0.c @@ -10,7 +10,6 @@ ** ... ** fsrmi\s+2 ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*mu ** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ ** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ ** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-floor-1.c= b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-floor-1.c index 5c462c424df..b4913eae2ad 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-floor-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-floor-1.c @@ -10,7 +10,6 @@ ** ... ** fsrmi\s+2 ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*mu ** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ ** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ ** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-floor-2.c= b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-floor-2.c index 6f07add1004..86a83d87e7b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-floor-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-floor-2.c @@ -10,7 +10,6 @@ ** ... ** fsrmi\s+2 ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*mu ** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ ** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ ** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-floor-3.c= b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-floor-3.c index a091ffdab50..a9a5d156ea7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-floor-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-floor-3.c @@ -10,7 +10,6 @@ ** ... ** fsrmi\s+2 ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*mu ** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ ** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ ** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-iceil-0.c= b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-iceil-0.c index 2d4a1d163d1..b8347868398 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-iceil-0.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-iceil-0.c @@ -10,7 +10,6 @@ ** ... ** fsrmi\s+3 ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma ** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+ ** ... ** fsrm\s+[atx][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ifloor-0.= c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ifloor-0.c index b9ec415d690..40c6519aa0d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ifloor-0.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-ifloor-0.c @@ -10,7 +10,6 @@ ** ... ** fsrmi\s+2 ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma ** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+ ** ... ** fsrm\s+[atx][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-irint-0.c= b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-irint-0.c index 3ca2f651763..3d0c887e63f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-irint-0.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-irint-0.c @@ -7,7 +7,6 @@ /* ** test_float_int___builtin_irintf: ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma ** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-iround-0.= c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-iround-0.c index f32515d1403..14828e22fd6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-iround-0.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-iround-0.c @@ -10,7 +10,6 @@ ** ... ** fsrmi\s+4 ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma ** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+ ** ... ** fsrm\s+[atx][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lceil-0.c= b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lceil-0.c index 3b13a52d555..5084672e290 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lceil-0.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lceil-0.c @@ -10,7 +10,6 @@ ** ... ** fsrmi\s+3 ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma ** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+ ** ... ** fsrm\s+[atx][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lceil-1.c= b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lceil-1.c index 5ff5d1d2ab1..1a51482af14 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lceil-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lceil-1.c @@ -10,7 +10,6 @@ ** ... ** fsrmi\s+3 ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma ** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+ ** ... ** fsrm\s+[atx][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lfloor-0.= c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lfloor-0.c index ac2d1722300..10bfadc7848 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lfloor-0.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lfloor-0.c @@ -10,7 +10,6 @@ ** ... ** fsrmi\s+2 ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma ** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+ ** ... ** fsrm\s+[atx][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lfloor-1.= c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lfloor-1.c index 164e97c17d6..b2eede8d130 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lfloor-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lfloor-1.c @@ -10,7 +10,6 @@ ** ... ** fsrmi\s+2 ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma ** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+ ** ... ** fsrm\s+[atx][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llceil-0.= c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llceil-0.c index 3480c3ea91d..ba85728d3e5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llceil-0.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llceil-0.c @@ -11,7 +11,6 @@ ** ... ** fsrmi\s+3 ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma ** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+ ** ... ** fsrm\s+[atx][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llfloor-0= .c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llfloor-0.c index 4b10f966015..2bd82ac4631 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llfloor-0.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llfloor-0.c @@ -11,7 +11,6 @@ ** ... ** fsrmi\s+2 ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma ** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+ ** ... ** fsrm\s+[atx][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llrint-0.= c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llrint-0.c index 4bf125f8cc8..b919109051d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llrint-0.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llrint-0.c @@ -8,7 +8,6 @@ /* ** test_double_int64_t___builtin_llrint: ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma ** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llround-0= .c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llround-0.c index 4f8b4553a91..2f3a7c60d22 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llround-0.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llround-0.c @@ -11,7 +11,6 @@ ** ... ** fsrmi\s+4 ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma ** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+ ** ... ** fsrm\s+[atx][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lrint-0.c= b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lrint-0.c index a60ef30efa4..dae0cfa76fd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lrint-0.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lrint-0.c @@ -7,7 +7,6 @@ /* ** test_double_long___builtin_lrint: ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma ** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lrint-1.c= b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lrint-1.c index 57e92ffb0e6..426a6439530 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lrint-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lrint-1.c @@ -7,7 +7,6 @@ /* ** test_float_long___builtin_lrintf: ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma ** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+ ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lround-0.= c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lround-0.c index 32b7348e7ad..242074e6794 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lround-0.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lround-0.c @@ -10,7 +10,6 @@ ** ... ** fsrmi\s+4 ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma ** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+ ** ... ** fsrm\s+[atx][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lround-1.= c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lround-1.c index a4d6fcfb0dc..3d95e224c0b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lround-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lround-1.c @@ -10,7 +10,6 @@ ** ... ** fsrmi\s+4 ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma ** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+ ** ... ** fsrm\s+[atx][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-nearbyint= -0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-nearbyint-0.c index f67b22ac02d..85d5e0acab2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-nearbyint-0.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-nearbyint-0.c @@ -7,7 +7,6 @@ /* ** test__Float16___builtin_nearbyintf16: ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*mu ** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ ** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ ** frflags\s+[axt][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-nearbyint= -1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-nearbyint-1.c index 93639863412..9697aed3bf1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-nearbyint-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-nearbyint-1.c @@ -7,7 +7,6 @@ /* ** test_float___builtin_nearbyintf: ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*mu ** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ ** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ ** frflags\s+[axt][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-nearbyint= -2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-nearbyint-2.c index d31de739d2d..00402ddee70 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-nearbyint-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-nearbyint-2.c @@ -7,7 +7,6 @@ /* ** test_double___builtin_nearbyint: ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*mu ** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ ** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ ** frflags\s+[axt][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-nearbyint= -3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-nearbyint-3.c index 4fd99505b40..6a8a276cc45 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-nearbyint-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-nearbyint-3.c @@ -7,7 +7,6 @@ /* ** test_float___builtin_nearbyintf: ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*mu ** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ ** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ ** frflags\s+[axt][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-0.c = b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-0.c index 0d44b9844dd..d57f9de82fc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-0.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-0.c @@ -7,7 +7,6 @@ /* ** test__Float16___builtin_rintf16: ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*mu ** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ ** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ ** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-1.c = b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-1.c index 2ce122af677..4a796739ff4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-1.c @@ -7,7 +7,6 @@ /* ** test_float___builtin_rintf: ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*mu ** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ ** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ ** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-2.c = b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-2.c index e3b911b45c4..a7d75501e1a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-2.c @@ -7,7 +7,6 @@ /* ** test_double___builtin_rint: ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*mu ** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ ** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ ** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-3.c = b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-3.c index 541c42c2ec7..33e62871238 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-3.c @@ -7,7 +7,6 @@ /* ** test_float___builtin_rintf: ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*mu ** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ ** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ ** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-round-0.c= b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-round-0.c index 06de57bf7e2..18770df99cc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-round-0.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-round-0.c @@ -10,7 +10,6 @@ ** ... ** fsrmi\s+4 ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*mu ** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ ** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ ** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-round-1.c= b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-round-1.c index ee51bcd820b..d50c293ca26 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-round-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-round-1.c @@ -10,7 +10,6 @@ ** ... ** fsrmi\s+4 ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*mu ** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ ** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ ** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-round-2.c= b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-round-2.c index d78f0583e41..28a928debd5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-round-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-round-2.c @@ -10,7 +10,6 @@ ** ... ** fsrmi\s+4 ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*mu ** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ ** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ ** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-round-3.c= b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-round-3.c index 98d14673e20..953ed60eac1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-round-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-round-3.c @@ -10,7 +10,6 @@ ** ... ** fsrmi\s+4 ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*mu ** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ ** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ ** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-roundeven= -0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-roundeven-0.c index ab65e372f0e..98d1171065c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-roundeven-0.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-roundeven-0.c @@ -10,7 +10,6 @@ ** ... ** fsrmi\s+0 ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*mu ** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ ** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ ** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-roundeven= -1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-roundeven-1.c index fac85ed0895..5c021770352 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-roundeven-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-roundeven-1.c @@ -10,7 +10,6 @@ ** ... ** fsrmi\s+0 ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*mu ** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ ** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ ** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-roundeven= -2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-roundeven-2.c index 074f1b4a1ae..7a14a7d4034 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-roundeven-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-roundeven-2.c @@ -10,7 +10,6 @@ ** ... ** fsrmi\s+0 ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*mu ** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ ** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ ** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-roundeven= -3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-roundeven-3.c index c95e8eca007..6092fdcd8dc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-roundeven-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-roundeven-3.c @@ -10,7 +10,6 @@ ** ... ** fsrmi\s+0 ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*mu ** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ ** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ ** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-0.c= b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-0.c index e3046341b99..ea135cd8965 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-0.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-0.c @@ -7,7 +7,6 @@ /* ** test__Float16___builtin_truncf16: ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*mu ** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ ** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ ** vfcvt\.rtz\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-1.c= b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-1.c index 8100419d22f..e4ef82dac19 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-1.c @@ -7,7 +7,6 @@ /* ** test_float___builtin_truncf: ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*mu ** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ ** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ ** vfcvt\.rtz\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-2.c= b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-2.c index 40551f559a7..7d17a11bbaf 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-2.c @@ -7,7 +7,6 @@ /* ** test_double___builtin_trunc: ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*mu ** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ ** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ ** vfcvt\.rtz\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-3.c= b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-3.c index bb113fd4f2a..66c19463e08 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-trunc-3.c @@ -7,7 +7,6 @@ /* ** test_float___builtin_truncf: ** ... -** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*mu ** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ ** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ ** vfcvt\.rtz\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t -- 2.34.1 --_000_MW5PR11MB59087CD0579B26EC1C698325A9D8AMW5PR11MB5908namp_--