From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by sourceware.org (Postfix) with ESMTPS id 049913858023 for ; Mon, 23 Oct 2023 08:02:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 049913858023 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 049913858023 Authentication-Results: server2.sourceware.org; arc=pass smtp.remote-ip=192.198.163.7 ARC-Seal: i=2; a=rsa-sha256; d=sourceware.org; s=key; t=1698048133; cv=pass; b=mBqz2rC3twtk7kkYMbyZ+vUqN/nOrkxNi6x1D4HObZ31fpMr5LiWHVvq7rjO7dFSbSsfKcTsGZNZxfbMuR1k5lc0KjjuYWFHbL2EkT0E846bC13KIDIiWr6dlD/OSOe80lNNJw2qXY71AB+zCXjJukGziWOGcP0FhvJBrbjQz0Y= ARC-Message-Signature: i=2; a=rsa-sha256; d=sourceware.org; s=key; t=1698048133; c=relaxed/simple; bh=vXWAMlyvINNpXk+2sJxx4yhAc4C84LARu1uvNIzuuWU=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=Iz7pUYIO9cUmmJZAGtQwFyKgdv2566r3bv4SQxi3TIQGQqYtLO6jVJhc5IACBt+/x85aTvHA4ouHu34cYzf7bU0I5Hf7ZBqAROXQiJ0E6WdHs7PJHYUeSYnjUqk/VfmklzCsT6iGX0im8e+MxZ593vAK0nqaO7THvjucupQeImM= ARC-Authentication-Results: i=2; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698048131; x=1729584131; h=from:to:cc:subject:date:message-id:references: in-reply-to:mime-version; bh=vXWAMlyvINNpXk+2sJxx4yhAc4C84LARu1uvNIzuuWU=; b=R2meiGa6kJqv3RvdUTdtFR5wKg0MTwll2vxL8J0//AcN2iH64fDbv5Xx aobhw/njGhSwK3rZ9obfZpPBc8oiZzaSfOym/qBdguUFLs5FiLKxqHVKn +DgYP3a1k42ZR3DFstE+BQ3UuWgb6vgcAZoRX+z82IojgCvEHWYkDeLDM ty8AMqp+zCT/UnUMj2IaQo5F/eeACPEwkJErKLQU54uMsvMyki200DnBX Ig1ZDK+6aLb2oFWMLvCT+439ugE4z4or72Cmyq969L17xs4NtivTUFolQ 2nTzKTbUdtvpfFTec2HwJu0LUuOKK0K2JjMdKBGTZOFDFskOEfmUM0mmb A==; X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="8347141" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208,217";a="8347141" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2023 01:01:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208,217";a="5993058" Received: from fmsmsx601.amr.corp.intel.com ([10.18.126.81]) by fmviesa001.fm.intel.com with ESMTP/TLS/AES256-GCM-SHA384; 23 Oct 2023 01:01:32 -0700 Received: from fmsmsx611.amr.corp.intel.com (10.18.126.91) by fmsmsx601.amr.corp.intel.com (10.18.126.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32; Mon, 23 Oct 2023 01:01:36 -0700 Received: from FMSEDG603.ED.cps.intel.com (10.1.192.133) by fmsmsx611.amr.corp.intel.com (10.18.126.91) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32 via Frontend Transport; Mon, 23 Oct 2023 01:01:36 -0700 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (104.47.57.168) by edgegateway.intel.com (192.55.55.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.32; Mon, 23 Oct 2023 01:01:12 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Qjsul817NqDnYqo+qCe7oX/moKNYu99azUlgD2DinSjkSG/OqLSdf4dDK5By9EgNvnhj0EgxGQ9d+vy4N3izObVYxJeJWf/6B+ta2G5bSrEq5PCoH4+59GHYL0vYEXjaS/1cD4cJ4RsME1lbvNG0LY6AOetd+RQVJAQjewR2xnSpalMcqei96gCKIHCyu9La4FVWwAtpSpaxzmEEv8zAxtDLxvZNHyPSNB16saNA3bewzhfUYvyvAvwyoO6MyA3CQZ9saNSBuv4JZ1toP7ZIwqCavtfPu25/Nsii7Td0bKT7n5KHCPTstSAv6jJ8Dg0sIcJCI3/6vwTEFEqGeoNXXw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=zS+cc3KL1cXDTft1BlzGzcuDAkJVIqKTDqqXG+cbbR4=; b=lJmYNUIm6icofY0te21rt0XAZn9mWNzVmRhCrIt7X/Hlt2ecfxvGRKU4HJWn790FwmT9XJu5kflRmeKMxLLxPT3zobcmqNkHVUmLf39FGlqUo7uxWq0cIPi4N/YJHxeTjbcwP0ImAWXONQmXx6hkANj+gAYQ5OokfIMpSiouMUHNzPStm37rQsFQbiOBCY7BB00YVO9AVFmxy72jrK4GS6YvIiKhvi2SZKeJfHfzm30S9mslxXYfLZZA97bSa6LdUlQdQzNDfwVOS7PXlkmYMIzQy97zCevZaiGnL7tzLWdESWmaeO8GI926x2YY/dGEJRgE0WNv1IvInlrlT3AnLA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Received: from MW5PR11MB5908.namprd11.prod.outlook.com (2603:10b6:303:194::10) by LV2PR11MB6022.namprd11.prod.outlook.com (2603:10b6:408:17c::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6907.33; Mon, 23 Oct 2023 08:01:05 +0000 Received: from MW5PR11MB5908.namprd11.prod.outlook.com ([fe80::4317:53a0:2638:358c]) by MW5PR11MB5908.namprd11.prod.outlook.com ([fe80::4317:53a0:2638:358c%5]) with mapi id 15.20.6907.032; Mon, 23 Oct 2023 08:01:04 +0000 From: "Li, Pan2" To: "juzhe.zhong@rivai.ai" , gcc-patches CC: "Wang, Yanzhang" , kito.cheng Subject: RE: [PATCH v1] RISC-V: Bugfix for merging undef tmp register for trunc Thread-Topic: [PATCH v1] RISC-V: Bugfix for merging undef tmp register for trunc Thread-Index: AQHaBYYR6wXNOvyeoUSdkhs0igO3WrBXAeJNgAABGTA= Date: Mon, 23 Oct 2023 08:01:04 +0000 Message-ID: References: <20231023075335.3063731-1-pan2.li@intel.com> <12442B971FD216D6+202310231556011001550@rivai.ai> In-Reply-To: <12442B971FD216D6+202310231556011001550@rivai.ai> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: MW5PR11MB5908:EE_|LV2PR11MB6022:EE_ x-ms-office365-filtering-correlation-id: a4054d08-3f36-49a6-9313-08dbd39e34e6 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: kV3G+6fQyFx7U7uhsOHH2XdGRkuVlDoiN57k3t4BwUwKlWwbB6eCe5g5G5rZ9d+D5Zhep5vLzFX/nGYnjMdjslNWL2ENcWqV5q0EnTVu9qj6vJ/0m7Lt/Xf9viABOiQqPukVrAqSIMAYB51vwuaN2irzYFbIb58SJzlyiAU5qQJBvAu1DMTvO/HrfqBwZvHb38OGDV4C4GjWaEQzZ/9yusBuVzf33pplK6XlYT6mtIqm830W+DYf50HkhikpLgzOIF4jTEL1GGVTlmVdmDTCc3B+/ySzH8oZeFzXSKx9kQalcS9u6KTZr0cKTw11dIaUxifdEv+14w6Nh6FkmRsah0BGVZKbT17ynFfIoR/RPg5m7aA4yvUnDPdYCnZ588+0Czp4ShxtIjPP/U3lgctWyD6ZbWaen/I+n69N6nGVJWnEUZSD+VOl0XlTE2ArkWQSePepyqWmU9puaUmUFeK3JqiWr8I0gE/E7x1u9FK0bIWTuHezEE1KYVJFFCwknh6GAyOwfnT1ymDzkUuXUJ+necxUOF0gnS6aJR8wR1Okm2XhWkJ9F1/D6MK8OVlOhcxNZ1ijoowbZ6FD3W5R6xQDEcKMol1P+2VEyZITh1W7LjqvzTy9wU4TZOX3/TNV4GB7 x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MW5PR11MB5908.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(396003)(366004)(39860400002)(376002)(136003)(346002)(230922051799003)(1800799009)(186009)(64100799003)(451199024)(55016003)(2906002)(38100700002)(110136005)(76116006)(316002)(66946007)(54906003)(66556008)(66446008)(64756008)(122000001)(82960400001)(66476007)(478600001)(6506007)(7696005)(71200400001)(9686003)(53546011)(83380400001)(41300700001)(52536014)(86362001)(5660300002)(33656002)(4326008)(8936002)(8676002)(26005)(38070700009)(4001150100001)(579004)(559001);DIR:OUT;SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?iso-2022-jp?B?SDFqdFV5VWd3M051T3c5R1RIWDVxQlVXZWlWMEdUUU5HN2xxSURoZjhy?= =?iso-2022-jp?B?MUlIV1owK1NoUzB6TzdHcU1RYWY1d2xCWG5RRmN3blJGSXBQOGRaVmI3?= =?iso-2022-jp?B?ZXd0ekl2M2wxUVhUNU13S2NJbFFYUjQ2UEprcCtnSlNBZHp6NzFCQ01I?= =?iso-2022-jp?B?eDhoZVQ2eDR1MWpheng1WEhWTkhsemdNSFpid2VQeEE2N010TFpYUDVH?= =?iso-2022-jp?B?OC9YRHVYYjBycThSRllXUjFYUWgwdXBKSXlveE1ZaVVOejBFWGJ3UktY?= =?iso-2022-jp?B?RWpPejljRDMzNzUxa2llQXEvSVRqems5eTRjcVluMjZNL0sxUFRjZU5R?= =?iso-2022-jp?B?Vy9KR2c2OE1oUkVQck1TSnkvU3FDK0o5MHhOcWQwbEUxR3hPcmZsZktX?= =?iso-2022-jp?B?SWRKTDJUS3N4dDJQdzNJZTdqWkM1L1ViSENsZHNjVi9FSDJ0S0FhMDFM?= =?iso-2022-jp?B?OHlYWkNTQXIzWDNuWFVUazlSKytmaDhYV3NWbE5NZlhFaFA3bzVhSCs4?= =?iso-2022-jp?B?aUpLL0dkN3U1Y2pHS1VaU0tWRXBXc3FiK2dxZmpnVk9MQWh2WFhKZ1Fo?= =?iso-2022-jp?B?cmlqTGh0Yjl6clZnTFRaWCtINDgzK2JjT1h3S2dXVkdCa1RRVmY5MjF4?= =?iso-2022-jp?B?dDlRR1M2TlBaQWs1aERhNDBLbDVuaUFsL1ovaEEvWVZ0Z3h5L2pUb01w?= =?iso-2022-jp?B?WUFWSHkzU3NaTXEzV01kQVhMVWQrZC93azhJUXAxRnljT0RYKzd2QUJz?= =?iso-2022-jp?B?dTNhZVVGOEpMQndUM1c3UDZFbTFGM1FJZU1xNFp1cEk4ZHQ4TW9RR25a?= =?iso-2022-jp?B?eEZUQzRUQlloQkttVFQyOTRKZExLNktaUWZURGYzb0VWcTFldGNHRjFh?= =?iso-2022-jp?B?QWRuL3pIVER3VWRxQ0lGTjZNR1VJS0k5cDZ2eFJBTmI5NXY1VUYwS0FE?= =?iso-2022-jp?B?T1g4VWdGakNDd1ZPZm9rbkFQTkJTWXhkRmxzOTEyaTAzTStKRTJRV3Q4?= =?iso-2022-jp?B?SlZjM0I3ZTNwWnhOdStpMTF4d3ZkbnJaTkdZemg5cFVvRVBsM1UyeHBU?= =?iso-2022-jp?B?NFBYblREKzNML0FaOXpCUEZuYmdDMThLby9xTWUyTGhLeWplWWVvMUg0?= =?iso-2022-jp?B?N2FkUVVFTXhwakhKM0FVUGp3Zy8rMisrUGxkdnRSTE1INlluckZJdTlQ?= =?iso-2022-jp?B?M2dIYkdaMk1CVkVSZmxvMThYdnVNb2N2VUhHV1loeERKVVZidzRWdHBv?= =?iso-2022-jp?B?YkhrSHAyZ3lCVmhTNnNLSHB1Q0FibFJXSW1kOXh2dUZkSGpUL3V3VTJp?= =?iso-2022-jp?B?dlpXODdDUzFOaFdtaXZ1b2RaNko3T0dNcjhvaWJJVnA2Mmc1SGtKeldl?= =?iso-2022-jp?B?elhUUHZoaTJWRTNFdVBkczl6S3RITTk5dWRHMDdpYmEwbDJ4ZFl4NWlT?= =?iso-2022-jp?B?cFNPaVB6RUtuVWVzUTlsT1FtRnZWWm4vRGl4NjlpL3EvZVNqTlJRYTJM?= =?iso-2022-jp?B?NVRqaEM2Z2ZrM3kyU29FTEZRSEFKVkVmcGsvL29XajFBckJseXlxcDdQ?= =?iso-2022-jp?B?N1ZiUFNMRjEydmM5ejdLaGRNZEZNY2tqcmRLSUs4Rm1sRTlGSUhpTDVT?= =?iso-2022-jp?B?NVJlOHZoMEljOTF2dk1ZT0tXcEgwdE1rc3VTU0FzV2RnR1V3Y3pYanJF?= =?iso-2022-jp?B?RkwzUnkrbUJJQXpxdnRMWU92bXR2a3VYVGN2M2ZFKzlQM1ZlUlBacmky?= =?iso-2022-jp?B?bFJkeXJTM1E3WjhDWnQ0d1NCeE9WYkhHM0U2eHFDSHhydTNFWU5WT2xj?= =?iso-2022-jp?B?djV0V2xGVzFGMk9mSEVGV3hDendqdlQ3WmcwMzdla0lUbnB1SU9IbnhQ?= =?iso-2022-jp?B?eFN2dmNSb3p3SjVRSEcyUXRqTTlUWTlCMjc2QlQvZXpqemNUbitPNlda?= =?iso-2022-jp?B?aFZwLzF3NDE2U0Y2cmlXSGI0Wkx6UnkxQ0NtZ3crQTNkSVNFRmhZRGF0?= =?iso-2022-jp?B?dEJvOWF5UnlmV1NKdmlCME5QSVM4U3hsUFRXSEMwbTRFams5ZzFLeHo2?= =?iso-2022-jp?B?V01DTjZhWHp0aWhhVFNXTjdYV2NmSzNRcjlpUWNBOU9teGJSMHlNVFlM?= =?iso-2022-jp?B?YmhFNEtVaEU1NmNlTzRsK01nLzBJN3QyWHhSajVDSEZNNlpIQ3JRNk5G?= =?iso-2022-jp?B?U3lhZjZPa1hnME11MDdOWTB4cVNHaGlKdDNZZjhBSXJoc1lVNUd5R3BL?= =?iso-2022-jp?B?a3A3SmtyOVRNN05vWjVhOGdicXZFdnhndz0=?= Content-Type: multipart/alternative; boundary="_000_MW5PR11MB59088293628E3CED8A8C213FA9D8AMW5PR11MB5908namp_" MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MW5PR11MB5908.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: a4054d08-3f36-49a6-9313-08dbd39e34e6 X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Oct 2023 08:01:04.8585 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: n8kIFACAl0kx/89jiABW0MIQJYdj3TI9QgE78UlTpaxBI3fb7PqUHrV+vdfNU6EuQxK59vxxuUP1HkAsGImwIw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR11MB6022 X-OriginatorOrg: intel.com X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,HTML_MESSAGE,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --_000_MW5PR11MB59088293628E3CED8A8C213FA9D8AMW5PR11MB5908namp_ Content-Type: text/plain; charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable Committed, thanks Juzhe. Pan From: juzhe.zhong@rivai.ai Sent: Monday, October 23, 2023 3:56 PM To: Li, Pan2 ; gcc-patches Cc: Li, Pan2 ; Wang, Yanzhang ;= kito.cheng Subject: Re: [PATCH v1] RISC-V: Bugfix for merging undef tmp register for t= runc LGTM=1B$B!#=1B(B ________________________________ juzhe.zhong@rivai.ai From: pan2.li Date: 2023-10-23 15:53 To: gcc-patches CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng Subject: [PATCH v1] RISC-V: Bugfix for merging undef tmp register for trunc From: Pan Li > For trunc function autovec, there will be one step like below take MU for the merge operand. rtx tmp =3D gen_reg_rtx (vec_int_mode); emit_vec_cvt_x_f_rtz (tmp, op_1, mask, vec_fp_mode); The MU will leave the tmp (aka dest register) register unmasked elements unchanged and it is undefined here. This patch would like to adjust the MU to MA. gcc/ChangeLog: * config/riscv/riscv-v.cc (emit_vec_cvt_x_f_rtz): Add insn type arg. (expand_vec_trunc): Take MA instead of MU for cvt_x_f_rtz. Signed-off-by: Pan Li > --- gcc/config/riscv/riscv-v.cc | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 91ad6a61fa8..fb6a4e561db 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -4144,12 +4144,20 @@ emit_vec_cvt_f_x (rtx op_dest, rtx op_src, rtx mask, static void emit_vec_cvt_x_f_rtz (rtx op_dest, rtx op_src, rtx mask, - machine_mode vec_mode) + insn_type type, machine_mode vec_mode) { - rtx cvt_x_ops[] =3D {op_dest, mask, op_dest, op_src}; insn_code icode =3D code_for_pred (FIX, vec_mode); - emit_vlmax_insn (icode, UNARY_OP_TAMU, cvt_x_ops); + if (type & USE_VUNDEF_MERGE_P) + { + rtx cvt_x_ops[] =3D {op_dest, mask, op_src}; + emit_vlmax_insn (icode, type, cvt_x_ops); + } + else + { + rtx cvt_x_ops[] =3D {op_dest, mask, op_dest, op_src}; + emit_vlmax_insn (icode, type, cvt_x_ops); + } } void @@ -4285,7 +4293,7 @@ expand_vec_trunc (rtx op_0, rtx op_1, machine_mode ve= c_fp_mode, /* Step-3: Convert to integer on mask, rounding to zero (aka truncate). = */ rtx tmp =3D gen_reg_rtx (vec_int_mode); - emit_vec_cvt_x_f_rtz (tmp, op_1, mask, vec_fp_mode); + emit_vec_cvt_x_f_rtz (tmp, op_1, mask, UNARY_OP_TAMA, vec_fp_mode); /* Step-4: Convert to floating-point on mask for the rint result. */ emit_vec_cvt_f_x (op_0, tmp, mask, UNARY_OP_TAMU_FRM_DYN, vec_fp_mode); -- 2.34.1 --_000_MW5PR11MB59088293628E3CED8A8C213FA9D8AMW5PR11MB5908namp_--