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Thread-Topic: [PATCH v5] RISC-V: Refactor requirement of ZVFH and ZVFHMIN. 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Thanks Juzhe for reviewing. I see, this way may have even smaller code chan= ge which treats the zvfhmin as minimal base sub extension. I will have a try for PATCH V6. Pan From: juzhe.zhong@rivai.ai Sent: Wednesday, June 7, 2023 4:27 PM To: Li, Pan2 ; gcc-patches Cc: Robin Dapp ; jeffreyalaw ; = Li, Pan2 ; Wang, Yanzhang Subject: Re: [PATCH v5] RISC-V: Refactor requirement of ZVFH and ZVFHMIN. In this patch, you add TARGET_ZVFH into VF iterator which is not correct. When TARGET_ZVFH is true, TARGET_ZVFHMIN is always true. For vfadd, it is true we should enable "vfadd" for TARGET_ZVFH For vle16, we should enable for TARGET_ZVFHMIN. This patch will disable both "vle16" and "vfadd" for FP16 on ZVFHMIN which = is not correct. I think you should allow all FP16 vector modes in iterator enable by TARGET= _VECTOR_FP_ELN_16 (TARGET_ZVFHMIN). Then, when zvfhmin is enabled, all FP16 instructions are enabled by default. To gate the situation only enable when TARGET_ZVFH, you add the predicate a= s below: For example: vfadd.vv (need (define_insn "@pred_" [(set (match_operand:VF 0 "register_operand" "=3Dvd, vd, vr, vr= ") (if_then_else:VF (unspec: [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") (match_operand 6 "const_int_operand" " i, i, i, i") (match_operand 7 "const_int_operand" " i, i, i, i") (match_operand 8 "const_int_operand" " i, i, i, i") (match_operand 9 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (any_float_binop:VF (match_operand:VF 3 "register_operand" " vr, vr, vr, vr") (match_operand:VF 4 "register_operand" " vr, vr, vr, vr")) (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)" "vf.vv\t%0,%3,%4%p1" [(set_attr "type" "") (set_attr "mode" "")]) bool float_mode_supported_p (machine_mode mode) { if (GET_MODE_INNER (mode) =3D=3D HFmode) return TARGET_ZVFH; return true; } ________________________________ juzhe.zhong@rivai.ai From: pan2.li Date: 2023-06-07 16:06 To: gcc-patches CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang Subject: [PATCH v5] RISC-V: Refactor requirement of ZVFH and ZVFHMIN. From: Pan Li > This patch would like to refactor the requirement of both the ZVFH and ZVFHMIN. The related define_insn and iterator will take the requirement based on the ZVFHMIN and ZVFH. Please note the ZVFH will cover the ZVFHMIN instructions. This patch add one test for this. Signed-off-by: Pan Li > gcc/ChangeLog: * config/riscv/vector-iterators.md: Add requirement to VF, VWEXTF and VWCONVERTI, add V_CONVERT_F and VCONVERTF. * config/riscv/vector.md: Adjust FP convert to V_CONVERT_F and VCONVERTF, and fix V_WHOLE and V_FRACT. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: New test. --- gcc/config/riscv/vector-iterators.md | 79 +++++++++++++------ gcc/config/riscv/vector.md | 46 +++++------ .../riscv/rvv/base/zvfh-over-zvfhmin.c | 25 ++++++ 3 files changed, 104 insertions(+), 46 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmi= n.c diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector= -iterators.md index f4946d84449..e6c2ecf7c86 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -296,13 +296,13 @@ (define_mode_iterator VWI_ZVE32 [ ]) (define_mode_iterator VF [ - (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") - (VNx2HF "TARGET_VECTOR_ELEN_FP_16") - (VNx4HF "TARGET_VECTOR_ELEN_FP_16") - (VNx8HF "TARGET_VECTOR_ELEN_FP_16") - (VNx16HF "TARGET_VECTOR_ELEN_FP_16") - (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") - (VNx64HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >=3D 128") + (VNx1HF "TARGET_ZVFH && TARGET_MIN_VLEN < 128") + (VNx2HF "TARGET_ZVFH") + (VNx4HF "TARGET_ZVFH") + (VNx8HF "TARGET_ZVFH") + (VNx16HF "TARGET_ZVFH") + (VNx32HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32") + (VNx64HF "TARGET_ZVFH && TARGET_MIN_VLEN >=3D 128") (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128") (VNx2SF "TARGET_VECTOR_ELEN_FP_32") @@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [ (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGE= T_VECTOR_ELEN_64") (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16= DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >=3D 128") - (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") - (VNx2HF "TARGET_VECTOR_ELEN_FP_16") - (VNx4HF "TARGET_VECTOR_ELEN_FP_16") + (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN =3D=3D 32") + (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN =3D=3D 64") (VNx8HF "TARGET_VECTOR_ELEN_FP_16") (VNx16HF "TARGET_VECTOR_ELEN_FP_16") (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") @@ -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [ (define_mode_iterator V_FRACT [ (VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 32") = (VNx8QI "TARGET_MIN_VLEN >=3D 128") (VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI= "TARGET_MIN_VLEN >=3D 128") - (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF= "TARGET_MIN_VLEN >=3D 128") + + (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") + (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") + (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >=3D 128") + (VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARGET= _MIN_VLEN >=3D 128") (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MIN_= VLEN < 128") (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >=3D 128") @@ -497,12 +500,12 @@ (define_mode_iterator VWEXTI [ ]) (define_mode_iterator VWEXTF [ - (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128") - (VNx2SF "TARGET_VECTOR_ELEN_FP_32") - (VNx4SF "TARGET_VECTOR_ELEN_FP_32") - (VNx8SF "TARGET_VECTOR_ELEN_FP_32") - (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") - (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >=3D 128") + (VNx1SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 12= 8") + (VNx2SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32") + (VNx4SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32") + (VNx8SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32") + (VNx16SF "TARGET_ZVFH && TARGET_MIN_VLEN > 32") + (VNx32SF "TARGET_ZVFH && TARGET_MIN_VLEN >=3D 128") (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128") (VNx2DF "TARGET_VECTOR_ELEN_FP_64") @@ -512,12 +515,12 @@ (define_mode_iterator VWEXTF [ ]) (define_mode_iterator VWCONVERTI [ - (VNx1SI "TARGET_MIN_VLEN < 128 && TARGET_VECTOR_ELEN_FP_16") - (VNx2SI "TARGET_VECTOR_ELEN_FP_16") - (VNx4SI "TARGET_VECTOR_ELEN_FP_16") - (VNx8SI "TARGET_VECTOR_ELEN_FP_16") - (VNx16SI "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16") - (VNx32SI "TARGET_MIN_VLEN >=3D 128 && TARGET_VECTOR_ELEN_FP_16") + (VNx1SI "TARGET_ZVFH && TARGET_MIN_VLEN < 128") + (VNx2SI "TARGET_ZVFH") + (VNx4SI "TARGET_ZVFH") + (VNx8SI "TARGET_ZVFH") + (VNx16SI "TARGET_ZVFH && TARGET_MIN_VLEN > 32") + (VNx32SI "TARGET_ZVFH && TARGET_MIN_VLEN >=3D 128") (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN= _VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32") @@ -526,6 +529,21 @@ (define_mode_iterator VWCONVERTI [ (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MI= N_VLEN >=3D 128") ]) +(define_mode_iterator VCONVERTF [ + (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_= MIN_VLEN < 128") + (VNx2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32") + (VNx4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32") + (VNx8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32") + (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET= _MIN_VLEN > 32") + (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET= _MIN_VLEN >=3D 128") + + (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128") + (VNx2DF "TARGET_VECTOR_ELEN_FP_64") + (VNx4DF "TARGET_VECTOR_ELEN_FP_64") + (VNx8DF "TARGET_VECTOR_ELEN_FP_64") + (VNx16DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >=3D 128") +]) + (define_mode_iterator VQEXTI [ (VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI VNx8SI (VNx16SI "TARGET_M= IN_VLEN > 32") (VNx32SI "TARGET_MIN_VLEN >=3D 128") (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGE= T_VECTOR_ELEN_64") @@ -1181,6 +1199,21 @@ (define_mode_attr V_DOUBLE_TRUNC [ (VNx16DF "VNx16SF") ]) +(define_mode_attr V_CONVERT_F [ + (VNx1SF "VNx1HF") + (VNx2SF "VNx2HF") + (VNx4SF "VNx4HF") + (VNx8SF "VNx8HF") + (VNx16SF "VNx16HF") + (VNx32SF "VNx32HF") + + (VNx1DF "VNx1SF") + (VNx2DF "VNx2SF") + (VNx4DF "VNx4SF") + (VNx8DF "VNx8SF") + (VNx16DF "VNx16SF") +]) + (define_mode_attr V_QUAD_TRUNC [ (VNx1SI "VNx1QI") (VNx2SI "VNx2QI") (VNx4SI "VNx4QI") (VNx8SI "VNx8QI") (VNx16SI "VNx16QI") (VNx32SI "VNx32QI") diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 1d1847bd85a..97162b07642 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -7106,23 +7106,23 @@ (define_insn "@pred_widen_" (set_attr "mode" "")]) (define_insn "@pred_extend" - [(set (match_operand:VWEXTF 0 "register_operand" "=3D&vr= , &vr") - (if_then_else:VWEXTF + [(set (match_operand:VCONVERTF 0 "register_operand" "=3D&vr, &= vr") + (if_then_else:VCONVERTF (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 4 "vector_length_operand" " rK, rK") - (match_operand 5 "const_int_operand" " i, i") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 4 "vector_length_operand" " rK, rK") + (match_operand 5 "const_int_operand" " i, i") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (float_extend:VWEXTF - (match_operand: 3 "register_operand" " vr, vr")) - (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0"))= )] + (float_extend:VCONVERTF + (match_operand: 3 "register_operand" " vr, vr")) + (match_operand:VCONVERTF 2 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "vfwcvt.f.f.v\t%0,%3%p1" [(set_attr "type" "vfwcvtftof") - (set_attr "mode" "")]) + (set_attr "mode" "")]) ;; ------------------------------------------------------------------------= ------- ;; ---- Predicated floating-point narrow conversions @@ -7193,25 +7193,25 @@ (define_insn "@pred_narrow_" (set_attr "mode" "")]) (define_insn "@pred_trunc" - [(set (match_operand: 0 "register_operand" "=3Dvd,= vd, vr, vr, &vr, &vr") - (if_then_else: + [(set (match_operand: 0 "register_operand" "=3Dvd, vd= , vr, vr, &vr, &vr") + (if_then_else: (unspec: - [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,W= c1,vmWc1,vmWc1") - (match_operand 4 "vector_length_operand" " rK, rK, rK, = rK, rK, rK") - (match_operand 5 "const_int_operand" " i, i, i, = i, i, i") - (match_operand 6 "const_int_operand" " i, i, i, = i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, = i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, = i, i, i") + [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,= vmWc1,vmWc1") + (match_operand 4 "vector_length_operand" " rK, rK, rK, rK,= rK, rK") + (match_operand 5 "const_int_operand" " i, i, i, i,= i, i") + (match_operand 6 "const_int_operand" " i, i, i, i,= i, i") + (match_operand 7 "const_int_operand" " i, i, i, i,= i, i") + (match_operand 8 "const_int_operand" " i, i, i, i,= i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) - (float_truncate: - (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, = 0, vr, vr")) - (match_operand: 2 "vector_merge_operand" " vu, 0, vu, = 0, vu, 0")))] + (float_truncate: + (match_operand:VCONVERTF 3 "register_operand" " 0, 0, 0, 0,= vr, vr")) + (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0,= vu, 0")))] "TARGET_VECTOR" "vfncvt.f.f.w\t%0,%3%p1" [(set_attr "type" "vfncvtftof") - (set_attr "mode" "")]) + (set_attr "mode" "")]) (define_insn "@pred_rod_trunc" [(set (match_operand: 0 "register_operand" "=3Dvd,= vd, vr, vr, &vr, &vr") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/= gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c new file mode 100644 index 00000000000..32d6657775c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-march=3Drv64gcv_zvfh -mabi=3Dlp64 -O3" } */ + +#include "riscv_vector.h" + +vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) { + return __riscv_vfncvt_f_f_w_f16mf4(src, vl); +} + +vfloat16m4_t test_vfncvt_f_f_w_f16m4(vfloat32m8_t src, size_t vl) { + return __riscv_vfncvt_f_f_w_f16m4(src, vl); +} + +vfloat32mf2_t test_vfwcvt_f_f_v_f32mf2(vfloat16mf4_t src, size_t vl) { + return __riscv_vfwcvt_f_f_v_f32mf2(src, vl); +} + +vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) { + return __riscv_vfwcvt_f_f_v_f32m8(src, vl); +} + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\= s*mf4,\s*t[au],\s*m[au]} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\= s*m4,\s*t[au],\s*m[au]} 2 } } */ +/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+= } 2 } } */ +/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+= } 2 } } */ -- 2.34.1 --_000_MW5PR11MB5908972148C13AA32DFB8D26A953AMW5PR11MB5908namp_--