Committed, thanks Juzhe. Pan From: juzhe.zhong@rivai.ai Sent: Friday, December 8, 2023 4:03 PM To: Li, Pan2 ; gcc-patches Cc: Li, Pan2 ; Wang, Yanzhang ; kito.cheng Subject: Re: [PATCH v1] RISC-V: Fix ICE for incorrect mode attr in V_F2DI_CONVERT_BRIDGE LGTM. ________________________________ juzhe.zhong@rivai.ai From: pan2.li Date: 2023-12-08 16:00 To: gcc-patches CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng Subject: [PATCH v1] RISC-V: Fix ICE for incorrect mode attr in V_F2DI_CONVERT_BRIDGE From: Pan Li > The mode attr V_F2DI_CONVERT_BRIDGE converts the floating-point mode to the widden floating-point by design. But we take (RVVM1HF "RVVM2SI") by mistake. This patch would like to fix it by replacing the (RVVM1HF "RVVM2SI") to (RVVM1HF "RVVM2SF") as design. gcc/ChangeLog: * config/riscv/vector-iterators.md: Replace RVVM2SI to RVVM2SF for mode attr V_F2DI_CONVERT_BRIDGE. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv64-ice-1.c: New test. Signed-off-by: Pan Li > --- gcc/config/riscv/vector-iterators.md | 2 +- .../riscv/rvv/autovec/unop/math-lroundf16-rv64-ice-1.c | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv64-ice-1.c diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 56080ed1f5f..5f5f7b5b986 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -3267,7 +3267,7 @@ (define_mode_attr v_f2di_convert [ ]) (define_mode_attr V_F2DI_CONVERT_BRIDGE [ - (RVVM2HF "RVVM4SF") (RVVM1HF "RVVM2SI") (RVVMF2HF "RVVM1SF") + (RVVM2HF "RVVM4SF") (RVVM1HF "RVVM2SF") (RVVMF2HF "RVVM1SF") (RVVMF4HF "RVVMF2SF") (RVVM4SF "VOID") (RVVM2SF "VOID") (RVVM1SF "VOID") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv64-ice-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv64-ice-1.c new file mode 100644 index 00000000000..5fb61c7b44c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv64-ice-1.c @@ -0,0 +1,7 @@ +/* Test that we do not have ice when compile */ +/* { dg-do compile } */ +/* { dg-options "--param=riscv-autovec-lmul=m4 -march=rv64gcv_zvfh_zfh -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "test-math.h" + +TEST_UNARY_CALL_CVT (_Float16, long, __builtin_lroundf16) -- 2.34.1